[Mesa-dev] [PATCH 08/16] ac/nir: Expand user SGPR descriptions a bit.

To prevent VS/TCS collisions in merged shaders. --- src/amd/common/ac_nir_to_llvm.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/amd/common/ac_nir_to_llvm.h b/src/amd/common/ac_nir_to_llvm.h index 66d539dec47..360d613d58d 100644 --- a/src/amd/common/ac_nir_to_llvm.

[Mesa-dev] [PATCH 03/16] ac/nir: Change interface to allow multiple source shaders.

--- src/amd/common/ac_nir_to_llvm.c | 82 ++--- src/amd/common/ac_nir_to_llvm.h | 3 +- src/amd/vulkan/radv_shader.c| 2 +- 3 files changed, 48 insertions(+), 39 deletions(-) diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c i

[Mesa-dev] [PATCH 02/16] ac/nir: Add HS calling convention.

Needed for GFX9 merged shaders. --- src/amd/common/ac_nir_to_llvm.c | 5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c index 3ba3ebf051e..1df97b59a2e 100644 --- a/src/amd/common/ac_nir_to_llvm.c +++ b/src/amd/co

[Mesa-dev] [PATCH 10/16] ac/nir: Add LS-HS input VGPR workaround.

--- src/amd/common/ac_nir_to_llvm.c | 18 ++ 1 file changed, 18 insertions(+) diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c index cb011bd88bb..242675654d2 100644 --- a/src/amd/common/ac_nir_to_llvm.c +++ b/src/amd/common/ac_nir_to_llvm.c @@ -6377,6

[Mesa-dev] [PATCH 16/16] radv: Modify rsrc1/rsrc2 generation for merged tess.

No OC_LDS_EN for HS, and the included LS vgpr_comp_cnt is at a different offset. --- src/amd/vulkan/radv_shader.c | 23 --- 1 file changed, 16 insertions(+), 7 deletions(-) diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c index a7836543998..a86ba2a01c0

[Mesa-dev] [PATCH 09/16] ac/nir: Compile the bodies of multiple shaders.

--- src/amd/common/ac_nir_to_llvm.c | 133 +--- 1 file changed, 83 insertions(+), 50 deletions(-) diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c index 67945a353e8..cb011bd88bb 100644 --- a/src/amd/common/ac_nir_to_llvm.c +++ b/sr

[Mesa-dev] [PATCH 12/16] radv: Update GFX9 user data regs for GS/tess.

--- src/amd/vulkan/radv_cmd_buffer.c | 14 +++--- src/amd/vulkan/radv_pipeline.c | 2 +- src/amd/vulkan/radv_shader.c | 19 +++ src/amd/vulkan/radv_shader.h | 4 ++-- 4 files changed, 25 insertions(+), 14 deletions(-) diff --git a/src/amd/vulkan/radv_cmd_buffer

[Mesa-dev] [PATCH 14/16] radv: Add GFX9 HS emitting code.

--- src/amd/vulkan/radv_cmd_buffer.c | 21 - 1 file changed, 16 insertions(+), 5 deletions(-) diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index 3e31fbafd34..a746777ca40 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv

[Mesa-dev] [PATCH 13/16] radv: Remove remaining hard coded references to VS.

--- src/amd/vulkan/radv_cmd_buffer.c | 19 ++- src/amd/vulkan/radv_pipeline.c | 14 -- src/amd/vulkan/radv_private.h| 2 ++ 3 files changed, 28 insertions(+), 7 deletions(-) diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index 7

[Mesa-dev] [PATCH 15/16] radv: Set correct registers for merged shader rings.

We need different regs to end up in s0/s1. --- src/amd/vulkan/radv_device.c | 36 1 file changed, 24 insertions(+), 12 deletions(-) diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c index fd705fe726d..125498809ec 100644 --- a/src/amd/vul

Re: [Mesa-dev] [PATCH] radv: fix CLEAR_STATE packet length.

Reviewed-by: Bas Nieuwenhuizen On Thu, Oct 19, 2017 at 5:54 AM, Dave Airlie wrote: > From: Dave Airlie > > Looking at shader traces I noticed some registers were missing, > one of them was being eaten by the wrong clear state length. > > Fixes: 4f42ea4dc (radv: use CLEAR_STAT

Re: [Mesa-dev] [PATCH] radv: move DB_COUNT_CONTROL initialization to si_emit_config()

r-b On Thu, Oct 19, 2017 at 4:25 PM, Samuel Pitoiset wrote: > CLEAR_STATE will initialize DB_COUNT_CONTROL to 0 for CIK+. > > Signed-off-by: Samuel Pitoiset > --- > src/amd/vulkan/radv_cmd_buffer.c | 1 - > src/amd/vulkan/si_cmd_buffer.c | 5 + > 2 files changed, 5 insertions(+), 1 deleti

Re: [Mesa-dev] [PATCH 3/3] radv: re-emit VGT_INDEX_TYPE because non-indexed draws overwrite it

r-b for the series. MAybe add a fixes tag? On Thu, Oct 19, 2017 at 12:35 PM, Samuel Pitoiset wrote: > Only on CIK and later. We should only update VGT_INDEX_TYPE but > it seems easier to re-emit all the index buffer packets. > > Signed-off-by: Samuel Pitoiset > --- > src/amd/vulkan/radv_cmd_buf

Re: [Mesa-dev] [PATCH 2/2] radv: copy indirect lowering settings from radeonsi

Reviewed-by: Bas Nieuwenhuizen as well. On Thu, Oct 19, 2017 at 12:27 AM, Timothy Arceri wrote: > It looks the original indirect mask was probably copied from > ANV. > > Sascha Willems demo results: > > tessellation ~4000 -> ~4200 fps > > V2: continue lowering

Re: [Mesa-dev] [PATCH 8/9] radv: add radv_emit_shaders_prefetch()

On Tue, Oct 17, 2017 at 11:03 AM, Samuel Pitoiset wrote: > Signed-off-by: Samuel Pitoiset > --- > src/amd/vulkan/radv_cmd_buffer.c | 38 ++ > 1 file changed, 26 insertions(+), 12 deletions(-) > > diff --git a/src/amd/vulkan/radv_cmd_buffer.c > b/src/amd/vulka

Re: [Mesa-dev] [PATCH 1/2] radv: be smarter with descriptors when emitting secondary buffers

On Wed, Oct 11, 2017 at 5:18 PM, Samuel Pitoiset wrote: > If the secondary buffers don't use any descriptors we don't > have to re-emit the ones from the primary command buffer. > > Signed-off-by: Samuel Pitoiset > --- > src/amd/vulkan/radv_cmd_buffer.c | 29 - > 1 fi

Re: [Mesa-dev] [PATCH] radv: don't flush the VS when srcStageMask == TOP_OF_PIPE_BIT

Reviewed-by: Bas Nieuwenhuizen On Thu, Oct 19, 2017 at 8:54 PM, Fredrik Höglund wrote: > The Vulkan specification says: > >"... an execution dependency with only VK_PIPELINE_STAGE_TOP_OF_- > PIPE_BIT in the source stage mask will effectively not wait for > a

[Mesa-dev] [PATCH 2/2] radv: Enable tessellation shaders for GFX9.

It mostly works now. --- src/amd/vulkan/radv_device.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c index 7f306db5c48..125498809ec 100644 --- a/src/amd/vulkan/radv_device.c +++ b/src/amd/vulkan/radv_device.c @@ -429,

[Mesa-dev] [PATCH 1/2] ac/nir: init full exec mask for merged shaders.

From: Dave Airlie Signed-off-by: Bas Nieuwenhuizen --- src/amd/common/ac_llvm_build.c | 8 src/amd/common/ac_llvm_build.h | 1 + src/amd/common/ac_nir_to_llvm.c | 3 +++ 3 files changed, 12 insertions(+) diff --git a/src/amd/common/ac_llvm_build.c b/src/amd/common/ac_llvm_build.c

Re: [Mesa-dev] [PATCH] meson: bump libdrm_amdgpu requirement to 2.4.85

woops, r-b. Thanks. On Sat, Oct 21, 2017 at 1:30 AM, Dylan Baker wrote: > fixes: b60372570323243ec73 ("configure.ac: Bump libdrm_amdgpu version to > 2.4.85.") > cc: Bas Nieuwenhuizen > Signed-off-by: Dylan Baker > --- > meson.build | 2 +- > 1 file chan

[Mesa-dev] [PATCH 2/2] ac/nir: Set larged wrokgroup size for GS on GFX9.

They don't take a single wave anymore and we need the barriers. Fixes: 6bc42855f92 'radv: enable GS on GFX9' --- src/amd/common/ac_nir_to_llvm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c index 02420f46966.

[Mesa-dev] [PATCH 1/2] ac/nir: Take the max workgroup size of all provided shaders.

Fixes: ffaf4d608a1 'radv: Enable tessellation shaders for GFX9.' --- src/amd/common/ac_nir_to_llvm.c | 7 ++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c index 61ffe91eafd..02420f46966 100644 --- a/src/amd/comm

Re: [Mesa-dev] [PATCH] radv: Fix pipeline cache locking issues

For radv_create_shader_variants_from_pipeline_cache I'm not really sure why this would cause corruption. Yes we might create the variants a few times too much, but that should not cause any corruption. Either way, it is a fix, so Reviewed-by: Bas Nieuwenhuizen and pushed. Thanks. On Thu

[Mesa-dev] [PATCH 2/3] radv: Keep RADV_CMD_DIRTY_INDEX_BUFFER.

Otherwise for non-indexed draws we set and immediately unset it. Fixes: 341529dbee5 'radv: use optimal packet order for draws' --- src/amd/vulkan/radv_cmd_buffer.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer

[Mesa-dev] [PATCH 1/3] radv: Correctly detect changed shaders for vertex descriptors.

As they were emitted after the new pipeline, the changed pipeline detection was not working anymore. Fixes: 341529dbee5 'radv: use optimal packet order for draws' --- src/amd/vulkan/radv_cmd_buffer.c | 12 ++-- 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/src/amd/vulkan/r

[Mesa-dev] [PATCH 3/3] radv: Don't explicitly reference vertex shader for draw_id.

With merged shaders the vertex shader may not exist. This got in because the offending patch was written before merged shaders were upstream, but committed after. Fixes: 75dfab24a2c 'radv: refactor indirect draws with radv_draw_info' --- src/amd/vulkan/radv_cmd_buffer.c | 2 +- 1 file changed, 1

[Mesa-dev] [PATCH] radv: Don't check for max GL GS invocations.

We specify 127 instead of 32 as the limit in vulkan. Fixes: 6bc42855f92 'radv: enable GS on GFX9' --- src/amd/vulkan/radv_pipeline.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index eac4456a3fb..db550811eaf 100644 --- a/src

[Mesa-dev] [PATCH] radv: Don't compile shaders when they are cached already.

When the gs_copy_shader is NULL (due to an incomplete cache), but the main shaders are found, we still do the nir, but we shouldn't compile the shaders again. For merged shaders we should also account for the missing shaders. Fixes: ce03c119ce0 'radv: Add code to compile merged shaders.' --- src/

[Mesa-dev] [PATCH] ac/nir: Account for compact array index in GS input load from LDS.

Mirrors the vram path. Fixes: d4ecc3c9299 'ac/nir: Add loading from LDS for merged GS.' --- src/amd/common/ac_nir_to_llvm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c index ca856bb2f9e..83b49b535c6 100644 -

[Mesa-dev] [PATCH] radv: Don't use vgpr indexing for outputs on GFX9.

Due to LLVM bugs. Fixes a bunch of dEQP-VK.glsl.indexing.* tests. --- src/amd/vulkan/radv_shader.c | 5 + 1 file changed, 5 insertions(+) diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c index e572f693203..07e68d6032b 100644 --- a/src/amd/vulkan/radv_shader.c +++ b/src

[Mesa-dev] [PATCH 1/2] ac/nir: Fix nir_texop_lod on GFX for 1D arrays.

Fixes: 1bcb953e166 'radv: handle GFX9 1D textures' --- src/amd/common/ac_nir_to_llvm.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c index 83b49b535c6..473dd67355b 100644 --- a/src/amd/common/ac_nir_to_llvm.

[Mesa-dev] [PATCH 2/2] radv: Disallow indirect outputs for GS on GFX9 as well.

Since it also uses the output vector before writing to memory. Fixes: e38685cc62e 'Revert "radv: disable support for VEGA for now."' --- src/amd/vulkan/radv_shader.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c

Re: [Mesa-dev] [PATCH] radv/ac/nir: only emit tess factors to storage if tes reads them

r-b (though I suppose now that we have linking, we should probably rework keys too, since we'll have lots of pre-ac info to pass along that are not needed for the cache hashing.) On Sun, Oct 22, 2017 at 10:59 PM, Dave Airlie wrote: > From: Dave Airlie > > Otherwise we just need to write them to

[Mesa-dev] [PATCH] ac/nir: Only clamp shadow reference on radeonsi.

Vulkan CTS does not expect the value to be clamped (at least for D32), and it makes a differences even though depth is in [0,1], due to strict inequalities. I couldn't find anything in the Vulkan spec about this, but the test seemed to be copied from GL tests and the GL spec only specifies clampin

Re: [Mesa-dev] [PATCH] radv: move nir print after linking is done

r-b On Tue, Oct 24, 2017 at 12:59 AM, Timothy Arceri wrote: > We now have linking optimisation so we want to delay dumping the > nir until after these are complete. > > Fixes: 06f05040eb73 (radv: Link shaders) > --- > src/amd/vulkan/radv_pipeline.c | 9 +++-- > src/amd/vulkan/radv_shader.c

Re: [Mesa-dev] [PATCH] radv: only emit dfsm packets if dfsm is allowed.

r-b On Tue, Oct 24, 2017 at 5:04 AM, Dave Airlie wrote: > From: Dave Airlie > > radeonsi only emits these when dfsm is enabled, so for now > just hinge them on a flag we never set. > > Signed-off-by: Dave Airlie > --- > src/amd/vulkan/radv_cmd_buffer.c | 6 +++--- > src/amd/vulkan/radv_private

Re: [Mesa-dev] [PATCH] radv: print NIR before LLVM IR and disassembly

yay, bikeshedding. Fair enough though, r-b. On Tue, Oct 24, 2017 at 5:23 PM, Samuel Pitoiset wrote: > It's still printed after linking, but it makes more sense to > have SPIRV->NIR->LLVM IR->ASM. > > Fixes: f0a2bbd1a4 (radv: move nir print after linking is done) > Signed-off-by: Samuel Pitoiset

Re: [Mesa-dev] [PATCH] radv: allow to use a compute shader for resetting the query pool

Can you run this through CTS? Kind of worried about cache flushes when using a compute shader. Otherwise r-b On Tue, Oct 24, 2017 at 2:02 PM, Samuel Pitoiset wrote: > Serious Sam Fusion 2017 uses a huge number of occlusion queries, > and the allocated query pool buffer is greater than 4096 bytes

[Mesa-dev] [PATCH 3/3] radv: Compute ac keys from pipeline key.

The beginning of the end for the shader keys. Not entirely sure what I'm going to replace them with for the compiler though, so this is the first step. --- src/amd/vulkan/radv_pipeline.c | 113 +++-- 1 file changed, 41 insertions(+), 72 deletions(-) diff --git

[Mesa-dev] [PATCH 1/3] Don't compute as_ls/as_es before hashing.

--- src/amd/vulkan/radv_pipeline.c | 26 -- 1 file changed, 12 insertions(+), 14 deletions(-) diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index 669d9a4858e..1d7ebfb85e8 100644 --- a/src/amd/vulkan/radv_pipeline.c +++ b/src/amd/vulkan/radv_p

[Mesa-dev] [PATCH 2/3] radv: Add single pipeline cache key.

To decouple the key used for info gathering and the cache from whatever we pass to the compiler. --- src/amd/vulkan/radv_pipeline.c | 44 +--- src/amd/vulkan/radv_pipeline_cache.c | 6 ++--- src/amd/vulkan/radv_private.h| 13 +-- 3 files chang

Re: [Mesa-dev] [PATCH] radv: use a define for the transition point between cp and compute shader

r-b On Wed, Oct 25, 2017 at 12:06 AM, Dave Airlie wrote: > From: Dave Airlie > > For certain buffer meta ops we can use the CP or a compute shader, > we should use a define to rather than hardcoding 4096, allows > for easier testing and more consistency. > > Signed-off-by: Dave Airlie > --- >

Re: [Mesa-dev] [PATCH V2 4/7] ac: add support for explicit component packing

= component; i < value_count + component; i++) { > + LLVMValueRef value = values[i]; > + > + if (!i) > + vec = LLVMGetUndef( LLVMVectorType(LLVMTypeOf(value), > value_count)); > + LLVMValueRef index = LLVMConstInt(ctx->i32

Re: [Mesa-dev] [PATCH 5/7] radv: enable lower to scalar nir pass

unsigned first = MESA_SHADER_STAGES; > + unsigned last = 0; > + for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) { > + if (!pStages[i]) > + continue; > + if (first == MESA_SHADER_STAGES) > + first = i;

Re: [Mesa-dev] [PATCH] radv: use device name in cache creation like radeonsi.

Reviewed-by: Bas Nieuwenhuizen On Wed, Oct 25, 2017 at 3:24 AM, Dave Airlie wrote: > From: Dave Airlie > > Not sure how useful this is, but it makes it more consistent. > > Signed-off-by: Dave Airlie > --- > src/amd/vulkan/radv_device.c | 5 +++-- > 1 file cha

[Mesa-dev] [PATCH] radv: Fix truncation issue hexifying the cache uuid for the disk cache.

Going from binary to hex has a 2x blowup. Fixes: 14216252923 'radv: create on-disk shader cache' --- src/amd/vulkan/radv_device.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c index c4e25222eaf..6cc793654c7 1006

Re: [Mesa-dev] [PATCH V2] ac/nir: generate correct instruction for atomic min/max on unsigned images

Thanks, pushed. On Wed, Oct 25, 2017 at 3:20 PM, Matthew Nicholls wrote: > v2: fix silly typo > > Cc: "17.2 17.3" > --- > src/amd/common/ac_nir_to_llvm.c | 6 -- > 1 file changed, 4 insertions(+), 2 deletions(-) > > diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llv

Re: [Mesa-dev] [PATCH 2/2] radv: Implement VK_AMD_shader_info

On Wed, Oct 25, 2017 at 4:03 PM, Samuel Pitoiset wrote: > > > On 10/25/2017 02:20 PM, Alex Smith wrote: >> >> On 25 October 2017 at 12:46, Samuel Pitoiset > > wrote: >> >> I have something similar on my local tree (started on monday). >> >> Though, I don't

Re: [Mesa-dev] [PATCH] radv: add cache items to in memory cache when reading from disk

Reviewed-by: Bas Nieuwenhuizen On Thu, Oct 26, 2017 at 4:41 AM, Timothy Arceri wrote: > Otherwise we will leak them, load duplicates from disk rather > than memory and never write items loaded from disk to the apps > pipeline cache. > > Fixes: fd24be134ffd 'radv: make

Re: [Mesa-dev] [PATCH] spirv: Claim support for the simple memory model

I couldn't find in the SPIR-V spec what the actual difference is supposed by the two? Seems like in both cases the compiler can assume no aliasing. Reviewed-by: Bas Nieuwenhuizen On Thu, Oct 26, 2017 at 7:11 PM, Jason Ekstrand wrote: > It's rather surprising that we've never

Re: [Mesa-dev] [PATCH 1/2] radv: make radv_fill_buffer() return the needed flush bits

Reviewed-by: Bas Nieuwenhuizen for the series. On Thu, Oct 26, 2017 at 6:03 PM, Samuel Pitoiset wrote: > Only needed when the CS path is used. > > Signed-off-by: Samuel Pitoiset > --- > src/amd/vulkan/radv_cmd_buffer.c | 46 +-- &g

Re: [Mesa-dev] [PATCH 2/2] radv: Disallow indirect outputs for GS on GFX9 as well.

copy indirect lowering > settings from radeonsi Yes, that would be reasonable. Timothy's patch is an optimization though, so I'd be happy to send a backport that only generates the variable needed for the other two if you'd prefer that. > > Let me know what you think. > >

Re: [Mesa-dev] [PATCH 2/7] nir: add varying component packing helpers

+ unsigned slots = glsl_count_attribute_slots(type, false); > + for (unsigned i = 0; i < slots; i++) { > + interp_type[location + i] = > + get_interp_type(var, default_to_smooth_interp); > + > +if (dual_slot) { > +

Re: [Mesa-dev] [PATCH 7/7] radv: enable nir component packing

Reviewed-by: Bas Nieuwenhuizen On Mon, Oct 23, 2017 at 2:10 AM, Timothy Arceri wrote: > SaschaWillems Vulkan demo tessellation: > > ~4300fps -> ~4800fps > --- > src/amd/vulkan/radv_pipeline.c | 13 + > 1 file changed, 13 insertions(+) > > diff --git a/src

Re: [Mesa-dev] [PATCH v3] radv: Implement VK_AMD_shader_info

I fixed the LDS reporting (lds_size is what is in the reg, we need a multiplier), and pushed this. Thanks. On Fri, Oct 27, 2017 at 3:25 PM, Alex Smith wrote: > This allows an app to query shader statistics and get a disassembly of > a shader. RenderDoc git has support for it, so this allows you t

Re: [Mesa-dev] [PATCH 20/21] nir/lower_indirect: Bail early if modes == 0

Doesn't the old behavior also lower compact arrays even with modes = 0? On Sat, Oct 28, 2017 at 8:36 PM, Jason Ekstrand wrote: > There's no point in walking the program if 100% if we're never going to > actually lower anything. > --- > src/compiler/nir/nir_lower_indirect_derefs.c | 3 +++ > 1

Re: [Mesa-dev] [PATCH] radv: Fix -Wformat-security issue

Reviewed-by: Bas Nieuwenhuizen Won't be in a position to push till the evening though. On 30 Oct 2017 09:38, "Alex Smith" wrote: Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103513 Fixes: de889794134e ("radv: Implement VK_AMD_shader_info") Signed-off-by:

Re: [Mesa-dev] [PATCH] radv: use correct alloc function when loading from disk

R-b On 31 Oct 2017 01:35, "Timothy Arceri" wrote: > Fixes regression in: > > dEQP-VK.api.object_management.alloc_callback_fail.graphics_pipeline > > Fixes: 1e84e53712ae "radv: add cache items to in memory cache when reading > from disk" > --- > src/amd/vulkan/radv_pipeline_cache.c | 15

Re: [Mesa-dev] [PATCH] radv: bail out when binding the same vertex buffers

Reviewed-by: Bas Nieuwenhuizen On Mon, Oct 30, 2017 at 7:37 PM, Samuel Pitoiset wrote: > Signed-off-by: Samuel Pitoiset > --- > src/amd/vulkan/radv_cmd_buffer.c | 18 -- > 1 file changed, 16 insertions(+), 2 deletions(-) > > diff --git a/src/amd/vulkan/radv

Re: [Mesa-dev] [PATCH] radv: bail out when binding the same index buffer

Reviewed-by: Bas Nieuwenhuizen Since we store buffer and offset, do we want to calculate index_va at emit time, so we don't have to store it? On Mon, Oct 30, 2017 at 5:12 PM, Samuel Pitoiset wrote: > DOW3 appears to hit this path. > > Signed-off-by: Samuel Pitoiset > ---

Re: [Mesa-dev] [PATCH] radv: make radv_bind_descriptor_set() static

Reviewed-by: Bas Nieuwenhuizen On Tue, Oct 31, 2017 at 10:29 AM, Samuel Pitoiset wrote: > Signed-off-by: Samuel Pitoiset > --- > src/amd/vulkan/radv_cmd_buffer.c | 6 +++--- > src/amd/vulkan/radv_private.h| 3 --- > 2 files changed, 3 insertions(+), 6 deletions(-) > >

[Mesa-dev] [PATCH] radv: Don't expose heaps with 0 memory.

It confuses CTS. This pregenerates the heap info into the physical device, so we can use it for translating contiguous indices into our "standard" ones. This also makes the WSI a bit smarter in case the first preferred heap does not exist. CC: --- src/amd/vulkan/radv_device.c | 135 +++

Re: [Mesa-dev] [PATCH] radv: do not advertise D16_UNORM on VI for Talos/Serious Sam Fusion 2017

On Fri, Nov 3, 2017 at 11:39 AM, Samuel Pitoiset wrote: > VK_FORMAT_D16_UNORM is mandatory for 2D images, but Talos and > Serious Sam Fusion 2017 can use VK_FORMAT_D32_SFLOAT instead. > > This implements some sort of drirc for radv (just based on > the application names). > > This improves perform

[Mesa-dev] [PATCH 2/2] radv: Optimize calling radv_save_descriptors.

uint32_t data[MAX_SETS * 2] = {}; was getting executed before the exit and took significant amounts of time. By having the check outside the function, we skip the execution of the clear. --- src/amd/vulkan/radv_cmd_buffer.c | 6 ++ 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/

[Mesa-dev] [PATCH 1/2] radv: Use an array to store descriptor sets.

The vram_list linked list resulted in lots of pointer chasing. Replacing this with an array instead improves descriptor set allocation CPU usage by 3x at least (when also considering the free), because it had to iterate through 300-400 sets on average. Not a huge improvement as the pre-improvement

Re: [Mesa-dev] [PATCH] radv: free attachments on end command buffer.

Reviewed-by: Bas Nieuwenhuizen On Mon, Nov 6, 2017 at 1:37 AM, Dave Airlie wrote: > From: Dave Airlie > > If we allocate attachments in the begin command buffer due to the > render pass continue bit, we were leaking them. > > Since renderpasses inside a cmd buffer malloc/f

Re: [Mesa-dev] [PATCH 3/4] radv: add helper for setting a descriptor.

On Mon, Nov 6, 2017 at 12:44 AM, Dave Airlie wrote: > From: Dave Airlie > > This is just a simple refactor. > > Signed-off-by: Dave Airlie > --- > src/amd/vulkan/radv_cmd_buffer.c | 20 > src/amd/vulkan/radv_meta.c | 3 +-- > src/amd/vulkan/radv_private.h| 4 +++

Re: [Mesa-dev] [PATCH] radv: add initial copy descriptor support. (v2)

Reviewed-by: Bas Nieuwenhuizen On Sat, Nov 4, 2017 at 9:15 PM, Dave Airlie wrote: > From: Dave Airlie > > It appears the latest dota2 vulkan uses this, > and we get a hang in VR mode without it. > > v2: remove finishme I left in after finishing. > > Cc: "17.2

[Mesa-dev] [PATCH 1/3] radv: copy indirect lowering settings from radeonsi

From: Timothy Arceri It looks the original indirect mask was probably copied from ANV. Sascha Willems demo results: tessellation ~4000 -> ~4200 fps V2: continue lowering local indirects due to llvm deficiencies. (backport from 087e010b2b3dd83a539f97203909d6) --- src/amd/vulkan/radv_pipeline.

[Mesa-dev] [PATCH 3/3] radv: Disallow indirect outputs for GS on GFX9 as well.

Since it also uses the output vector before writing to memory. Fixes: e38685cc62e 'Revert "radv: disable support for VEGA for now."' Reviewed-by: Dave Airlie Reviewed-by: Timothy Arceri (cherry-picked from c07d719e8b683e1bf78f187dd17fe4716f4e5e9c) --- src/amd/vulkan/radv_pipeline.c | 6 ++

[Mesa-dev] [PATCH 2/3] radv: Don't use vgpr indexing for outputs on GFX9.

Due to LLVM bugs. Fixes a bunch of dEQP-VK.glsl.indexing.* tests. Fixes: e38685cc62e 'Revert "radv: disable support for VEGA for now."' Reviewed-by: Dave Airlie (cherry-pick of 6ce550453f1) --- src/amd/vulkan/radv_pipeline.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/src/amd/vulk

Re: [Mesa-dev] [Mesa-stable] [PATCH 2/2] radv: Disallow indirect outputs for GS on GFX9 as well.

t latest by > tomorrow. > > Thanks! > > On Mon, 2017-10-30 at 18:55 +0200, Andres Gomez wrote: >> On Fri, 2017-10-27 at 19:50 +0200, Bas Nieuwenhuizen wrote: >> > On Fri, Oct 27, 2017 at 5:03 PM, Andres Gomez wrote: >> >> [...] >> >> > >

Re: [Mesa-dev] [PATCH] radv: Don't expose heaps with 0 memory.

ive change and has several trivial > conflicts. I think it is OK to merge if you really meant it for 17.2 > too, but just double checking. > > Thanks! > > On Wed, 2017-11-01 at 20:58 +0100, Bas Nieuwenhuizen wrote: >> It confuses CTS. This pregenerates the heap info into the &g

Re: [Mesa-dev] [PATCH] ac/nir: add support for all intrinsics.

On Thu, Nov 9, 2017 at 2:04 AM, Dave Airlie wrote: > From: Dave Airlie > > This is derived from tgsi/radeonsi code from the GLSL intrinsics. > > This should pre-fix radv for the upcoming spirv patches. > > Signed-off-by: Dave Airlie > --- > src/amd/common/ac_nir_to_llvm.c | 32 +

Re: [Mesa-dev] [PATCH] ac/nir: add support for all intrinsics. (v2)

Reviewed-by: Bas Nieuwenhuizen On Thu, Nov 9, 2017 at 2:12 AM, Dave Airlie wrote: > From: Dave Airlie > > This is derived from tgsi/radeonsi code from the GLSL intrinsics. > > This should pre-fix radv for the upcoming spirv patches. > > v2: actually use wait_cnt, sleep de

[Mesa-dev] [PATCH 1/3] radv: Add support for VK_KHR_get_memory_requirements2.

Fished the SparseImage call out of the headers as the spec missed the definition. Signed-off-by: Bas Nieuwenhuizen --- src/amd/vulkan/radv_device.c | 31 +++ src/amd/vulkan/radv_entrypoints_gen.py | 1 + 2 files changed, 32 insertions(+) diff --git a/src

[Mesa-dev] [PATCH 2/3] radv: Add support for VK_KHR_dedicated_allocation.

Signed-off-by: Bas Nieuwenhuizen --- src/amd/vulkan/radv_device.c | 36 -- src/amd/vulkan/radv_entrypoints_gen.py | 1 + 2 files changed, 35 insertions(+), 2 deletions(-) diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c index

[Mesa-dev] [PATCH 3/3] radv: Implement VK_KHR_external_memory

From: Jason Ekstrand This effectively reverts commit 43a171878bb4b5aedb36a. Technically, VK_KHR_get_memory_requirements2 and VK_KHR_dedicated_allocation are required for the KHR version but this at least restores the removed functionality. This patch builds but has received zero testing. Cc: D

[Mesa-dev] [PATCH 2/2] radv: Remove NV dedicated alloc extension.

To not confuse apps in thinking it might be faster. Signed-off-by: Bas Nieuwenhuizen --- src/amd/vulkan/radv_device.c | 4 1 file changed, 4 deletions(-) diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c index 630f35ff7a8..2670d47fdb8 100644 --- a/src/amd/vulkan

[Mesa-dev] [PATCH 1/2] radv: Use the KHR dedicated alloc for the WSI.

NV isn't valid for external images anymore. Signed-off-by: Bas Nieuwenhuizen Fixes: 6ddc64b93ea "radv: Add support for VK_KHR_dedicated_allocation." --- src/amd/vulkan/radv_wsi.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/amd/vulkan/radv_wsi.c b

[Mesa-dev] [PATCH 1/2] radv: Add VK_KHR_storage_buffer_storage_class support.

Signed-off-by: Bas Nieuwenhuizen --- src/amd/vulkan/radv_device.c | 4 src/amd/vulkan/radv_entrypoints_gen.py | 1 + 2 files changed, 5 insertions(+) diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c index a91b366721b..e3655dabe3a 100644 --- a/src/amd

[Mesa-dev] [PATCH 2/2] radv: Add support for VK_KHR_variable_pointers.

Just a trivial enable. Signed-off-by: Bas Nieuwenhuizen --- src/amd/vulkan/radv_device.c | 16 src/amd/vulkan/radv_entrypoints_gen.py | 1 + src/amd/vulkan/radv_pipeline.c | 1 + 3 files changed, 18 insertions(+) diff --git a/src/amd/vulkan/radv_device.c b

Re: [Mesa-dev] [PATCH] radv: initial support for shared semaphores (v2)

counts->sem_count++; > + } > + > + if (counts->syncobj_count) { > + counts->syncobj = (uint32_t *)malloc(sizeof(uint32_t) * > counts->syncobj_count); > + if (!counts->syncobj) > + return VK_ERROR_OUT_OF_HOST_ME

[Mesa-dev] [PATCH] radv: Handle VK_ATTACHMENT_UNUSED in color attachments.

This just sets them to INVALID COLOR, instead of shifting the attachments together. This also fixes a number of cases where we use it first and only then check if it is VK_ATTACHMENT_UNUSED. Signed-off-by: Bas Nieuwenhuizen Fixes: f4e499ec791 "radv: add initial non-conformant radv v

[Mesa-dev] [PATCH] radv: Don't segfault when exporting an image which hasn't been bound yet.

dEQP-VK.api.external.memory.opaque_fd.dedicated.image.export_bind_import_bind Signed-off-by: Bas Nieuwenhuizen Fixes: b70829708ac "radv: Implement VK_KHR_external_memory" --- src/amd/vulkan/radv_image.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulk

Re: [Mesa-dev] [PATCH] radv: check enabled device features.

Reviewed-by: Bas Nieuwenhuizen On Mon, Jul 24, 2017 at 8:18 AM, Dave Airlie wrote: > From: Dave Airlie > > The spec says we should return VK_ERROR_FEATURE_NOT_PRESENT. > > Ported from anv. > > Fixes CTS test dEQP-VK.api.device_init.create_device_unsupported_features &g

Re: [Mesa-dev] [PATCH] radv: for external memory imports close the fd on import success

Reviewed-by: Bas Nieuwenhuizen On Mon, Jul 24, 2017 at 4:51 AM, Dave Airlie wrote: > From: Dave Airlie > > If we get an fd, we need to close it before returning. > > Fixes CTS test > dEQP-VK.api.external.memory.opaque_fd.dedicated.device_only.import_multiple_times > >

Re: [Mesa-dev] [PATCH] radv: allow buffers to be shareable as well.

On Mon, Jul 24, 2017 at 5:03 AM, Dave Airlie wrote: > From: Dave Airlie > > Buffers should report dedicated flags as well, so report the > same information for them as for images. > > (alternately we can turn dedicated off for buffers maybe?) > > Fixes CTS dEQP-VK.api.external.memory.opaque_fd.de

Re: [Mesa-dev] [PATCH] radv: allow buffers to be shareable as well.

On Mon, Jul 24, 2017 at 9:13 AM, Dave Airlie wrote: > On 24 July 2017 at 16:49, Bas Nieuwenhuizen wrote: >> On Mon, Jul 24, 2017 at 5:03 AM, Dave Airlie wrote: >>> From: Dave Airlie >>> >>> Buffers should report dedicated flags as well, so report the >>

Re: [Mesa-dev] [PATCH] radv: fix non-0 based layer clears.

Reviewed-by: Bas Nieuwenhuizen On Mon, Jul 24, 2017 at 9:11 AM, Dave Airlie wrote: > From: Dave Airlie > > If the layer base was > 0, it wasn't getting passed as the start > instance or getting added in the shaders. > > Fixes CTS > dEQP-VK.api.image_clearin

Re: [Mesa-dev] [PATCH] radv: don't set dedicated bit for buffer external memory.

Not even sure why that bit still exists, but Reviewed-by: Bas Nieuwenhuizen On Mon, Jul 24, 2017 at 9:16 AM, Dave Airlie wrote: > From: Dave Airlie > > This is an alternate fix for the buffer export dedicated interaction. > > Signed-off-by: Dave Airlie > --- > src/amd/

Re: [Mesa-dev] [PATCH] radv: enable sample shading

Reviewed-by: Bas Nieuwenhuizen On Mon, Jul 24, 2017 at 9:31 AM, Dave Airlie wrote: > From: Dave Airlie > > This calculates ps_iter_samples from the minSampleShading input > > Signed-off-by: Dave Airlie > --- > src/amd/vulkan/radv_device.c | 2 +- > src/amd/vu

Re: [Mesa-dev] [PATCH] radv: fix buffer views on SI/CIK.

@@ -181,6 +181,11 @@ radv_make_buffer_descriptor(struct radv_device *device, > state[0] = va; > state[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | > S_008F04_STRIDE(stride); > + > + if (device->physical_device->rad_info.chip_cla

Re: [Mesa-dev] [PATCH] radv: only report external semaphore info for opaque fd.

Reviewed-by: Bas Nieuwenhuizen On Tue, Jul 25, 2017 at 2:21 AM, Dave Airlie wrote: > From: Dave Airlie > > Until we support sync fd, don't report the info. > > Fixes CTS dEQP-VK.api.external.semaphore.sync_fd.* from crashing. > > Fixes: eaa56eab6 (radv: initial sup

Re: [Mesa-dev] [PATCH] st/mesa: fix the unconditional return in st_framebuffer_iface_remove

Per https://www.mesa3d.org/submittingpatches.html, just a Fixes tag should be enough to get in all the stable branches that still get updated and contain the commit that is referenced. - Bas On Tue, Jul 25, 2017 at 8:55 PM, Marek Olšák wrote: > I've already sent a patch for this bug, but in the

Re: [Mesa-dev] [PATCH] radv/ac: realign SI workaround with radeonsi.

Reviewed-by: Bas Nieuwenhuizen On Wed, Jul 26, 2017 at 3:34 AM, Dave Airlie wrote: > From: Dave Airlie > > This ports: da7453666ae > radeonsi: don't apply the Z export bug workaround to Hainan > to radv. > > Just noticed in passing. > > Fixes: f4e499ec7 (radv:

Re: [Mesa-dev] [PATCH] radv/ac: port SI TC L1 write corruption fix.

ntext *ctx, > bool is_da = glsl_sampler_type_is_array(type) || > glsl_get_sampler_dim(type) == > GLSL_SAMPLER_DIM_CUBE; > LLVMValueRef da = is_da ? ctx->i1true : ctx->i1false; > - LLVMValueRef glc = ctx

Re: [Mesa-dev] [PATCH] radv/winsys: fix padding command stream for SI

On Wed, Jul 26, 2017 at 4:29 AM, Dave Airlie wrote: > From: Dave Airlie > > We were adding pad to size after creating the object, so we could > submit a CS bigger than the bo created for it. So while this is indeed pedantically more correct, I wonder what would trigger it, since bo size is alway

Re: [Mesa-dev] [PATCH] radv: implement SI/CIK compute shader regalloc hang workaround.

Per the comment, the correct fix for radv should be to limit workgroup size to 256 for SI/BONAIRE/KABINI? On Wed, Jul 26, 2017 at 4:56 AM, Dave Airlie wrote: > From: Dave Airlie > > This ports the regalloc hang workaround from radeonsi, not 100% > sure if this is only needed on the GFX queue as

Re: [Mesa-dev] [PATCH] radv/winsys: fix padding command stream for SI

Fair enough. Reviewed-by: Bas Nieuwenhuizen On Wed, Jul 26, 2017 at 9:43 AM, Dave Airlie wrote: > > > On 26 Jul. 2017 17:25, "Bas Nieuwenhuizen" wrote: > > On Wed, Jul 26, 2017 at 4:29 AM, Dave Airlie wrote: >> From: Dave Airlie >> >> We were addin

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