Re: [Mesa-dev] [PATCH] docs: add GL_ARB_gpu_shader_fp64 and OpenGL 4.0 support for Intel Haswell.

On 05/01/17 09:56, Iago Toral Quiroga wrote: --- docs/relnotes/13.1.0.html | 2 ++ 1 file changed, 2 insertions(+) diff --git a/docs/relnotes/13.1.0.html b/docs/relnotes/13.1.0.html index 4dce843..124da93 100644 --- a/docs/relnotes/13.1.0.html +++ b/docs/relnotes/13.1.0.html @@ -47,6 +47,8 @@

Re: [Mesa-dev] [PATCH] docs: add GL_ARB_gpu_shader_fp64 and OpenGL 4.0 support for Intel Haswell.

Reviewed-by: Tapani Pälli On 01/05/2017 09:56 AM, Iago Toral Quiroga wrote: --- docs/relnotes/13.1.0.html | 2 ++ 1 file changed, 2 insertions(+) diff --git a/docs/relnotes/13.1.0.html b/docs/relnotes/13.1.0.html index 4dce843..124da93 100644 --- a/docs/relnotes/13.1.0.html +++ b/docs/relnote

Re: [Mesa-dev] [PATCH] docs: add GL_ARB_gpu_shader_fp64 and OpenGL 4.0 support for Intel Haswell.

On Thu, 2017-01-05 at 09:59 +0200, Martin Peres wrote: > On 05/01/17 09:56, Iago Toral Quiroga wrote: > > > > --- > >   docs/relnotes/13.1.0.html | 2 ++ > >   1 file changed, 2 insertions(+) > > > > diff --git a/docs/relnotes/13.1.0.html b/docs/relnotes/13.1.0.html > > index 4dce843..124da93 1006

[Mesa-dev] [PATCH] docs: Mark GL_ARB_gpu_shader_fp64 and OpenGL 4.0 as done for i965/hsw+

--- docs/features.txt | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/docs/features.txt b/docs/features.txt index 63b45af..f4a67df 100644 --- a/docs/features.txt +++ b/docs/features.txt @@ -107,7 +107,7 @@ GL 3.3, GLSL 3.30 --- all DONE: i965, nv50, nvc0, r600, radeonsi, l

Re: [Mesa-dev] [PATCH] docs: Mark GL_ARB_gpu_shader_fp64 and OpenGL 4.0 as done for i965/hsw+

On Thursday, January 5, 2017 9:28:56 AM PST Iago Toral Quiroga wrote: > --- > docs/features.txt | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/docs/features.txt b/docs/features.txt > index 63b45af..f4a67df 100644 > --- a/docs/features.txt > +++ b/docs/features.txt >

Re: [Mesa-dev] [PATCH 0/3] RadeonSI L2 prefetch for shader binaries

This series is, Reviewed-by: Edward O'Callaghan On 01/03/2017 07:18 AM, Marek Olšák wrote: > Please review. > > Marek > ___ > mesa-dev mailing list > mesa-dev@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/mesa-dev > signatu

Re: [Mesa-dev] [PATCH] winsys/amdgpu: fix a race condition between fence updates and IB submissions

Acked-by: Edward O'Callaghan On 01/03/2017 07:20 AM, Marek Olšák wrote: > From: Marek Olšák > > The CS thread is needed to ensure proper ordering of operations and can't > be disabled (without complicating the code). > > Discovered by Nine CSMT, which ended up in a deadlock. > --- > src/galli

Re: [Mesa-dev] [PATCH 46/70] st/mesa: get Version from gl_program rather than gl_shader_program

On Thu, 2017-01-05 at 15:30 +0900, Michel Dänzer wrote: > On 20/12/16 07:37 PM, Timothy Arceri wrote: > > Reviewed-by: Nicolai Hähnle > > --- > >  src/mesa/state_tracker/st_atom_texture.c | 5 + > >  1 file changed, 1 insertion(+), 4 deletions(-) > > > > diff --git a/src/mesa/state_tracker/st_

Re: [Mesa-dev] [PATCH] i965: Print VS output VUE map in Vulkan too.

I really need to land my patches. Reviewed-by: Timothy Arceri On Wed, 2017-01-04 at 17:52 -0800, Kenneth Graunke wrote: > We need to move this to the shared layer. > > Signed-off-by: Kenneth Graunke > --- >  src/mesa/drivers/dri/i965/brw_vec4.cpp | 5 + >  src/mesa/drivers/dri/i965/brw_vs.c

Re: [Mesa-dev] [PATCH v2 22/25] nir/i965: use two slots from inputs_read for dvec3/dvec4 vertex input attributes

On Wed, 2017-01-04 at 07:06 -0800, Jason Ekstrand wrote: > On Jan 4, 2017 5:46 AM, "Juan A. Suarez Romero" > wrote: > On Tue, 2017-01-03 at 14:41 -0800, Jason Ekstrand wrote: > > I made a few pretty trivial comments.  With those addressed, > > > > Reviewed-by: Jason Ekstrand > > > > On Dec 16,

Re: [Mesa-dev] [PATCH] i965: Fix last slot calculations

On Wed, 2017-01-04 at 21:33 -0800, Kenneth Graunke wrote: > If the VUE map has slots at the end which the shader does not write, > then we'd "flush" (constructing an URB write) on the last output it > actually wrote.  Then, we'd construct another SEND with EOT, but with > no actual payload data.  T

[Mesa-dev] [PATCH v3 03/22] spirv: add support for loading DF constants

v2 (Jason): - Add assert. Signed-off-by: Samuel Iglesias Gonsálvez Reviewed-by: Jason Ekstrand --- src/compiler/spirv/spirv_to_nir.c | 12 ++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/src/compiler/spirv/spirv_to_nir.c b/src/compiler/spirv/spirv_to_nir.c index 46e

[Mesa-dev] [PATCH v3 08/22] spirv: add double support to _vtn_variable_load_store

Signed-off-by: Samuel Iglesias Gonsálvez Reviewed-by: Jason Ekstrand --- src/compiler/spirv/vtn_variables.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/compiler/spirv/vtn_variables.c b/src/compiler/spirv/vtn_variables.c index e3845365bdd..3a5c23eff93 100644 --- a/src/compiler/spirv/

[Mesa-dev] [PATCH v3 05/22] spirv: add DF support to SpvOp*ConstantComposite

v2 (Jason): - Add assert. Signed-off-by: Samuel Iglesias Gonsálvez Reviewed-by: Jason Ekstrand --- src/compiler/spirv/spirv_to_nir.c | 14 +++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --git a/src/compiler/spirv/spirv_to_nir.c b/src/compiler/spirv/spirv_to_nir.c index 5

[Mesa-dev] [PATCH v3 02/22] spirv: add definition of double based data types

Signed-off-by: Samuel Iglesias Gonsálvez Reviewed-by: Jason Ekstrand --- src/compiler/spirv/spirv_to_nir.c | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/src/compiler/spirv/spirv_to_nir.c b/src/compiler/spirv/spirv_to_nir.c index 9dc93e20202..46e0c386eed 100644 --- a/

[Mesa-dev] [PATCH v3 00/22] Enable Float64 capability support for Intel's Vulkan driver

Hello, This patch series is the third iteration of previous one: https://lists.freedesktop.org/archives/mesa-dev/2016-December/138403.html Main changes are the ones suggested by Jason. There are still 7 patches unreviewed: 6, 12, 16, 18, 20, 21, 22. Our plan is to land this patch series in mast

[Mesa-dev] [PATCH v3 15/22] spirv/nir: add (un)packDouble2x32() translation

Signed-off-by: Samuel Iglesias Gonsálvez Reviewed-by: Jason Ekstrand --- src/compiler/spirv/vtn_glsl450.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/compiler/spirv/vtn_glsl450.c b/src/compiler/spirv/vtn_glsl450.c index a19676fcc2c..0d32fddbef4 100644 --- a/src/compiler/spirv/vtn_g

[Mesa-dev] [PATCH v3 09/22] spirv: add double support to _vtn_block_load_store()

Signed-off-by: Samuel Iglesias Gonsálvez Reviewed-by: Jason Ekstrand --- src/compiler/spirv/vtn_variables.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/compiler/spirv/vtn_variables.c b/src/compiler/spirv/vtn_variables.c index 3a5c23eff93..3fd29ff88da 100644 --- a/src/compiler/spirv/

[Mesa-dev] [PATCH v3 06/22] spirv: fix SpvOpSpecConstantOp with SpvOpVectorShuffle working with double-based vecs

We need to pick two 32-bit values per component to perform the right shuffle operation. v2 (Jason): - Add assert to check matching bit sizes (Jason) - Simplify the code to pick components (Jason) Signed-off-by: Samuel Iglesias Gonsálvez --- src/compiler/spirv/spirv_to_nir.c | 40 ++

[Mesa-dev] [PATCH v3 04/22] spirv: add DF support to vtn_const_ssa_value()

Signed-off-by: Samuel Iglesias Gonsálvez Reviewed-by: Jason Ekstrand --- src/compiler/spirv/spirv_to_nir.c | 8 +--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/src/compiler/spirv/spirv_to_nir.c b/src/compiler/spirv/spirv_to_nir.c index 27995ba0d26..594569d8fa7 100644 ---

[Mesa-dev] [PATCH v3 01/22] spirv: fix typo in spec_constant_decoration_cb()

Signed-off-by: Samuel Iglesias Gonsálvez Reviewed-by: Jason Ekstrand --- src/compiler/spirv/spirv_to_nir.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/compiler/spirv/spirv_to_nir.c b/src/compiler/spirv/spirv_to_nir.c index 41da0e85c9d..9dc93e20202 100644 --- a/sr

[Mesa-dev] [PATCH v3 16/22] spirv: add support for doubles to OpSpecConstant

v2 (Jason): - Fix indent in radv change - Add vtn_u64_literal() helper to take 64 bits (Jason) Signed-off-by: Samuel Iglesias Gonsálvez --- src/amd/vulkan/radv_pipeline.c| 5 - src/compiler/spirv/nir_spirv.h| 5 - src/compiler/spirv/spirv_to_nir.c | 42 +

[Mesa-dev] [PATCH v3 12/22] nir: add nir_get_nir_type_for_glsl_type()

v2 (Jason): - Refactor nir_get_nir_type_for_glsl_type() to avoid using unneeded helpers (Jason) Signed-off-by: Samuel Iglesias Gonsálvez --- src/compiler/nir/nir.h | 27 +++ 1 file changed, 27 insertions(+) diff --git a/src/compiler/nir/nir.h b/src/compiler/nir/nir.h in

[Mesa-dev] [PATCH v3 10/22] spirv: Enable double floating points when copying variables in _vtn_variable_copy()

Signed-off-by: Samuel Iglesias Gonsálvez Reviewed-by: Jason Ekstrand --- src/compiler/spirv/vtn_variables.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/compiler/spirv/vtn_variables.c b/src/compiler/spirv/vtn_variables.c index 3fd29ff88da..9b84c970af7 100644 --- a/src/compiler/spirv/

[Mesa-dev] [PATCH v3 19/22] nir/i965: use two slots from inputs_read for dvec3/dvec4 vertex input attributes

From: "Juan A. Suarez Romero" So far, input_reads was a bitmap tracking which vertex input locations were being used. In OpenGL, an attribute bigger than a vec4 (like a dvec3 or dvec4) consumes just one location, any other small attribute. So we mark the proper bit in inputs_read, and also the s

[Mesa-dev] [PATCH v3 21/22] anv: enable float64 feature on supported platforms

Signed-off-by: Samuel Iglesias Gonsálvez --- src/intel/vulkan/anv_pipeline.c | 7 ++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/src/intel/vulkan/anv_pipeline.c b/src/intel/vulkan/anv_pipeline.c index 361fd256cf7..e25465fc1d9 100644 --- a/src/intel/vulkan/anv_pipeline.c +++

[Mesa-dev] [PATCH v3 17/22] anv/pipeline: get map for double input attributes

From: "Juan A. Suarez Romero" Reviewed-by: Jason Ekstrand --- src/intel/vulkan/anv_pipeline.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/intel/vulkan/anv_pipeline.c b/src/intel/vulkan/anv_pipeline.c index 21a5a446efc..361fd256cf7 100644 --- a/src/intel/vulkan/anv_pipeline.c +++ b/s

[Mesa-dev] [PATCH v3 11/22] spirv: add support for doubles on OpComposite{Insert, Extract}

Signed-off-by: Samuel Iglesias Gonsálvez Reviewed-by: Jason Ekstrand --- src/compiler/spirv/spirv_to_nir.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/compiler/spirv/spirv_to_nir.c b/src/compiler/spirv/spirv_to_nir.c index b428ed33619..6910ca04ef5 100644 --- a/src/compiler/spirv/spi

[Mesa-dev] [PATCH v3 13/22] nir: add nir_type_conversion_op()

This function returns the nir_op corresponding to the conversion between the given nir_alu_type arguments. This function lacks support for integer-based types with bit_size != 32 and for float16 conversion ops. v2: - Improve readiness of the code and delete cases that don't happen now (Jason) Si

[Mesa-dev] [PATCH v3 22/22] anv: enable shaderFloat64 feature

Signed-off-by: Samuel Iglesias Gonsálvez --- src/intel/vulkan/anv_device.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c index 062fab6fabe..219c6114083 100644 --- a/src/intel/vulkan/anv_device.c +++ b/src/intel/vu

[Mesa-dev] [PATCH v3 18/22] isl: fix VA64 support for double and dvecN vertex attributes

We use *64*_PASSTHRU formats to upload vertex attributes of 64 bits to avoid conversions. From the BDW PRM, Volume 2d, page 586 (VERTEX_ELEMENT_STATE): "When SourceElementFormat is set to one of the *64*_PASSTHRU formats, 64-bit components are stored in the URB without any conversio

[Mesa-dev] [PATCH v3 20/22] spirv: enable SpvCapabilityFloat64 only to supported platforms

v2 (Jason): - Use nir_spirv_supported_extensions to check if the feature is enabled. Signed-off-by: Samuel Iglesias Gonsálvez --- src/compiler/spirv/nir_spirv.h| 1 + src/compiler/spirv/spirv_to_nir.c | 5 - 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/src/compiler/spirv

[Mesa-dev] [PATCH v3 14/22] spirv/nir: implement DF conversions

SPIR-V does not have special opcodes for DF conversions. We need to identify them by checking the bit size of the operand and the result. Signed-off-by: Samuel Iglesias Gonsálvez Reviewed-by: Jason Ekstrand --- src/compiler/spirv/spirv_to_nir.c | 4 +++- src/compiler/spirv/vtn_alu.c | 29

[Mesa-dev] [PATCH v3 07/22] spirv: add double support to SpvOpCompositeExtract

v2 (Jason): - Add asserts. Signed-off-by: Samuel Iglesias Gonsálvez Reviewed-by: Jason Ekstrand --- src/compiler/spirv/spirv_to_nir.c | 16 ++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/src/compiler/spirv/spirv_to_nir.c b/src/compiler/spirv/spirv_to_nir.c inde

Re: [Mesa-dev] [PATCH 1/3] vl/dri3: use external texture as back buffers(v4)

Am 04.01.2017 um 18:13 schrieb Nayan Deshmukh: dri3 allows us to send handle of a texture directly to X so this patch allows a state tracker to directly send its texture to X to be used as back buffer and avoids extra copying v2: use clip width/height to display a portion of the surface v3: remo

[Mesa-dev] [PATCH] i965: Fix textureGather with RG32I/UI on Gen7.

According to the "Gather4 R32G32_FLOAT Bug" internal documentation page, the R32G32_UINT and R32G32_SINT formats are affected by the same bug as R32G32_FLOAT. Applying the same workarounds should be viable - apparently the R32G32_FLOAT_LD format shouldn't corrupt integer data which is NaN or other

[Mesa-dev] [Bug 99179] Mesa freezez the pc when running nativ games for linux

https://bugs.freedesktop.org/show_bug.cgi?id=99179 --- Comment #8 from Vedran Miletić --- > if i install the games and then upgrade de mesa version to 13.0 it's running fine Sounds like an installation issue to me. -- You are receiving this mail because: You are the QA Contact for the bug. You

[Mesa-dev] [Bug 98783] Talos Principle rendering garbage in main menu animation when using Vulkan

https://bugs.freedesktop.org/show_bug.cgi?id=98783 Vedran Miletić changed: What|Removed |Added Resolution|--- |FIXED Status|NEW

[Mesa-dev] [PATCH] i965: call intel_prepare_render always when reading pixels

Currently we do this only in the fallback code (when tiled memcpy version failed) but it needs to be done always so that we have correct read and write buffer in place. No regressions seen in CI. Fixes: dEQP-EGL.functional.buffer_age.* Signed-off-by: Tapani Pälli Bugzilla: https://bugs.f

[Mesa-dev] [PATCH] st/mesa: fix a segfault when prog->sh.data is NULL

From: Marek Olšák Broken by: st/mesa: get Version from gl_program rather than gl_shader_program --- src/mesa/state_tracker/st_atom_texture.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/mesa/state_tracker/st_atom_texture.c b/src/mesa/state_tracker/st_atom_textur

Re: [Mesa-dev] [PATCH 46/70] st/mesa: get Version from gl_program rather than gl_shader_program

I've just sent a fix for this. Marek On Thu, Jan 5, 2017 at 9:58 AM, Timothy Arceri wrote: > On Thu, 2017-01-05 at 15:30 +0900, Michel Dänzer wrote: >> On 20/12/16 07:37 PM, Timothy Arceri wrote: >> > Reviewed-by: Nicolai Hähnle >> > --- >> > src/mesa/state_tracker/st_atom_texture.c | 5 +

Re: [Mesa-dev] [PATCH 3/3] radeonsi: add a workaround for the Witcher 2 black transitions

I'm gonna send a v2 of this patch with a different commit message. Marek On Wed, Jan 4, 2017 at 1:45 PM, Marek Olšák wrote: > Here's my theory about the Witcher 2 issue: > > The problematic shader contains KILL. Reloading inputs after KILL is > unsafe, because KILL breaks the WQM mode, thus the

[Mesa-dev] [PATCH] radeonsi: fix the Witcher 2 black transitions

From: Marek Olšák v2: do it properly --- src/gallium/drivers/radeonsi/si_shader_tgsi_setup.c | 15 +-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/src/gallium/drivers/radeonsi/si_shader_tgsi_setup.c b/src/gallium/drivers/radeonsi/si_shader_tgsi_setup.c index 996a4

[Mesa-dev] [PATCH 01/22] i965/disasm: also print nibctrl in IVB for execsize=8

From: Iago Toral Quiroga 4-wide DF operations where NibCtrl applies require and execsize of 8 in IvyBridge/Valleyview. --- src/mesa/drivers/dri/i965/brw_disasm.c | 7 +++ 1 file changed, 7 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_disasm.c b/src/mesa/drivers/dri/i965/brw_dis

[Mesa-dev] [PATCH 05/22] i965/fs: consider execsize can be duplicated in lower_simd_with

From: "Juan A. Suarez Romero" In IVB/VLV, for instructions dealing with DF, execsize will be duplicated in the final code. So take this in account when checking if instructions should be split. --- src/mesa/drivers/dri/i965/brw_fs.cpp | 13 - 1 file changed, 12 insertions(+), 1 dele

[Mesa-dev] [PATCH 04/22] i965/fs: add lowering step to duplicate sources with stride 0.

From: "Juan A. Suarez Romero" When dealing with DF uniforms with just 1 component, we set stride 0 to use the value along the operation. However, when duplicating the regioning parameters in IVB/VLV, we are violating the regioning restrictions. So instead of using the value with stride 0, we jus

[Mesa-dev] [PATCH 10/22] i965/fs: indirect addressing with doubles is not supported in IVB/VLV

It is tested empirically that IVB/VLV don't support indirect addressing with doubles but it is not documented in the PRM. This patch applies the same solution than for Cherryview/Broxton and takes into account that we cannot duplicate the stride, since the hardware will do it internally. Signed-o

[Mesa-dev] [PATCH 06/22] i965/fs: double-precision execution does not use 2 channels per DF in IVB/VLV

From: Iago Toral Quiroga It seems to use 1 channel por DF, just like later hardware. The docs say things like: "Each DF operand uses a pair of channels and all masking and swizzling should be adjusted appropriately." "In Align16, all regioning parameters must use the syntax of a pair of packe

[Mesa-dev] [PATCH 02/22] i965/fs: add helper to retrieve instruction data size

From: "Juan A. Suarez Romero" The execution data size is the biggest type size of any instruction operand. We will use it to know if the instruction deals with DF, because in Ivy we need to duplicate the execution size and regioning parameters. --- src/mesa/drivers/dri/i965/brw_fs.cpp | 19 +++

[Mesa-dev] [PATCH 00/22] i965 Ivybridge ARB_gpu_shader_fp64 / OpenGL 4.0

Hi, This series implements initial support for Ivybridge FP64 for both align16 and align1 backends, and with that we can enable FP64 and OpenGL 4.0 in Ivybridge. These patches are available in our repository for testing. You can clone it using the following command: $ git clone -b i965-fp64-gen

[Mesa-dev] [PATCH 03/22] i965/fs: duplicate regioning parameters and execsize for DF in IVB/VLV

From: "Juan A. Suarez Romero" In IVB and VLV, both regioning parameters and execution sizes are measured as floats. So when we have something like: mov(8) g2<1>DF g3<4,4,1>DF We are not actually moving 8 doubles (our intention), but 4 doubles. We need to duplicate the parameters to cope with

[Mesa-dev] [PATCH 08/22] i965/fs: fix lower SIMD width for IVB/VLV's MOVE_INDIRECT

From: "Juan A. Suarez Romero" Previous to Broadwell, we have 8 registers for MOV_INDIRECT. But if IVB/VLV deal with DFs, we will duplicate the exec_size from 8 to 16. This patch limits the SIMD width to 4 in this case. --- src/mesa/drivers/dri/i965/brw_fs.cpp | 9 +++-- 1 file changed, 7 in

[Mesa-dev] [PATCH 09/22] i965/fs: add lowering x2d step for IVB/VLV

From: "Juan A. Suarez Romero" On Ivybridge/Valleyview, when converting a float (F) to a double precision float (DF), the hardware automatically duplicates the source horizontal stride, hence converting only the values in odd positions. This commit adds a new lowering step, exclusively for IVB/VL

[Mesa-dev] [PATCH 12/22] i965/vec4: split DF instructions and later duplicate its execsize in IVB/VLV

We need to split DF instructions in two on IVB/VLV as it needs an execsize 8 to process 4 DF values (one GRF in total). Signed-off-by: Samuel Iglesias Gonsálvez --- src/mesa/drivers/dri/i965/brw_ir_vec4.h | 1 + src/mesa/drivers/dri/i965/brw_vec4.cpp | 20 +++-

[Mesa-dev] [PATCH 11/22] i965/fs: lower all non-force_writemask_all DF instructions to SIMD4 on IVB/VLV

The hardware applies the same channel enable signals to both halves of the compressed instruction which will be just wrong under non-uniform control flow. Fix this by splitting those instructions to SIMD4. Signed-off-by: Samuel Iglesias Gonsálvez --- src/mesa/drivers/dri/i965/brw_fs.cpp | 9

[Mesa-dev] [PATCH 07/22] i965/fs: fix dst stride in IVB/VLV type conversions

From: "Juan A. Suarez Romero" When converting a DF to F, we set dst stride to 2, to fulfil alignment restrictions. But in IVB/VLV, this is not necessary, as each DF conversion already writes 2 F, the first one the real value, and the second one a 0. That is, IVB/VLV already set stride = 2 implic

[Mesa-dev] [PATCH 13/22] i965/vec4: keep original type when dealing with null registers

From: "Juan A. Suarez Romero" Keep the original type when dealing with null registers. Specially because we do no want to introduce an implicit conversion between types that could affect the conditional flags. This affects specially when the original type is DF, and we are working on Ivybridge/V

[Mesa-dev] [PATCH 15/22] i965/vec4: fix SIMD-width lowering for double_to_single operation in IVB/VLV

From: "Juan A. Suarez Romero" When spliting double_to_single() in Ivybridge/Valleyview, the second part should use a temporal register, and then move the values to the second half of the original destiny, so we get all the results in the same register. --- src/mesa/drivers/dri/i965/brw_vec4.cpp

[Mesa-dev] [PATCH 16/22] i965/vec4: consider subregister offset in live variables

From: "Juan A. Suarez Romero" Take in account the offset value when getting the var from register. This is required when dealing with an operation that writes half of the register (like one d2x in IVB/VLV, which uses exec_size == 4). Note that for live analysis variables we need to stick to per

[Mesa-dev] [PATCH 18/22] i965/vec4: adapt setup_imm_df() to allow inserting instructions before another one

Add a new setup_imm_df() that alows the insertion of the instructions before another one. This will be used in the lowering passes for DF instructions. Signed-off-by: Samuel Iglesias Gonsálvez --- src/mesa/drivers/dri/i965/brw_vec4.h | 2 ++ src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 21

[Mesa-dev] [PATCH 17/22] i965/vec4: fix register_coalesce() for partial writes

From: "Juan A. Suarez Romero" When lowering double_to_single() we added a final mov() that puts 32-bit values from one register in the second half of destination. --- src/mesa/drivers/dri/i965/brw_vec4.cpp | 5 + src/mesa/drivers/dri/i965/brw_vec4_copy_propagation.cpp | 3 ++

[Mesa-dev] [PATCH 19/22] i965/vec4: fix SIMD-with lowering for CMP/MOV instructions with conditional modifiers

From: "Juan A. Suarez Romero" When splitting a CMP/MOV instruction with NULL dest, DF sources, and conditional modifier; we can't use directly the flag registers, as they will have the wrong results in IVB/VLV after the scalarization. Rather, we need to store the result in a temporary register,

[Mesa-dev] [PATCH 14/22] i965/vec4: fix double_to_single() for IVB/VLV

From: "Juan A. Suarez Romero" In the generator we must generate slightly different code for Ivybridge/Valleview, because of the way the stride works in this hardware. --- src/mesa/drivers/dri/i965/brw_vec4_generator.cpp | 26 +--- 1 file changed, 23 insertions(+), 3 deletions

[Mesa-dev] [PATCH 20/22] i965: enable ARB_gpu_shader_fp64 for Ivybridge/Valleyview

Signed-off-by: Samuel Iglesias Gonsálvez --- src/mesa/drivers/dri/i965/intel_extensions.c | 5 + 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/src/mesa/drivers/dri/i965/intel_extensions.c b/src/mesa/drivers/dri/i965/intel_extensions.c index 22651de..f402f7f 100644 --- a/src/me

[Mesa-dev] [PATCH] anv: don't skip the VUE header if we are reading gl_Layer in a fragment shader

This is the same we do in the GL driver: the hardware provides gl_Layer in the VUE header, so when the fragment shader reads it we can't skip it. --- With this patch we now successfully read gl_Layer in fragment shaders. Layered rendering still does not work though, probably because we still need

[Mesa-dev] [PATCH 22/22] docs: mark GL_ARB_gpu_shader_fp64 and OpenGL 4.0 as supported by i965/gen7+

Signed-off-by: Samuel Iglesias Gonsálvez --- docs/features.txt | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/docs/features.txt b/docs/features.txt index f4a67df..18327af 100644 --- a/docs/features.txt +++ b/docs/features.txt @@ -107,7 +107,7 @@ GL 3.3, GLSL 3.30 --- all

[Mesa-dev] [PATCH 21/22] i965: enable OpenGL 4.0 to Ivybridge/Valleyview

Signed-off-by: Samuel Iglesias Gonsálvez --- src/mesa/drivers/dri/i965/intel_extensions.c | 2 +- src/mesa/drivers/dri/i965/intel_screen.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mesa/drivers/dri/i965/intel_extensions.c b/src/mesa/drivers/dri/i965/intel_ext

Re: [Mesa-dev] [PATCH 2/2] va: call texture_get_handle while the mutex is being held

Am 04.01.2017 um 18:57 schrieb Marek Olšák: On Wed, Jan 4, 2017 at 6:40 PM, Alex Deucher wrote: On Wed, Jan 4, 2017 at 5:47 AM, Marek Olšák wrote: From: Marek Olšák The context may be used by texture_get_handle. The the omx state tracker need this as well? The omx state tracker doesn't us

Re: [Mesa-dev] [PATCH] st/mesa: fix a segfault when prog->sh.data is NULL

This fixes a bunch of arb_fragment_program piglit tests. Thanks. Reviewed-by: Samuel Pitoiset On 01/05/2017 01:48 PM, Marek Olšák wrote: From: Marek Olšák Broken by: st/mesa: get Version from gl_program rather than gl_shader_program --- src/mesa/state_tracker/st_atom_texture.c | 4 +++-

[Mesa-dev] [PATCH] st/va: fix incorrect argument in vl_compositor_cleanup

This fixes the mistake introduced in commit b6737a8bcd03ea68952799144c0c6e6e6679bee9 Signed-off-by: Nayan Deshmukh --- src/gallium/state_trackers/va/context.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/gallium/state_trackers/va/context.c b/src/gallium/state_trackers

Re: [Mesa-dev] [PATCH v2 22/25] nir/i965: use two slots from inputs_read for dvec3/dvec4 vertex input attributes

On Jan 5, 2017 3:11 AM, "Juan A. Suarez Romero" wrote: On Wed, 2017-01-04 at 07:06 -0800, Jason Ekstrand wrote: On Jan 4, 2017 5:46 AM, "Juan A. Suarez Romero" wrote: On Tue, 2017-01-03 at 14:41 -0800, Jason Ekstrand wrote: I made a few pretty trivial comments. With those addressed, Reviewe

Re: [Mesa-dev] [PATCH v2 22/25] nir/i965: use two slots from inputs_read for dvec3/dvec4 vertex input attributes

On Thu, 2017-01-05 at 06:41 -0800, Jason Ekstrand wrote: > On Jan 5, 2017 3:11 AM, "Juan A. Suarez Romero" > wrote: > On Wed, 2017-01-04 at 07:06 -0800, Jason Ekstrand wrote: > > On Jan 4, 2017 5:46 AM, "Juan A. Suarez Romero" > m> wrote: > > On Tue, 2017-01-03 at 14:41 -0800, Jason Ekstrand wrot

Re: [Mesa-dev] [PATCH 1/5] gallium/hud: add an option to rename each data source

On 01.01.2017 01:05, Marek Olšák wrote: From: Marek Olšák useful for radeonsi performance counters --- src/gallium/auxiliary/hud/hud_context.c | 40 - 1 file changed, 30 insertions(+), 10 deletions(-) diff --git a/src/gallium/auxiliary/hud/hud_context.c b/src/

Re: [Mesa-dev] [PATCH 1/3] vl/dri3: use external texture as back buffers(v4)

On 01/05/2017 05:21 AM, Christian König wrote: Am 04.01.2017 um 18:13 schrieb Nayan Deshmukh: dri3 allows us to send handle of a texture directly to X so this patch allows a state tracker to directly send its texture to X to be used as back buffer and avoids extra copying v2: use clip width/h

Re: [Mesa-dev] [PATCH 12/12] radeonsi: turn SDMA IBs into de-facto preambles of GFX IBs

That Deus Ex number is impressive. For the series: Reviewed-by: Nicolai Hähnle On 02.01.2017 23:54, Marek Olšák wrote: From: Marek Olšák Draw calls no longer flush SDMA IBs. r600_need_dma_space is responsible for synchronizing execution between both IBs. Initial buffer clears and fast clear

Re: [Mesa-dev] [PATCH] st/va: fix incorrect argument in vl_compositor_cleanup

Am 05.01.2017 um 15:30 schrieb Nayan Deshmukh: This fixes the mistake introduced in commit b6737a8bcd03ea68952799144c0c6e6e6679bee9 Signed-off-by: Nayan Deshmukh Reviewed-by: Christian König . --- src/gallium/state_trackers/va/context.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(

Re: [Mesa-dev] [PATCH 3/7] gallium: add FBFETCH opcode to retrieve the current sample value

On 02.01.2017 21:41, Marek Olšák wrote: On Mon, Jan 2, 2017 at 7:01 AM, Ilia Mirkin wrote: Signed-off-by: Ilia Mirkin --- src/gallium/auxiliary/tgsi/tgsi_info.c | 2 +- src/gallium/docs/source/tgsi.rst | 11 +++ src/gallium/include/pipe/p_shader_tokens.h | 2 +- 3 file

Re: [Mesa-dev] [PATCH 5/7] gallium: add flags parameter to texture barrier

On 02.01.2017 07:01, Ilia Mirkin wrote: This is so that we can differentiate between flushing any framebuffer reading caches from regular sampler caches. Signed-off-by: Ilia Mirkin --- This felt too simple and silly to create an extra callback for, especially since the implementations that rel

Re: [Mesa-dev] [PATCH 6/7] st/mesa: add support for advanced blend when fb can be fetched from

Reviewed-by: Nicolai Hähnle On 02.01.2017 07:01, Ilia Mirkin wrote: This implements support for emitting FBFETCH ops, using the existing lowering pass for advanced blend logic, and disabling hw blend when advanced blending is enabled. Signed-off-by: Ilia Mirkin --- src/mesa/state_tracker/st_

Re: [Mesa-dev] [PATCH 31/32] i965: Remove scanout restriction from lossless compression

On Wed, Jan 04, 2017 at 06:36:05PM -0800, Ben Widawsky wrote: > On 17-01-04 10:41:58, Topi Pohjolainen Topi Pohjolainen wrote: > > On Mon, Jan 02, 2017 at 06:37:22PM -0800, Ben Widawsky wrote: > > > v2: Try to keep the assert as recommended by Topi. This requires > > > modifying the num_samples che

Re: [Mesa-dev] [PATCH 27/32] i965: Change resolve flags to enum

On Wed, Jan 04, 2017 at 05:58:46PM -0800, Ben Widawsky wrote: > On 17-01-04 10:00:59, Topi Pohjolainen Topi Pohjolainen wrote: > > On Mon, Jan 02, 2017 at 06:37:18PM -0800, Ben Widawsky wrote: > > > In the foreseeable future it doesn't seem to make sense to have multiple > > > resolve flags. What d

Re: [Mesa-dev] [PATCH 24/32] i965/miptree: Allocate mt earlier in update winsys

On Wed, Jan 04, 2017 at 06:17:31PM -0800, Ben Widawsky wrote: > On 17-01-04 10:57:40, Topi Pohjolainen Topi Pohjolainen wrote: > > On Wed, Jan 04, 2017 at 10:26:50AM +0200, Pohjolainen, Topi wrote: > > > On Mon, Jan 02, 2017 at 06:37:15PM -0800, Ben Widawsky wrote: > > > > Allows us to continue uti

Re: [Mesa-dev] [PATCH 22/32] i965: Create correctly sized mcs for an image

On Wed, Jan 04, 2017 at 05:36:22PM -0800, Ben Widawsky wrote: > On 17-01-04 09:51:20, Topi Pohjolainen Topi Pohjolainen wrote: > > On Mon, Jan 02, 2017 at 06:37:13PM -0800, Ben Widawsky wrote: > > > v2: Leave "image+mod" (Topi) > > > > > > Signed-off-by: Ben Widawsky > > > Acked-by: Daniel Stone

Re: [Mesa-dev] [PATCH 3/7] gallium: add FBFETCH opcode to retrieve the current sample value

On Thu, Jan 5, 2017 at 10:48 AM, Nicolai Hähnle wrote: > On 02.01.2017 21:41, Marek Olšák wrote: >> >> On Mon, Jan 2, 2017 at 7:01 AM, Ilia Mirkin wrote: >>> >>> Signed-off-by: Ilia Mirkin >>> --- >>> src/gallium/auxiliary/tgsi/tgsi_info.c | 2 +- >>> src/gallium/docs/source/tgsi.rst

Re: [Mesa-dev] [PATCH 5/5] gallium: remove TGSI_OPCODE_SUB

On 01.01.2017 01:04, Marek Olšák wrote: From: Marek Olšák It's redundant with the source modifier. This could have been split up, but oh well. Aside from Ilia's comment, patches 4&5 are Reviewed-by: Nicolai Hähnle --- src/gallium/auxiliary/draw/draw_pipe_aaline.c | 2 +- src/gall

[Mesa-dev] [ANNOUNCE] mesa 13.0.3

Mesa 13.0.3 is now available. This series we have - multiple fixes for i965 and radeonsi. The ANV driver has extra smoke testing fixes and memory leaks have been resolved. Chad Versace (2): i965/mt: Disable aux surfaces after making miptree shareable egl: Fix crashes in eglCreate*Sur

Re: [Mesa-dev] [PATCH 3/7] gallium: add FBFETCH opcode to retrieve the current sample value

On 05.01.2017 17:02, Ilia Mirkin wrote: On Thu, Jan 5, 2017 at 10:48 AM, Nicolai Hähnle wrote: On 02.01.2017 21:41, Marek Olšák wrote: On Mon, Jan 2, 2017 at 7:01 AM, Ilia Mirkin wrote: Signed-off-by: Ilia Mirkin --- src/gallium/auxiliary/tgsi/tgsi_info.c | 2 +- src/gallium/docs/so

Re: [Mesa-dev] [PATCH v3 06/22] spirv: fix SpvOpSpecConstantOp with SpvOpVectorShuffle working with double-based vecs

On Jan 5, 2017 10:20, "Samuel Iglesias Gonsálvez" wrote: We need to pick two 32-bit values per component to perform the right shuffle operation. v2 (Jason): - Add assert to check matching bit sizes (Jason) - Simplify the code to pick components (Jason) Signed-off-by: Samuel Iglesias Gonsálvez

[Mesa-dev] [PATCH] radeonsi: compute the absolute value before RSQ

As explained by Nicolai, it seems like D3D always compute the absolute value while GLSL says that the result of inversesqrt() is undefined if x <= 0. Using the absolute value looks like safer especially when the game has been ported from D3D to GL. This gets rid of the NaN values in the "Spec Ops:

Re: [Mesa-dev] [PATCH 3/7] gallium: add FBFETCH opcode to retrieve the current sample value

On Thu, Jan 5, 2017 at 11:30 AM, Nicolai Hähnle wrote: > On 05.01.2017 17:02, Ilia Mirkin wrote: >> >> On Thu, Jan 5, 2017 at 10:48 AM, Nicolai Hähnle >> wrote: >>> >>> On 02.01.2017 21:41, Marek Olšák wrote: On Mon, Jan 2, 2017 at 7:01 AM, Ilia Mirkin wrote: > >

Re: [Mesa-dev] [PATCH 0/8] i965: gl_TessLevel rescrambling in NIR

Hi, On 05.01.2017 01:55, Kenneth Graunke wrote: On Wednesday, January 4, 2017 3:16:41 PM PST Eero Tamminen wrote: Are there yet other use-cases for Vulkan tessellation besides Sacha Willems' three tests here: https://github.com/SaschaWillems/Vulkan ? Does it matter? It's required for

[Mesa-dev] [PATCH] swr: [rasterizer core/common/jitter] gl_double support

--- .../drivers/swr/rasterizer/common/formats.cpp | 104 ++--- .../drivers/swr/rasterizer/common/formats.h| 4 + .../drivers/swr/rasterizer/core/format_traits.h| 88 + src/gallium/drivers/swr/rasterizer/core/utils.h| 64 + .../dr

Re: [Mesa-dev] [PATCH 7/7] nvc0: enable FBFETCH with a special slot for color buffer 0

Would be nice to test on Maxwell as well. More comments inline. Thanks. On 01/02/2017 07:01 AM, Ilia Mirkin wrote: We don't need to support all the color buffers for advanced blend, just cb0. For Fermi, we use the special binding slots so that we don't overlap with user textures, while Kepler+

Re: [Mesa-dev] [PATCH] radeonsi: compute the absolute value before RSQ

Shouldn't we also use abs for SQRT? For example, this adds abs for both RSQ and SQRT: https://cgit.freedesktop.org/~mareko/mesa/commit/?id=5e0fb661a8e6ac5f7b2245dd31595155128e0664 Marek On Thu, Jan 5, 2017 at 5:47 PM, Samuel Pitoiset wrote: > As explained by Nicolai, it seems like D3D always co

Re: [Mesa-dev] [PATCH 7/7] nvc0: enable FBFETCH with a special slot for color buffer 0

On Thu, Jan 5, 2017 at 12:22 PM, Samuel Pitoiset wrote: > Would be nice to test on Maxwell as well. No ES 3.1 there (yet), so no tests. I probably should have just forced it. Will do. > > More comments inline. > > Thanks. > > > On 01/02/2017 07:01 AM, Ilia Mirkin wrote: >> diff --git a/src/galli

[Mesa-dev] [PATCH 1/2] glsl: Change copy propagation to use variable -> acp_entry mapping

Map from ir_variable to acp_entry instead of from lhs to rhs. Add a field in the acp_entry for the acp_entry of the ir_variable that is meant to be a replacement for this ir_variable. Insert both acp_entries in the table mapped to their own ir_variable. This way we can use only one hash table, and

[Mesa-dev] [PATCH 2/2] glsl: Make copy propagation loop through copy-chains

This should allow us to resolve copy propagation faster, as we don't need multiple runs of the pass when we have situations like: foo = bar; baz = foo; --- src/compiler/glsl/opt_copy_propagation.cpp | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/src/compiler/glsl/opt_co

Re: [Mesa-dev] [PATCH] radeonsi: compute the absolute value before RSQ

Meh, I'm not really a big fan of such hacks. GPUs have support for NaNs since ages, and while glsl is lenient the point stands that returning a NaN is a more correct result, so doing extra work to get a wrong result doesn't look all that great to me. FWIW dx10 requires NaNs as results (for both sqr

Re: [Mesa-dev] [PATCH] swr: [rasterizer core/common/jitter] gl_double support

Reviewed-by: Bruce Cherniak > On Jan 5, 2017, at 11:18 AM, Tim Rowley wrote: > > --- > .../drivers/swr/rasterizer/common/formats.cpp | 104 ++--- > .../drivers/swr/rasterizer/common/formats.h| 4 + > .../drivers/swr/rasterizer/core/format_traits.h| 88 +

Re: [Mesa-dev] [PATCH v3 5/7] i965: Add support for xfb overflow on query buffer objects.

On Tuesday, December 13, 2016 2:50:57 PM PST Rafael Antognolli wrote: > Enable getting the results of a transform feedback overflow query with a > buffer object. > > Signed-off-by: Rafael Antognolli > --- > src/mesa/drivers/dri/i965/hsw_queryobj.c | 108 > +++ > 1 fi

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