From: "Juan A. Suarez Romero" <jasua...@igalia.com>
When converting a DF to F, we set dst stride to 2, to fulfil alignment
restrictions.
But in IVB/VLV, this is not necessary, as each DF conversion already
writes 2 F, the first one the real value, and the second one a 0. That
is, IVB/VLV already set stride = 2 implicitly, so we must set it to 1
explicitly to avoid ending up with stride = 4.
---
src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
index ac2d8ad..6967584 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
@@ -1634,6 +1634,16 @@ fs_generator::generate_code(const cfg_t *cfg, int
dispatch_width)
inst->src[i].type != BRW_REGISTER_TYPE_UD ||
!inst->src[i].negate);
}
+ /* When converting from DF->F, we set destination's stride as 2 as an
+ * aligment requirement. But in IVB/VLV, each DF implicitly writes 2 F,
+ * being the first one the converted value. So we don't need to
+ * explicitly set stride 2, but 1.
+ */
+ if (devinfo->gen == 7 && !devinfo->is_haswell &&
+ type_sz(inst->src[0].type) > type_sz(inst->dst.type)) {
+ assert(inst->dst.stride == 2 || inst->dst.stride == 1);
+ inst->dst.stride = 1;
+ }
dst = brw_reg_from_fs_reg(compiler, inst, &inst->dst, compressed);
brw_set_default_access_mode(p, BRW_ALIGN_1);
--
2.9.3
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