Re: [Mesa-dev] [PATCH 05/12] st/va: add encode entrypoint

Am 19.07.2016 um 00:43 schrieb Boyuan Zhang: VAAPI passes PIPE_VIDEO_ENTRYPOINT_ENCODE as entry point for encoding case. We will save this encode entry point in config. config_id was used as profile previously. Now, config has both profile and entrypoint field, and config_id is used to get the

Re: [Mesa-dev] [PATCH 11/12] st/va: add environmental variable to disable interlace

Am 19.07.2016 um 00:43 schrieb Boyuan Zhang: Add environmental variable to disable interlace mode. At VAAPI decoding stage, driver can not distinguish b/w pure decoding case and transcoding case. And since interlace encoding is not supported, we have to disable interlace for transcoding case.

Re: [Mesa-dev] [PATCH 09/12] st/va: add functions for VAAPI encode

Am 19.07.2016 um 00:43 schrieb Boyuan Zhang: Add necessary functions/changes for VAAPI encoding to buffer and picture. These changes will allow driver to handle all Vaapi encode related operations. This patch doesn't change the Vaapi decode behaviour. Signed-off-by: Boyuan Zhang --- src/gal

Re: [Mesa-dev] [Mesa-stable] [PATCH] mapi: Export all GLES 3.1 functions in libGLESv2.so

Hi, sorry for being late but this patch doesn't mention that all those symbols should be exported in libGL.so too [1]. If you look at the history of static_data.py it was mentioned that this list of functions should never grow [2]. Thanks, Andreas [1] https://anonscm.debian.org/cgit/pkg-xorg/li

[Mesa-dev] [PATCH v2 6/8] nv50/ir: optimize ADD3(d, 0x0, b, c) to ADD(d, b, c)

And ADD3(d, a, 0x0, c) to ADD(d, a, c) as well. v2: - use moveSources() - allow ADD3 -> ADD when srcFlags is set Signed-off-by: Samuel Pitoiset --- src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp | 7 ++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/src/gallium/

[Mesa-dev] [PATCH v2 8/8] nv50/ir: optimize ADD3(d, a, b, c) to ADD(d, a, b + c)

And ADD3(d, a, b, c) to ADD(d, b, a + c) as well. Signed-off-by: Samuel Pitoiset --- .../drivers/nouveau/codegen/nv50_ir_peephole.cpp | 62 ++ 1 file changed, 62 insertions(+) diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp b/src/gallium/drivers/nouv

[Mesa-dev] [PATCH v2 1/8] nv50/ir: add preliminary support for OP_ADD3

This instruction is new since SM50 (Maxwell) and allows to perform an add with three sources. Unfortunately, it only supports integers. Signed-off-by: Samuel Pitoiset --- src/gallium/drivers/nouveau/codegen/nv50_ir.h| 1 + src/gallium/drivers/nouveau/codegen/nv50_ir_print.cpp

[Mesa-dev] [PATCH v2 7/8] nv50/ir: optimize ADD3(d, a, b, c) to ADD(d, c, a + b)

This is similar to what we already do for MAD/FMA. Signed-off-by: Samuel Pitoiset --- src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp | 11 ++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp b/src/gallium/d

[Mesa-dev] [PATCH v2 4/8] nv50/ir: optimize ADD3(d, a, b, c) to MOV(d, a + b + c)

Signed-off-by: Samuel Pitoiset --- src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp | 11 +++ 1 file changed, 11 insertions(+) diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp index ceb9718..77bac82

[Mesa-dev] [PATCH v2 5/8] nv50/ir: optimize ADD3(d, a, b, 0x0) to ADD(d, a, b)

Signed-off-by: Samuel Pitoiset --- src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp | 8 1 file changed, 8 insertions(+) diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp index 77bac82..ec6418b 10064

[Mesa-dev] [PATCH v2 2/8] gm107/ir: add emission for OP_ADD3

Signed-off-by: Samuel Pitoiset --- .../drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp | 34 ++ 1 file changed, 34 insertions(+) diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp index f1ba27a.

[Mesa-dev] [PATCH v2 3/8] nv50/ir: optimize ADD(ADD(a, b), c) to ADD3(a, b, c)

Signed-off-by: Samuel Pitoiset --- .../drivers/nouveau/codegen/nv50_ir_peephole.cpp | 55 ++ 1 file changed, 55 insertions(+) diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp index 3fc1abf..ceb

Re: [Mesa-dev] [PATCH 02/12] vl: add entry point

Am 19.07.2016 um 00:43 schrieb Boyuan Zhang: Add entrypoint to distinguish H.264 decode and encode. For example, in patch 5/11 when is calling "VaCreateContext", "pps" and "sps" shouldn't be allocated for H.264 encoding. So we need to use the entry_point to determine this is H.264 decode or H.2

Re: [Mesa-dev] [PATCH mesa v2] vl: fix memory leak

Yeah, already done so. Regards, Christian. Am 18.07.2016 um 19:17 schrieb Nayan Deshmukh: Hi Guys, I don't have the push access. Can anyone please push the patch. Thanks, Nayan. On Thu, Jul 14, 2016 at 10:36 AM, Nayan Deshmukh mailto:nayan26deshm...@gmail.com>> wrote: Reviewed-by: Nay

[Mesa-dev] [PATCH 61/95] i965/vec4: do not emit 64-bit MAD

RepCtrl=1 does not work with 64-bit operands so we need to use RepCtrl=0. In that situation, the regioning generated for the sources seems to be equivalent to <4,4,1>:DF, so it will only work for components XY, which means that we have to move any other swizzle to a temporary so that we can source

[Mesa-dev] [PATCH] configure.ac: Use ${datarootdir} for --with-vulkan-icddir help string too

The help string wasn't updated in cbc37f7. Fixes: cbc37f7 ("anv: install the intel_icd.json to ${datarootdir} by default") Signed-off-by: Andreas Boll --- configure.ac | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/configure.ac b/configure.ac index 54416b4..6ea1f2c 100644 -

[Mesa-dev] [PATCH 67/95] i965/vec4: prevent copy-propagation from values with a different type size

Because the meaning of the swizzles and writemasks involved is different, so replacing the source would lead to different semantics. --- src/mesa/drivers/dri/i965/brw_vec4_copy_propagation.cpp | 7 +++ 1 file changed, 7 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_vec4_copy_propag

[Mesa-dev] [PATCH 60/95] i965/vec4/nir: do not emit 64-bit MAD

RepCtrl=1 does not work with 64-bit operands so we need to use RepCtrl=0. In that situation, the regioning generated for the sources seems to be equivalent to <4,4,1>:DF, so it will only work for components XY, which means that we have to move any other swizzle to a temporary so that we can source

[Mesa-dev] [PATCH 63/95] i965/vec4: Fix UBO loads for 64-bit data

We need to emit to 32-bit load messages to load a full dvec4. If only 1 or 2 double components are needed dead-code-elimination will remove the second one. We also need to shuffle the result of the 32-bit messages to form valid 64-bit SIMD4x2 data. --- src/mesa/drivers/dri/i965/brw_vec4_nir.cpp |

[Mesa-dev] [PATCH 64/95] i965/vec4: Fix SSBO loads for 64-bit data

Same requirements as for UBO loads. --- src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 32 -- 1 file changed, 26 insertions(+), 6 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp index 172bf48..5bc1fd5 100

[Mesa-dev] [PATCH 66/95] i965/vec4: don't constant propagate 64-bit immediates

From: Connor Abbott v2: Also check if the instruction source target is 64-bit. (Samuel) Signed-off-by: Samuel Iglesias Gonsálvez --- src/mesa/drivers/dri/i965/brw_vec4_copy_propagation.cpp | 7 +++ 1 file changed, 7 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_vec4_copy_propag

[Mesa-dev] [PATCH 72/95] i965/vec4: Do not use DepCtrl with 64-bit instructions

The BDW PRM says that it is not supported, but it seems that gen7 is also affected, since doing DepCtrl on double-float instructions leads to GPU hangs in some cases, which is probably not surprising knowing that this is not supported in new hardware iterations. The SKL PRMs do not mention this res

[Mesa-dev] [PATCH 65/95] i965/vec4: Fix SSBO stores for 64-bit data

In this case we need to shuffle the 64-bit data before we write it to memory, source from reg_offset + 1 to write components Z and W and consider that each DF channel is twice as big. --- src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 40 -- 1 file changed, 32 insertions(

[Mesa-dev] [PATCH 76/95] i965/vec4: fix scratch reads for 64bit data

--- src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 15 +-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp index 454ad03..6e09778 100644 --- a/src/mesa/drivers/dri/i965/brw

[Mesa-dev] [PATCH 69/95] i965/vec4: don't propagate single-precision uniforms into 4-wide instructions

Otherwise we end up producing code that violates the register region restriction that says that when execsize == width and hstride != 0 the vstride can't be 0. --- src/mesa/drivers/dri/i965/brw_vec4_copy_propagation.cpp | 11 +++ 1 file changed, 11 insertions(+) diff --git a/src/mesa/driv

[Mesa-dev] [PATCH 73/95] i965/vec4: set force_vstride0 on any 64-bit source that has subnr > 0

From: Samuel Iglesias Gonsálvez Sometimes we emit code that has subnr > 0 to select the second half of a DF register (components Z or W). For example, the 64-bit shuffling code does this. For that code to work properly we need to make sure that that we use a vstride=0 on these source registers to

[Mesa-dev] [PATCH 70/95] i965/vec4: don't copy propagate if subnr is set

From: Samuel Iglesias Gonsálvez This means we would copy propagate partial reads or writes and that can affect the result. Signed-off-by: Samuel Iglesias Gonsálvez --- src/mesa/drivers/dri/i965/brw_vec4_copy_propagation.cpp | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/mesa/driver

[Mesa-dev] [PATCH 71/95] i965/vec4: extend the DWORD multiply DepCtrl restriction to all gen8 platforms

--- src/mesa/drivers/dri/i965/brw_vec4.cpp | 9 ++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_vec4.cpp b/src/mesa/drivers/dri/i965/brw_vec4.cpp index e204d81..b4a22d1 100644 --- a/src/mesa/drivers/dri/i965/brw_vec4.cpp +++ b/src/mesa/drivers

[Mesa-dev] [PATCH 75/95] i965/vec4: fix scratch offset for 64bit data

A vec4 is 16 bytes and a dvec4 is 32 bytes so for doubles we have to multiply the reladdr by 2. The reg_offset part is in units of 16 bytes and is used to select the low/high 16-byte chunk of a full dvec4, so we don't want to multiply that part of the address. --- src/mesa/drivers/dri/i965/brw_vec

[Mesa-dev] [PATCH 62/95] i965/vec4: Add a shuffle_64bit_data helper

SIMD4x2 64bit data is stored in register space like this: r0.0:DF x0 y0 z0 w0 r0.1:DF x1 y1 z1 w1 When we need to write data such as this to memory using 32-bit write messages we need to shuffle it in this fashion: r0.0:DF x0 y0 x1 y1 r0.1:DF z0 w0 z1 w1 and emit two 32-bit write messages,

[Mesa-dev] [PATCH 82/95] i965/vec4: fix store output for 64-bit types

We need to shuffle the data before it is written to the URB. Also, dvec3/4 need two vec4 slots. --- src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 19 +++ 1 file changed, 15 insertions(+), 4 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp b/src/mesa/drivers/dri

[Mesa-dev] [PATCH 86/95] i965/vec4/tes: fix input loading for 64bit data types

FIXME: We need to fix the case where not all the attributes fit in the push constant buffer --- src/mesa/drivers/dri/i965/brw_vec4_tes.cpp | 63 +++--- 1 file changed, 48 insertions(+), 15 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_vec4_tes.cpp b/src/mesa/dri

[Mesa-dev] [PATCH 74/95] i965/vec4: do not split scratch read/write opcodes

64-bit scratch read/writes require to shuffle data around so we need to have access to the full 64-bit data. We will do the right thing for these when we emit the messages. --- src/mesa/drivers/dri/i965/brw_vec4.cpp | 9 + 1 file changed, 9 insertions(+) diff --git a/src/mesa/drivers/dri/

[Mesa-dev] [PATCH 81/95] i965/vec4: make emit_pull_constant_load support 64-bit loads

This way callers don't need to know about 64-bit particularities and we reuse some code. --- src/mesa/drivers/dri/i965/brw_vec4.cpp | 22 ++- src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 81 ++ 2 files changed, 50 insertions(+), 53 deletions(-) diff --git a

[Mesa-dev] [PATCH 87/95] i965/vec4/tes: fix setup_payload() for 64bit data types

Use a width of 2 with 64-bit attributes. Also, if we have a dvec split across two registers such that components XY are stored in the second half of a register and components ZW are stored in the first half of the next register, fix up the regioning parameters for channels ZW. --- src/mesa/drivers

[Mesa-dev] [PATCH 91/95] i965/vec4: dump subnr for FIXED_GRF

This came in handy when debugging the payload setup for Tess Eval, since it prints correct subnr for attributes that can be loaded in the second half of a register. --- src/mesa/drivers/dri/i965/brw_vec4.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mesa/drivers/dri/i

[Mesa-dev] [PATCH 85/95] i965/vec4/tcs: fix outputs for 64-bit data

--- src/mesa/drivers/dri/i965/brw_vec4_tcs.cpp | 29 +++-- 1 file changed, 27 insertions(+), 2 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_vec4_tcs.cpp b/src/mesa/drivers/dri/i965/brw_vec4_tcs.cpp index 70f81a0..cdfcefa 100644 --- a/src/mesa/drivers/dri/i965/b

[Mesa-dev] [PATCH 92/95] i965/vec4/scalarize_df: do not scalarize instructions with identity swizzles

We can implement them directly. Also, document other possible improvements for future reference. --- src/mesa/drivers/dri/i965/brw_vec4.cpp | 46 +- 1 file changed, 45 insertions(+), 1 deletion(-) diff --git a/src/mesa/drivers/dri/i965/brw_vec4.cpp b/src/mesa/driv

[Mesa-dev] [PATCH 90/95] i965/vec4: implement force_vstride0 for FIXED_GRF

From: Samuel Iglesias Gonsálvez Signed-off-by: Samuel Iglesias Gonsálvez --- src/mesa/drivers/dri/i965/brw_vec4.cpp | 13 - 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/src/mesa/drivers/dri/i965/brw_vec4.cpp b/src/mesa/drivers/dri/i965/brw_vec4.cpp index f92abe3..1

[Mesa-dev] [PATCH 80/95] i965/vec4: fix move_push_constants_to_pull_constants() for 64-bit data

--- src/mesa/drivers/dri/i965/brw_vec4.cpp | 20 +--- 1 file changed, 17 insertions(+), 3 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_vec4.cpp b/src/mesa/drivers/dri/i965/brw_vec4.cpp index d7fbb5d..5c7a07a 100644 --- a/src/mesa/drivers/dri/i965/brw_vec4.cpp +++ b/src

[Mesa-dev] [PATCH 78/95] i965/vec4: fix move_uniform_array_access_to_pull_constant() for 64-bit data

--- src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 19 +-- 1 file changed, 17 insertions(+), 2 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp index 441a450..40ba648 100644 --- a/src/mesa/drivers/dri/i965

[Mesa-dev] [PATCH 88/95] i965/vec4: split instructions that read 64-bit attrs in TessEval

The tessellation evaluation stage generates source regions with a vstride=0 for these so they hit the gen7 hardware decompression bug. Split them to prevent this. --- src/mesa/drivers/dri/i965/brw_vec4.cpp | 13 - 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/src/mesa/d

[Mesa-dev] [PATCH 77/95] i965/vec4: fix scratch writes for 64bit data

Mostly the same stuff as usual: we ned to shuffle the data before we write and we need to emit two 32-bit write messages (with appropriate 32-bit writemask channels set) for a full dvec4 scratch write. --- src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 64 ++ 1 file chang

[Mesa-dev] [PATCH 79/95] i965/vec4: fix indentation in move_push_constants_to_pull_constants()

--- src/mesa/drivers/dri/i965/brw_vec4.cpp | 60 +- 1 file changed, 30 insertions(+), 30 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_vec4.cpp b/src/mesa/drivers/dri/i965/brw_vec4.cpp index 99b30ce..d7fbb5d 100644 --- a/src/mesa/drivers/dri/i965/brw_vec

[Mesa-dev] [PATCH 89/95] i965/vec4: fix writes to Z/W:DF from a FIXED_GRF

These can happen, for example, in tessellation evaluation when it maps incoming attributes to FIXED_GRF registers. In this case, just as with VGRFs, we need to make sure we have vstride=0 for these to work. --- src/mesa/drivers/dri/i965/brw_vec4.cpp | 3 +-- 1 file changed, 1 insertion(+), 2 delet

[Mesa-dev] [PATCH 83/95] i965/vec4/gs: fix input loading for 64bit data

From: Samuel Iglesias Gonsálvez Signed-off-by: Samuel Iglesias Gonsálvez --- src/mesa/drivers/dri/i965/brw_vec4_gs_nir.cpp | 43 +-- 1 file changed, 28 insertions(+), 15 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_vec4_gs_nir.cpp b/src/mesa/drivers/dri/i965

[Mesa-dev] [PATCH 95/95] i965/gen7: expose OpenGL 4.0 on Haswell

ARB_gpu_shader_fp64 was the last piece missing. Notice that some hardware and kernel combinations do not support pipelined register writes, which are required for some OpenGL 4.0 features, in which case the driver won't expose 4.0. --- src/mesa/drivers/dri/i965/intel_extensions.c | 2 ++ src/mesa/

[Mesa-dev] [PATCH 84/95] i965/vec4/tcs: fix input loading for 64-bit data

--- src/mesa/drivers/dri/i965/brw_vec4_tcs.cpp | 27 --- 1 file changed, 24 insertions(+), 3 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_vec4_tcs.cpp b/src/mesa/drivers/dri/i965/brw_vec4_tcs.cpp index f61c612..70f81a0 100644 --- a/src/mesa/drivers/dri/i965/brw

[Mesa-dev] [PATCH 94/95] i965/vec4: enable ARB_gpu_shader_fp64 for Haswell

--- src/mesa/drivers/dri/i965/intel_extensions.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/mesa/drivers/dri/i965/intel_extensions.c b/src/mesa/drivers/dri/i965/intel_extensions.c index c557137..6ba44b8 100644 --- a/src/mesa/drivers/dri/i965/intel_extensions.c +++ b/src/mesa/drive

[Mesa-dev] [PATCH 93/95] i965/vec4/scalarize_df: Always scalarize XY / ZW writemasks

Now that we are letting some instructions through without being fully scalarized we have to make sure that we do scalarize any that have XY / ZW writemasks, since this don't have native support. --- src/mesa/drivers/dri/i965/brw_vec4.cpp | 10 +- 1 file changed, 9 insertions(+), 1 deletion

[Mesa-dev] [PATCH 68/95] i965/vec4: Prevent copy propagation from violating pre-gen8 restrictions

In gen < 8 instructions that write more than one register need to read more than one register too. Make sure we don't break that restriction by copy propagating from a uniform. --- src/mesa/drivers/dri/i965/brw_vec4_copy_propagation.cpp | 7 +++ 1 file changed, 7 insertions(+) diff --git a/sr

[Mesa-dev] [PATCH 03/95] i965/vec4/nir: allocate two registers for dvec3/dvec4

From: Connor Abbott --- src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp index 6662a1e..1f8fa80 100644 --- a/src/mesa/drivers/dri/i965/brw_ve

[Mesa-dev] [PATCH 01/95] i965/nir: double/dvec2 uniforms only need to be padded to a single vec4 slot

From: Samuel Iglesias Gonsálvez max_vector_size is used in the vec4 backend to pad out the uniform components to match a size that is a multiple of a vec4. Double and dvec2 uniforms only require a single vec4 slot, not two. Signed-off-by: Samuel Iglesias Gonsálvez Signed-off-by: Iago Toral Quir

[Mesa-dev] [PATCH 02/95] i965/vec4/nir: simplify glsl_type_for_nir_alu_type()

From: Connor Abbott Less duplication, one one less case to handle for doubles and support for sized NIR types. v2: Fix call to get_instance by swapping rows and columns params (Iago) Signed-off-by: Iago Toral Quiroga --- src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 16 ++-- 1 file

[Mesa-dev] [PATCH 05/95] i965/vec4/nir: support doubles in ALU operations

Basically, this involves considering the bit-size information to set the appropriate type on both operands and destination. --- src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 12 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp b/

[Mesa-dev] [PATCH 09/95] i965/vec4: add support for printing DF immediates

From: Connor Abbott --- src/mesa/drivers/dri/i965/brw_vec4.cpp | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_vec4.cpp b/src/mesa/drivers/dri/i965/brw_vec4.cpp index 162b481..bf6701e 100644 --- a/src/mesa/drivers/dri/i965/brw_vec4.cpp +++ b/src/mesa/drivers

[Mesa-dev] [PATCH 14/95] i965/vec4: set correct register regions for 32-bit and 64-bit

For 32-bit instructions we want to use <4,4,1> regions for VGRF sources so we should really set a width of 4 (we were setting 8). For 64-bit instructions we want to use a width of 2 because the hardware uses 32-bit swizzles, meaning that we can only address 2 consecutive 64-bit components in a row

[Mesa-dev] [PATCH 24/95] i965/vec4/nir: implement double comparisons

--- src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 21 ++--- 1 file changed, 18 insertions(+), 3 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp index dd06a32..cf35f2e 100644 --- a/src/mesa/drivers/dri/i965/brw_vec4_

[Mesa-dev] [PATCH 04/95] i965/vec4/nir: Add bit-size information to types

--- src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp index 1f8fa80..c5b9715 100644 --- a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp +++ b/s

[Mesa-dev] [PATCH 06/95] i965/vec4/nir: fix nir_intrinsic_load_uniform for doubles

From: Connor Abbott --- src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp index 5a7ee0b..df927e7 100644 --- a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp +++ b/src

[Mesa-dev] [PATCH 10/95] i965/vec4: handle 32 and 64 bit channels in liveness analysis

From: "Juan A. Suarez Romero" Our current data flow analysis does not take into account that channels on 64-bit operands are 64-bit. This is a problem when the same register is accessed using both 64-bit and 32-bit channels. This is very common in operations where we need to access 64-bit data in

[Mesa-dev] [PATCH 19/95] i965/vec4: add VEC4_OPCODE_SET_{LOW, HIGH}_32BIT opcodes

These opcodes will set the low/high 32-bit in each 64-bit data element using Align1 mode. We will use this to implement packDouble2x32. We can't do this in Align16 because we would need data to cross the vec4 boundary. --- src/mesa/drivers/dri/i965/brw_defines.h | 2 ++ src/mesa/drivers

[Mesa-dev] [PATCH 16/95] i965/vec4: We only support 32-bit integer ALU operations for now

Add asserts so we remember to address this when we enable 64-bit integer support, as suggested by Connor and Jason. --- src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 70 ++ 1 file changed, 52 insertions(+), 18 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_vec4

[Mesa-dev] [PATCH 12/95] i965/vec4: translate d2f/f2d

--- src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 24 1 file changed, 24 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp index cbb4dae..1d33fb2 100644 --- a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp +++ b

[Mesa-dev] [PATCH 21/95] i965/vec4: don't copy propagate vector opcodes that operate in align1 mode

Basically, ALIGN1 mode will ignore swizzles on the input vectors so we don't want the copy propagation pass to mess with them. --- .../drivers/dri/i965/brw_vec4_copy_propagation.cpp | 24 ++ 1 file changed, 24 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_vec4_copy_

[Mesa-dev] [PATCH 15/95] i965/disasm: align16 DF source regions have a width of 2

--- src/mesa/drivers/dri/i965/brw_disasm.c | 5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/src/mesa/drivers/dri/i965/brw_disasm.c b/src/mesa/drivers/dri/i965/brw_disasm.c index d74d5d5..c8bdeab 100644 --- a/src/mesa/drivers/dri/i965/brw_disasm.c +++ b/src/mesa/drivers/dri/

[Mesa-dev] [PATCH 28/95] i965/vec4: fix register allocation for 64-bit undef sources

--- src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp index 7b8e30d..65fa057 100644 --- a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp +++ b/src/mes

[Mesa-dev] [PATCH 17/95] i965/vec4: add dst_null_df()

--- src/mesa/drivers/dri/i965/brw_vec4.h | 5 + 1 file changed, 5 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_vec4.h b/src/mesa/drivers/dri/i965/brw_vec4.h index 3043147..afcf31e 100644 --- a/src/mesa/drivers/dri/i965/brw_vec4.h +++ b/src/mesa/drivers/dri/i965/brw_vec4.h @@ -79,

[Mesa-dev] [PATCH 08/95] i965/vec4/nir: fix emitting 64-bit immediates

--- src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 22 ++ 1 file changed, 18 insertions(+), 4 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp index 095a27d..cbb4dae 100644 --- a/src/mesa/drivers/dri/i965/brw_vec4

Re: [Mesa-dev] [PATCH 07/10] egl/android: Make drm_gralloc headers optional

On 19 July 2016 at 04:21, Tomasz Figa wrote: > On Tue, Jul 19, 2016 at 2:35 AM, Emil Velikov > wrote: >> On 18 July 2016 at 16:38, Tomasz Figa wrote: >>> On Mon, Jul 18, 2016 at 11:58 PM, Emil Velikov >>> wrote: On 18 July 2016 at 13:02, Tomasz Figa wrote: > On Mon, Jul 18, 2016 at

[Mesa-dev] [PATCH 00/95] i965 Haswell ARB_gpu_shader_fp64 / OpenGL 4.0

Hi, this series implements initial support for Haswell align16 FP64, and with that we can enable FP64 and OpenGL 4.0 in Haswell. Gen8+ is now fully scalar, so the patches focus on gen7 and Haswell specifically (although they do mention what things are not expected to work outside gen7 for futur

[Mesa-dev] [PATCH 22/95] i965/vec4: implement double unpacking

--- src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 12 1 file changed, 12 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp index 25fd1fe..82bf927 100644 --- a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp +++ b/src/mesa/dr

[Mesa-dev] [PATCH 13/95] i965: add brw_vecn_grf()

From: Connor Abbott --- src/mesa/drivers/dri/i965/brw_reg.h | 6 ++ 1 file changed, 6 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_reg.h b/src/mesa/drivers/dri/i965/brw_reg.h index 38cf8e3..e4c3e7a 100644 --- a/src/mesa/drivers/dri/i965/brw_reg.h +++ b/src/mesa/drivers/dri/i965

[Mesa-dev] [PATCH 26/95] i965/vec4: fix get_nir_dest() to use DF type for 64-bit destinations

--- src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 13 ++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp index fde7b60..7b8e30d 100644 --- a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp

[Mesa-dev] [PATCH 50/95] i965/vec4: Use force_vstride0 to fix DF Z/W writes from X/Y channels

A source region like <2,2,1>.xyxy:DF selects XXZZ of a dvec4. If we have code such as: mov g2.z g4.x This creates a problem because we end up writing g4.z in g2.z. To fix this we want to generate a region and we can do that by exploiting again the vstride=0 behavior of the hardware in gen7.

[Mesa-dev] [PATCH 47/95] i965/vec4: translate 64-bit swizzles to 32-bit

The hardware can only operate with 32-bit swizzles, which is a rather limiting restriction. However, the idea is not to expose this to the optimization passes, which would be a mess to deal with. Instead, we let the bulk of the vec4 backend ignore this fact and we fix the swizzles right before code

[Mesa-dev] [PATCH 36/95] i965/vec4: add a helper function to create double immediates

Gen7 hardware does not support double immediates so these need to be moved in 32-bit chunks to a regular vgrf instead. Instead of doing this every time we need to create a DF immediate, create a helper function that does the right thing depending on the hardware generation. Signed-off-by: Samuel I

[Mesa-dev] [PATCH 42/95] i965/vec4: dump NibCtrl for instructions with execsize 4

--- src/mesa/drivers/dri/i965/brw_vec4.cpp | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_vec4.cpp b/src/mesa/drivers/dri/i965/brw_vec4.cpp index 829b7d3..88bf895 100644 --- a/src/mesa/drivers/dri/i965/brw_vec4.cpp +++ b/src/mesa/drivers/dri/i965/brw_vec4.cpp

[Mesa-dev] [PATCH 48/95] i965/vec4: add a force_vstride0 flag to src_reg

We will use this in cases where we want to force the vstride of a src_reg to 0 to exploit a particular behavior of the hardware. It will come in handy to implement access to components Z/W. --- src/mesa/drivers/dri/i965/brw_ir_vec4.h | 1 + src/mesa/drivers/dri/i965/brw_vec4.cpp | 2 ++ 2 files c

[Mesa-dev] [PATCH 32/95] i965/vec4: implement d2i, d2u, i2d and u2d

--- src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 14 ++ 1 file changed, 14 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp index 81389a9..1525a3d 100644 --- a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp +++ b/src/mesa/

[Mesa-dev] [PATCH 41/95] i965/vec4: make the generator set correct NibCtrl for SIMD4 DF instructions

From the HSW PRM, Command Reference, QtrCtrl: "NibCtrl is only allowed for SIMD4 instructions with a DF (Double Float) source or destination type." v2 (Samuel): Assert that the type is DF. Signed-off-by: Samuel Iglesias Gonsálvez --- src/mesa/drivers/dri/i965/brw_vec4_generator.cpp | 9

[Mesa-dev] [PATCH 37/95] i965/vec4: use the new helper function to create double immediates

From: Samuel Iglesias Gonsálvez Signed-off-by: Samuel Iglesias Gonsálvez --- src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp index 8a45fd

[Mesa-dev] [PATCH 31/95] i965/vec4: implement hardware workaround for align16 double to float conversion

From the BDW PRM, Workarounds chapter: "DF->f format conversion for Align16 has wrong emask calculation when source is immediate." So detect the case and move the immediate source to a VGRF before we attempt the conversion. Notice that Broadwell and later are strictly scalar at the moment

[Mesa-dev] [PATCH 34/95] i965/vec4: implement fsign() for doubles

--- src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 57 ++ 1 file changed, 42 insertions(+), 15 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp index 4014020..c9b8edf 100644 --- a/src/mesa/drivers/dri/i965

[Mesa-dev] [PATCH 40/95] i965/vec4: add a SIMD lowering pass

Generally, instructions in Align16 mode only ever write to a single register and don't need anny form of SIMD splitting, that's why we have never had a SIMD splitting pass in the vec4 backend. However, double-precision instructions typically write 2 registers and in some cases they run into certain

[Mesa-dev] [PATCH 29/95] i965/vec4: Rename DF to/from F generator opcodes

The opcodes are not specific for conversions to/from float since we need the same for conversions to/from other 32-bit types. Rename the opcodes accordingly and change the asserts to check the size of the types involved instead. --- src/mesa/drivers/dri/i965/brw_defines.h | 4 ++--

[Mesa-dev] [PATCH 38/95] i965/vec4: allow the vec4 IR to indicate the execution size of instructions

In the vec4 backend the generator sets the execution size for all instructions to 8, however, we will have to split certain DF instructions to have an execution size of 4, so we need to indicate this explicitly in the IR for the generator to set the right execution size for them. We will use this

[Mesa-dev] [PATCH 07/95] i965/vec4/nir: set the right type for 64-bit registers

From: Connor Abbott --- src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp index df927e7..095a27d 100644 --- a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp +++ b/

[Mesa-dev] [PATCH 25/95] i965/vec4: fix base offset for nir_registers with doubles

--- src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 8 +--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp index cf35f2e..fde7b60 100644 --- a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp +++ b/s

[Mesa-dev] [PATCH 30/95] i965/vec4: add helpers for conversions to/from doubles

Use these helpers to implement d2f and f2d. We will reuse these helpers when we implement things like d2i or i2d as well. --- src/mesa/drivers/dri/i965/brw_vec4.h | 5 +++ src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 53 +++--- 2 files changed, 38 insertions(+), 20 d

[Mesa-dev] [PATCH 20/95] i965/vec4: Fix DCE for VEC4_OPCODE_SET_{LOW, HIGH}_32BIT

These opcodes do partial writes of 64-bit data. The problem is that we intend to use them to write on the same register to implement packDouble2x32 and from the point of view of DCE, since both opcodes write to the same register, only the last one stands and decides to eliminate the first, which is

[Mesa-dev] [PATCH 46/95] i965/vec4: add a scalarization pass for double-precision instructions

The hardware only supports 32-bit swizzles, which means that a swizzle like XYZW only selects channels XY of a DF, making access to channels ZW more difficult, specially considering the various regioning restrictions imposed by the hardware. The combination of both things makes handling ramdom swiz

[Mesa-dev] [PATCH 23/95] i965/vec4: implement double packing

--- src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 11 +++ 1 file changed, 11 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp index 82bf927..dd06a32 100644 --- a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp +++ b/src/mesa/dri

[Mesa-dev] [PATCH 11/95] i965/vec4: add double/float conversion pseudo-opcodes

These need to be emitted as align1 MOV's, since they need to have a stride of 2 on the float register (whether src or dest) so that data from another thread doesn't cross the middle of a SIMD8 register. v2 (Iago): - The float-to-double needs to align 32-bit data to 64-bit before doing the conversi

[Mesa-dev] [PATCH 27/95] i965/vec4: make opt_vector_float ignore doubles

The pass does not support doubles in its current form. I'm not even sure that it should, since it would basically change the type of the operation and that could have implications for things like SSBO writes, etc. --- src/mesa/drivers/dri/i965/brw_vec4.cpp | 1 + 1 file changed, 1 insertion(+) di

[Mesa-dev] [PATCH 18/95] i965/vec4: add VEC4_OPCODE_PICK_{LOW, HIGH}_32BIT opcodes

These opcodes will pick the low/high 32-bit in each 64-bit data element using Align1 mode. We will use this, for example, to things like unpackDouble2x32. We can't do this in Align16 because we would need data to cross the vec4 boundary. --- src/mesa/drivers/dri/i965/brw_defines.h | 2 +

[Mesa-dev] [PATCH 33/95] i965/vec4: implement d2b

--- src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 18 ++ 1 file changed, 18 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp index 1525a3d..4014020 100644 --- a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp +++ b/src/m

[Mesa-dev] [PATCH 39/95] i965/vec4: dump the instruction execution size

--- src/mesa/drivers/dri/i965/brw_vec4.cpp | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/mesa/drivers/dri/i965/brw_vec4.cpp b/src/mesa/drivers/dri/i965/brw_vec4.cpp index c55d594..8316691 100644 --- a/src/mesa/drivers/dri/i965/brw_vec4.cpp +++ b/src/mesa/drivers/dri/i9

[Mesa-dev] [PATCH 57/95] i965/vec4: fix pack_uniform_registers for doubles

We need to consider the fact that dvec3/4 require two vec4 slots. --- src/mesa/drivers/dri/i965/brw_vec4.cpp | 11 +-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_vec4.cpp b/src/mesa/drivers/dri/i965/brw_vec4.cpp index 1b190ab..95b408e 10064

[Mesa-dev] [PATCH 54/95] i965/vec4: fix regs_read() for doubles

--- src/mesa/drivers/dri/i965/brw_vec4.cpp | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_vec4.cpp b/src/mesa/drivers/dri/i965/brw_vec4.cpp index 9400baa..a366548 100644 --- a/src/mesa/drivers/dri/i965/brw_vec4.cpp +++ b/src/mesa/drivers/dri/i965/brw_vec4.cpp

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