---
src/mesa/drivers/dri/i965/brw_vec4_tcs.cpp | 29 +++++++++++++++++++++++++++--
1 file changed, 27 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_tcs.cpp
b/src/mesa/drivers/dri/i965/brw_vec4_tcs.cpp
index 70f81a0..cdfcefa 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_tcs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_tcs.cpp
@@ -423,8 +423,33 @@ vec4_tcs_visitor::nir_emit_intrinsic(nir_intrinsic_instr
*instr)
}
}
- emit_urb_write(swizzle(value, swiz), mask,
- imm_offset, indirect_offset);
+ if (nir_src_bit_size(instr->src[0]) == 64) {
+ /* For 64-bit data we need to shuffle the data before we write and
+ * emit two messages. Also, since each channel is twice as large we
+ * need to fix the writemask in each 32-bit message to account for it.
+ */
+ value = swizzle(retype(value, BRW_REGISTER_TYPE_DF), swiz);
+ dst_reg shuffled = dst_reg(this, glsl_type::dvec4_type);
+ shuffle_64bit_data(shuffled, value, true);
+ src_reg shuffled_float = src_reg(retype(shuffled,
BRW_REGISTER_TYPE_F));
+
+ for (int n = 0; n < 2; n++) {
+ unsigned fixed_mask = 0;
+ if (mask & WRITEMASK_X)
+ fixed_mask |= WRITEMASK_XY;
+ if (mask & WRITEMASK_Y)
+ fixed_mask |= WRITEMASK_ZW;
+ emit_urb_write(shuffled_float, fixed_mask,
+ imm_offset, indirect_offset);
+
+ shuffled_float = offset(shuffled_float, 1);
+ mask >>= 2;
+ imm_offset++;
+ }
+ } else {
+ emit_urb_write(swizzle(value, swiz), mask,
+ imm_offset, indirect_offset);
+ }
break;
}
--
2.7.4
_______________________________________________
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev
