Use a width of 2 with 64-bit attributes. Also, if we have a dvec
split across two registers such that components XY are stored in
the second half of a register and components ZW are stored in the
first half of the next register, fix up the regioning parameters
for channels ZW.
---
src/mesa/drivers/dri/i965/brw_vec4_tes.cpp | 20 +++++++++++++++++++-
1 file changed, 19 insertions(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_tes.cpp
b/src/mesa/drivers/dri/i965/brw_vec4_tes.cpp
index 8febc15..1a85acb 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_tes.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_tes.cpp
@@ -82,14 +82,32 @@ vec4_tes_visitor::setup_payload()
if (inst->src[i].file != ATTR)
continue;
+ bool is_64bit = type_sz(inst->src[i].type) == 8;
+
struct brw_reg grf =
brw_vec4_grf(reg + inst->src[i].nr / 2, 4 * (inst->src[i].nr % 2));
- grf = stride(grf, 0, 4, 1);
+ grf = stride(grf, 0, is_64bit ? 2 : 4, 1);
grf.swizzle = inst->src[i].swizzle;
grf.type = inst->src[i].type;
grf.abs = inst->src[i].abs;
grf.negate = inst->src[i].negate;
+ /* For 64-bit attributes we can end up with components XY in the
+ * second half of a register and components ZW in the first half
+ * of the next. Fix it up here.
+ */
+ if (is_64bit && grf.subnr > 0) {
+ /* If we ever use non-single swizzles with 64bit types this
+ * won't be so easy but for now it is all that we need to do.
+ */
+ assert(brw_is_single_value_swizzle(grf.swizzle));
+ if (grf.swizzle > BRW_SWIZZLE_YYYY) {
+ grf.subnr = 0;
+ grf.nr++;
+ grf.swizzle -= BRW_SWIZZLE_ZZZZ;
+ }
+ }
+
inst->src[i] = grf;
}
}
--
2.7.4
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