On Wed, Sep 16, 2015 at 1:14 AM, Samuel Iglesias Gonsálvez
wrote:
>
>
> On 15/09/15 21:03, Jordan Justen wrote:
>> On 2015-09-10 22:48:55, Samuel Iglesias Gonsálvez wrote:
>>> On 10/09/15 20:13, Jordan Justen wrote:
On 2015-09-10 06:35:41, Iago Toral Quiroga wrote:
> From: Samuel Iglesias
On 16/09/15 09:11, Ilia Mirkin wrote:
> On Wed, Sep 16, 2015 at 1:14 AM, Samuel Iglesias Gonsálvez
> wrote:
>>
>>
>> On 15/09/15 21:03, Jordan Justen wrote:
>>> On 2015-09-10 22:48:55, Samuel Iglesias Gonsálvez wrote:
On 10/09/15 20:13, Jordan Justen wrote:
> On 2015-09-10 06:35:41, Iag
On 2015-09-10 06:35:44, Iago Toral Quiroga wrote:
> From: Samuel Iglesias Gonsalvez
>
> v2:
> - Get interface packing information from interface's type, not the variable
> type.
> - Simplify is_std430 condition in emit_access() for readability (Jordan)
> - Add a commment explaing why array of th
On 16/09/15 09:46, Jordan Justen wrote:
> On 2015-09-10 06:35:44, Iago Toral Quiroga wrote:
>> From: Samuel Iglesias Gonsalvez
>>
>> v2:
>> - Get interface packing information from interface's type, not the variable
>> type.
>> - Simplify is_std430 condition in emit_access() for readability (Jo
On Wed, Sep 16, 2015 at 3:45 AM, Samuel Iglesias Gonsálvez
wrote:
>
>
> On 16/09/15 09:11, Ilia Mirkin wrote:
>> On Wed, Sep 16, 2015 at 1:14 AM, Samuel Iglesias Gonsálvez
>> wrote:
>>>
>>>
>>> On 15/09/15 21:03, Jordan Justen wrote:
On 2015-09-10 22:48:55, Samuel Iglesias Gonsálvez wrote:
>
On 16/09/15 10:39, Ilia Mirkin wrote:
> On Wed, Sep 16, 2015 at 3:45 AM, Samuel Iglesias Gonsálvez
> wrote:
>>
>>
>> On 16/09/15 09:11, Ilia Mirkin wrote:
>>> On Wed, Sep 16, 2015 at 1:14 AM, Samuel Iglesias Gonsálvez
>>> wrote:
On 15/09/15 21:03, Jordan Justen wrote:
> On 20
It seems that we have some bugs where we fail to compile shaders in gen6
because we do not having enough MRF registers available (see bugs 86469 and
90631 for example). That triggered some discussion about the fact that SNB
might actually have 24 MRF registers available, but since the docs where no
---
src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp | 11 +++
1 file changed, 7 insertions(+), 4 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
b/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
index 21fb3de..6900cee 100644
--- a/src/mesa/drivers/dri/i965
In a later patch we will make BRW_MAX_MRF return a different value depending
on the hardware generation, but it is inconvenient to add a gen parameter
to the brw_reg functions only for the assertions, so move them to the generator
where checking for this is easier.
FIXME: we would still need to ad
---
src/mesa/drivers/dri/i965/brw_eu_emit.c | 2 +-
src/mesa/drivers/dri/i965/brw_fs.cpp| 4 ++--
src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 12 ++--
src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp | 16
src/mesa
https://bugs.freedesktop.org/show_bug.cgi?id=92020
Bug ID: 92020
Summary: wglCreatePbufferARB handle attrib error
Product: Mesa
Version: 11.0
Hardware: x86 (IA32)
OS: Windows (All)
Status: NEW
Severity: no
On Tue, Sep 15, 2015 at 4:23 PM, Ulrich Weigand wrote:
>
> Various pieces of code to create compressed textures will first
> generate an uncompressed RGBA texture into a temporary buffer,
> and then read from that buffer while creating the final compressed
> texture in the requested format.
>
> Th
https://bugs.freedesktop.org/show_bug.cgi?id=92020
Emil Velikov changed:
What|Removed |Added
Component|EGL |Other
--- Comment #1 from Emil Velikov -
Reviewed-by: Iago Toral Quiroga
On Tue, 2015-09-15 at 17:40 -0400, Rob Clark wrote:
> From: Rob Clark
>
> Signed-off-by: Rob Clark
> ---
> src/glsl/nir/nir.h| 3 +++
> src/glsl/nir/nir_opt_algebraic.py | 1 +
> 2 files changed, 4 insertions(+)
>
> diff --git a/src/glsl/nir/ni
From: Rob Clark
Rename print_var_state to print_state, and stuff FILE ptr into the state
object. This avoids passing around an extra parameter everywhere.
v2: even more extensive conversion.. use state *everywhere* instead of
FILE ptr, and convert nir_print_instr() to use state as well
Signed-
https://bugs.freedesktop.org/show_bug.cgi?id=92020
--- Comment #2 from zeif <332447...@qq.com> ---
(In reply to Emil Velikov from comment #1)
> Hi zeif,
>
> This looks like a user error, rather than a mesa bug.
>
> Namely, I suspect that you're feeding attrib as defined by some extension,
> with
https://bugs.freedesktop.org/show_bug.cgi?id=92022
Bug ID: 92022
Summary: st/va: add initial support for Video Post Processing
and Export/Import of VaSurface
Product: Mesa
Version: git
Hardware: Other
OS: Al
https://bugs.freedesktop.org/show_bug.cgi?id=92022
Julien Isorce changed:
What|Removed |Added
CC||deathsim...@vodafone.de,
Looks good,
Reviewed-by: Iago Toral Quiroga
On Wed, 2015-09-16 at 08:25 -0400, Rob Clark wrote:
> From: Rob Clark
>
> Rename print_var_state to print_state, and stuff FILE ptr into the state
> object. This avoids passing around an extra parameter everywhere.
>
> v2: even more extensive conve
XA has been using L8_UNORM for a8 and yuv component surfaces.
This commit instead makes XA prefer R8_UNORM since it's assumed to have a
higher availability.
Also neither of these formats are suitable as destination formats using
destination alpha blending, so reject those operations.
Signed-off-b
Since there are no formats where block.bits isn't a multiple of 8 (and I
wouldn't expect that to change), you could theoretically fix that by
dividing by block.bits / 8 instead of multiplying base (or size) by 8.
Ought to be faster at least on 32bit systems...
Unless you wanted to support >= 4GB bu
On Tue, Sep 15, 2015 at 8:23 PM, Brian Paul wrote:
> Move this code out of bufferobj.c since it's not strongly connected to
> buffer objects.
> ---
Seems fine to me, and bonus points for removing now unneeded #includes! :)
Acked-by: Matt Turner
___
me
On Tue, Sep 15, 2015 at 10:38 AM, Arlie Davis wrote:
>
> Hello! I noticed an inefficiency in libGL.so, so I thought I'd take a
> stab at fixing it. This is my first patch submitted to mesa-dev, so
> if I'm doing anything dumb, let me know. I can't use git send-email,
> but I've formatted the pa
On Wed, Sep 16, 2015 at 8:25 AM, Rob Clark wrote:
> From: Rob Clark
>
> Rename print_var_state to print_state, and stuff FILE ptr into the state
> object. This avoids passing around an extra parameter everywhere.
>
> v2: even more extensive conversion.. use state *everywhere* instead of
> FILE p
On 09/16/2015 07:04 AM, Thomas Hellstrom wrote:
XA has been using L8_UNORM for a8 and yuv component surfaces.
This commit instead makes XA prefer R8_UNORM since it's assumed to have a
higher availability.
Also neither of these formats are suitable as destination formats using
destination alpha b
https://bugs.freedesktop.org/show_bug.cgi?id=92020
--- Comment #3 from Emil Velikov ---
Congratulations - seems like you found a bug in the emulator :-)
I would suggest taking a closer look into the emulator code.
To do things properly it should:
1. Create OpenGL context
2. Call wglGetProcAddre
https://bugs.freedesktop.org/show_bug.cgi?id=92020
--- Comment #4 from Emil Velikov ---
While one's in the emulator they could also fix the strstr in
wglGetExtentionsProcAddress.
Currently it will trigger whenever it finds FooBar, even if it's looking for
Foo.
--
You are receiving this mail be
Hi Rob,
On 16 September 2015 at 00:33, Rob Clark wrote:
> diff --git a/src/mesa/Makefile.sources b/src/mesa/Makefile.sources
> index ed9848c..2a719a0 100644
> --- a/src/mesa/Makefile.sources
> +++ b/src/mesa/Makefile.sources
> @@ -523,7 +523,9 @@ PROGRAM_FILES = \
> program/sampler.h \
>
On Wed, Sep 16, 2015 at 11:22 AM, Emil Velikov wrote:
> Hi Rob,
>
> On 16 September 2015 at 00:33, Rob Clark wrote:
>
>> diff --git a/src/mesa/Makefile.sources b/src/mesa/Makefile.sources
>> index ed9848c..2a719a0 100644
>> --- a/src/mesa/Makefile.sources
>> +++ b/src/mesa/Makefile.sources
>> @@
From: Matthew Waters
Move all the enums but CONTEXT_FLAGS. The spec seems quite explicit
about the latter (wrt OpenGL ES)
"In OpenGL ES versions prior to and including ES 3.1 there is no
CONTEXT_FLAGS state and therefore the CONTEXT_FLAG_DEBUG_BIT cannot
be queried."
v2 [Emil Veliko
On Wed, Sep 16, 2015 at 9:21 AM, Roland Scheidegger wrote:
> Since there are no formats where block.bits isn't a multiple of 8 (and I
> wouldn't expect that to change), you could theoretically fix that by
> dividing by block.bits / 8 instead of multiplying base (or size) by 8.
> Ought to be faster
The null check is safe to remove, for two reasons. First, we're allocating
with calloc, so we know for sure that the entire structure is zero-filled.
Second, we're assigning every byte of the table, so we don't even need to
rely on zero-filling it. (If this were a function that was frequently
cal
On Tue, Sep 15, 2015 at 3:01 PM, Anuj Phogat wrote:
>
>
> On Fri, Aug 28, 2015 at 7:50 AM, Nanley Chery
> wrote:
>
>> From: Nanley Chery
>>
>> Reuse utility functions instead of reimplementing the same logic.
>>
>> * _mesa_is_compressed_format() performs the required checking to
>> determine
On Wed, Sep 16, 2015 at 10:15 AM, Nanley Chery
wrote:
>
>
> On Tue, Sep 15, 2015 at 3:01 PM, Anuj Phogat
> wrote:
>
>>
>>
>> On Fri, Aug 28, 2015 at 7:50 AM, Nanley Chery
>> wrote:
>>
>>> From: Nanley Chery
>>>
>>> Reuse utility functions instead of reimplementing the same logic.
>>>
>>> * _me
https://bugs.freedesktop.org/show_bug.cgi?id=92022
Julien Isorce changed:
What|Removed |Added
CC||gb.de...@gmail.com,
|
When updating texture buffers, we might end up replacing the whole
buffer. Check that the tic address matches the resource address, and if
not, update the tic and reupload it.
This fixes:
arb_direct_state_access-texture-buffer
arb_texture_buffer_object-data-sync
Signed-off-by: Ilia Mirkin
Cc
https://bugs.freedesktop.org/show_bug.cgi?id=92022
--- Comment #2 from Ilia Mirkin ---
(In reply to Julien Isorce from comment #0)
> Just let know I did a first attempt to add VPP and
> VaAcquireBufferHandle(dmabuf) to st/va:
>
> https://github.com/CapOM/mesa/commits/wip_export_import_and_vpp
>
https://bugs.freedesktop.org/show_bug.cgi?id=92022
Ilia Mirkin changed:
What|Removed |Added
CC|imir...@alum.mit.edu|
--
You are receiving this mail because:
From: Rob Clark
Signed-off-by: Rob Clark
---
.../drivers/freedreno/ir3/ir3_compiler_nir.c | 53 --
1 file changed, 28 insertions(+), 25 deletions(-)
diff --git a/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
b/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir
From: Rob Clark
Split this out to reduce noise in later patches.
Signed-off-by: Rob Clark
---
src/glsl/nir/nir_lower_tex_projector.c | 146 +
1 file changed, 77 insertions(+), 69 deletions(-)
diff --git a/src/glsl/nir/nir_lower_tex_projector.c
b/src/glsl/nir/n
From: Rob Clark
Some hardware needs to clamp texture coordinates to [0.0, 1.0] in the
shader to emulate GL_CLAMP. This is added to lower_tex_proj since, in
the case of projected coords, the clamping needs to happen *after*
projection.
Signed-off-by: Rob Clark
---
src/glsl/nir/nir.h
From: Rob Clark
Some hardware, such as adreno a3xx, supports txp on some but not all
sampler types. In this case we want more fine grained control over
which texture projectors get lowered.
Signed-off-by: Rob Clark
---
src/glsl/nir/nir.h | 2 +-
src/glsl/nir/nir_lower_tex
On Wed, Sep 16, 2015 at 2:07 PM, Rob Clark wrote:
> From: Rob Clark
>
> Some hardware, such as adreno a3xx, supports txp on some but not all
> sampler types. In this case we want more fine grained control over
> which texture projectors get lowered.
I mentioned this on IRC, but should probably
On Wed, Sep 16, 2015 at 2:07 PM, Rob Clark wrote:
> From: Rob Clark
>
> Some hardware needs to clamp texture coordinates to [0.0, 1.0] in the
> shader to emulate GL_CLAMP. This is added to lower_tex_proj since, in
> the case of projected coords, the clamping needs to happen *after*
> projection.
On 2015-09-16 01:01:30, Samuel Iglesias Gonsálvez wrote:
>
>
> On 16/09/15 09:46, Jordan Justen wrote:
> > On 2015-09-10 06:35:44, Iago Toral Quiroga wrote:
> >> From: Samuel Iglesias Gonsalvez
> >>
> >> v2:
> >> - Get interface packing information from interface's type, not the
> >> variable t
On Wednesday, September 16, 2015 11:17:53 AM Iago Toral Quiroga wrote:
> It seems that we have some bugs where we fail to compile shaders in gen6
> because we do not having enough MRF registers available (see bugs 86469 and
> 90631 for example). That triggered some discussion about the fact that SN
On the review of the patch "i965/nir/vec4: fill the type of the dst
and src when loading an uniform" Jason Ekstrand suggested to change
the optimization pass in order to allow the copy propagation with
MOVs even if there is a type mismatch, as was done on the fs path,
instead of fixing the type for
SEL and MOV instructions, as long as they don't have source modifiers, are
just copying bits around. So those kind of instruction could be propagated
even if there are type mismatches. This is needed because NIR generates
integer SEL and MOV instructions whenever it doesn't know what else to
gener
SEL and MOV instructions, as long as they don't have source modifiers, are
just copying bits around. So those kind of instruction could be propagated
even if there are type mismatches. This is needed because NIR generates
integer SEL and MOV instructions whenever it doesn't know what else to
gener
https://bugs.freedesktop.org/show_bug.cgi?id=79783
--- Comment #3 from gregory.hain...@gmail.com ---
I have the same issue on my application (PCSX2).
The code in link_varyings.cpp (varying_matches::record) is potentially wrong
but it isn't the main issue. I try to comment the code and the issue i
https://bugs.freedesktop.org/show_bug.cgi?id=79783
--- Comment #4 from Ilia Mirkin ---
(In reply to gregory.hainaut from comment #3)
> Unfortunately I don't know if there is any
> possibility to dump VS asm code with Nouveau.
NV50_PROG_DEBUG=1 (assuming you've built mesa with --enable-debug) sho
This reverts commit 48961fa3ba37999a6f8fd812458b735e39604a95.
glamor/Xwayland use this, the spec saying something when it
was written, and the fact that the comment says Mesa relies on it
hasn't changed.
I also don't have a copy of this patch in my mail archive, which
seems wierd, did it get post
https://bugs.freedesktop.org/show_bug.cgi?id=92022
Julien Isorce changed:
What|Removed |Added
Severity|normal |enhancement
--- Comment #3 from Julien I
On Wed, Sep 16, 2015 at 2:11 PM, Ilia Mirkin wrote:
> On Wed, Sep 16, 2015 at 2:07 PM, Rob Clark wrote:
>> From: Rob Clark
>>
>> Some hardware, such as adreno a3xx, supports txp on some but not all
>> sampler types. In this case we want more fine grained control over
>> which texture projectors
On Wed, Sep 16, 2015 at 12:47 PM, Alejandro Piñeiro
wrote:
> SEL and MOV instructions, as long as they don't have source modifiers, are
> just copying bits around. So those kind of instruction could be propagated
> even if there are type mismatches. This is needed because NIR generates
> integer
On Wed, Sep 16, 2015 at 12:47 PM, Alejandro Piñeiro
wrote:
> SEL and MOV instructions, as long as they don't have source modifiers, are
> just copying bits around. So those kind of instruction could be propagated
> even if there are type mismatches. This is needed because NIR generates
> integer
On Wed, Sep 16, 2015 at 12:47 PM, Alejandro Piñeiro
wrote:
> On the review of the patch "i965/nir/vec4: fill the type of the dst
> and src when loading an uniform" Jason Ekstrand suggested to change
> the optimization pass in order to allow the copy propagation with
> MOVs even if there is a type
On Fri 11 Sep 2015, Ville Syrjälä wrote:
> As it turns out I was just looking at Yf and whatnot from display POV,
> and I came to the conclusion that I'll change the kernel to just have a
> function to return the tile width in bytes based on the cpp passed in,
> and then I can simply compute tile
On Wed 19 Aug 2015, Anuj Phogat wrote:
> This will require change in the parameters passed to
> intel_miptree_get_tile_masks().
>
> V2: Rearrange the order of parameters. (Ben)
> Change the name to intel_get_tile_masks(). (Topi)
>
> Cc: Ben Widawsky
> Cc: Topi Pohjolainen
> Signed-off-by: A
On Wed 19 Aug 2015, Anuj Phogat wrote:
> It takes care of using the correct tile width if we later use other
> tiling patterns for aux miptree.
>
> V2: Remove the comment about using Yf for aux miptree.
>
> Cc: Ben Widawsky
> Signed-off-by: Anuj Phogat
> ---
> src/mesa/drivers/dri/i965/gen8_su
On Wed 19 Aug 2015, Anuj Phogat wrote:
> Signed-off-by: Anuj Phogat
> ---
> src/mesa/drivers/dri/i965/intel_blit.c | 25 +
> 1 file changed, 9 insertions(+), 16 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/intel_blit.c
> b/src/mesa/drivers/dri/i965/intel_blit.
On Wed 19 Aug 2015, Anuj Phogat wrote:
> Current code checks the alignment restrictions only for Y tiling.
> From Broadwell PRM vol 10:
>
> "pitch is of 512Byte granularity for Tile-X: This means the tiled-x
> surface pitch can be (512, 1024, 1536, 2048...)/4 (in Dwords)."
>
> This patch adds
On Wed 19 Aug 2015, Anuj Phogat wrote:
> I misinterpreted the alignmnet restriction in XY_FAST_COPY_BLT earlier.
> Instead of checking pitch for 64KB alignmnet we need to check it for
> tile widh alignment.
>
> Signed-off-by: Anuj Phogat
> Cc: Ben Widawsky
> ---
> src/mesa/drivers/dri/i965/inte
On Wed 19 Aug 2015, Anuj Phogat wrote:
> This function isn't specific to miptrees. So, drop the "miptree"
> from function name.
>
> Signed-off-by: Anuj Phogat
> ---
> src/mesa/drivers/dri/i965/intel_fbo.c | 2 +-
> src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 6 +++---
> src/mesa/dr
On Sun, Sep 13, 2015 at 11:51 AM, Rob Clark wrote:
> From: Rob Clark
>
> Used internally in freedreno/ir3 to calc stream-out position. Seems
> like a generic enough way to implement stream-out (using str instrs),
> plus it avoids compiler warnings by sneaking in a non-enum value in
> switch stat
On Wed, Sep 16, 2015 at 7:30 PM, Rob Clark wrote:
> On Sun, Sep 13, 2015 at 11:51 AM, Rob Clark wrote:
>> From: Rob Clark
>>
>> Used internally in freedreno/ir3 to calc stream-out position. Seems
>> like a generic enough way to implement stream-out (using str instrs),
>> plus it avoids compiler
On Wed, Sep 16, 2015 at 7:34 PM, Ilia Mirkin wrote:
> On Wed, Sep 16, 2015 at 7:30 PM, Rob Clark wrote:
>> On Sun, Sep 13, 2015 at 11:51 AM, Rob Clark wrote:
>>> From: Rob Clark
>>>
>>> Used internally in freedreno/ir3 to calc stream-out position. Seems
>>> like a generic enough way to impleme
https://bugs.freedesktop.org/show_bug.cgi?id=92020
--- Comment #5 from zeif <332447...@qq.com> ---
(In reply to Emil Velikov from comment #4)
> While one's in the emulator they could also fix the strstr in
> wglGetExtentionsProcAddress.
>
> Currently it will trigger whenever it finds FooBar, even
Am 16.09.2015 23:00, schrieb Dave Airlie:
This reverts commit 48961fa3ba37999a6f8fd812458b735e39604a95.
glamor/Xwayland use this, the spec saying something when it
was written, and the fact that the comment says Mesa relies on it
hasn't changed.
Thank you Dave!
r600g - NI/Turks works again wit
This fixes the newly-added arb_texture_buffer_object-bufferstorage
piglit test.
Signed-off-by: Ilia Mirkin
Cc: "11.0"
---
src/gallium/drivers/nouveau/nv50/nv50_vbo.c | 19 +++
src/gallium/drivers/nouveau/nvc0/nvc0_vbo.c | 20
2 files changed, 39 insertions(+
Fixes regression caused by commit
2b1cdb0eddb73f62e4848d4b64840067f1f70865 in:
ES3-CTS.gtf.GL3Tests.shadow.shadow_execution_frag
No regressions observed in deqp, CTS or Piglit.
Signed-off-by: Tapani Pälli
Signed-off-by: Kevin Rogovin
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=911
On 09/15/2015 07:15 PM, Emil Velikov wrote:
Hi Tapani,
On 15 September 2015 at 08:13, Tapani Pälli wrote:
OpenGL ES 3.0 spec 3.7.2 "Transfer of Pixel Rectangles" specifies
DEPTH_COMPONENT, UNSIGNED_INT as a valid couple, validation for
internal format is checked by is_float_depth().
Fix reg
Signed-off-by: Ilia Mirkin
---
src/gallium/drivers/freedreno/a3xx/fd3_texture.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/src/gallium/drivers/freedreno/a3xx/fd3_texture.c
b/src/gallium/drivers/freedreno/a3xx/fd3_texture.c
index 3367f23..6ed5e0c 100644
--- a/src/gallium/drivers/freedr
The main issue is that the current logic looked into cso->u.tex, which
is the wrong side of the union to look into for texture buffers. While I
was at it, it was easy enough to add the logic to handle offsets
(first_element).
- reduce texture buffer size limit (determined experimentally)
- don't
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