From: Ville Syrjälä
Modern DXVK requires event support [1], but looks like it only
uses vkCmdSetEvent() + vkGetEventStatus(). So we can just
borrow the relevant code from gen8, leaving CmdWaitEvents still
unimplemented.
[1]
https://github.com/doitsujin/dxvk/commit/8c3900c533d83d12c970b905183d17
From: Ville Syrjälä
platform_x11 with dri3 needs inc_loader.
In file included from ../src/egl/drivers/dri2/platform_x11_dri3.c:35:0:
../src/egl/drivers/dri2/egl_dri2.h:41:32: fatal error: loader_dri3_helper.h: No
such file or directory
In file included from ../src/egl/drivers/dri2/platform_x11.
From: Ville Syrjälä
Build i915 with meson. More or less copied from i965, with all
the unneeded cruft removed, and the libdrm_intel dependency added.
Cc: Dylan Baker
Cc: Eric Anholt
Signed-off-by: Ville Syrjälä
---
meson.build | 7 +++
meson_options.txt
From: Ville Syrjälä
The pkg-config file is called xxf86vm.pc not xf86vm.pc.
Cc: Dylan Baker
Cc: Eric Anholt
Signed-off-by: Ville Syrjälä
---
meson.build | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/meson.build b/meson.build
index bff40f697d37..4ba00283cec7 100644
--- a
From: Ville Syrjälä
Pass the correct src coordinates to CopyTexSubImage()
when creating the temporary texture, and also take care to adjust
flipX/Y if the original src coordinates were flipped compared to
the new temporary texture src coordinates.
This fixes all the flip_src_x/y tests in
piglit.
From: Ville Syrjälä
gl_FragCoord contains the window coordinates so it seems to me that
we should not use perspective correct interpolation for it. At least
now I get similar output as i965/swrast/llvmpipe produce.
This fixes dEQP-GLES2.functional.shaders.builtin_variable.fragcoord_w.
dEQP-GLES2
From: Ville Syrjälä
Unlike the older gen2 hardware, gen3 performs perspective
correct interpolation even for the primary/secondary colors.
To do that it naturally needs us to emit W for the vertices.
Currently we emit W only when at least one texture coordinate
set gets emitted. This means the i
From: Ville Syrjälä
wpos_tex used to be a GLuint so assinging -1 to it and
later comparing with -1 worked correctly, but commit
c349031c27b7 ("i915: Fix texcoord vs. varying collision in
fragment programs") changed wpos_tex to uint8_t and hence
broke the comparison. To fix this define a more expl
From: Ville Syrjälä
Trying to build the Vulkan WSI code results in a failure without DRI3.
Make configure check that DRI3 is available before trying to build
the Vulkan drivers.
Signed-off-by: Ville Syrjälä
---
configure.ac | 4
1 file changed, 4 insertions(+)
diff --git a/configure.ac b
From: Ville Syrjälä
Set the include paths to consider in-tree headers before out-of-tree
headers.
Avoids the build failing due to stale headers being present in
$prefix. Previosuly 'make -ki install' or something similar was required
to update the out-of-tree headers to allow the build to succee
From: Ville Syrjälä
gcc-4 and earlier don't allow compound literals where a constant
is required in -std=c99/gnu99 mode, so we can't use ISL_SWIZZLE()
when populating the anv_formats[] array. There are a few ways around
it: First one would be -std=c89/gnu89, but the rest of the code
depends on c9
From: Ville Syrjälä
Looks like CHV MOCS behaves a bit differently than BDW MOCS. On BDW the
target cache bits can be used to enable L3 caching regardless if how the
other bits are set up to select the UC/WT/WB caching mode for LLC/eLLC.
On CHV however it appears that the other bits control the ca
From: Ville Syrjälä
The layout of the MOCS bits has kept changing for each new
platform. Instead of adding platform checks all over the
place just store the MOCS settings in the device info
and context.
Currently MOCS is only ever set up in two ways: either
let the PTE choose the LLC/eLLC cachin
From: Ville Syrjälä
All CHV devices will be branded as "Intel(r) HD Graphics".
Signed-off-by: Ville Syrjälä
---
include/pci_ids/i965_pci_ids.h | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/include/pci_ids/i965_pci_ids.h b/include/pci_ids/i965_pci_ids.h
index 3e3e8
From: Ville Syrjälä
The disassembly currently has the swizzle after the type for 3src source
operands, and the other way around for 2src. Flip the type and swizzle
around for 3src so that the output matches 2src.
Signed-off-by: Ville Syrjälä
---
src/mesa/drivers/dri/i965/brw_disasm.c | 6 +++--
From: Ville Syrjälä
Bring over the following fix from i965:
commit fb3d62fe3d4fc40ba4ad9804d8b6f451316c9ae2
Author: Kenneth Graunke
Date: Tue Aug 6 14:36:09 2013 -0700
i965: Remember to call intel_prepare_render() before blitting.
Fixes a crash in the following piglit tests:
bin/fbo-
From: Ville Syrjälä
The sub-pixel adjustment for points was killed off in
commit 60d762aa625095a8c1f9597d8530bb5a6fa61b4c
Author: Xiang, Haihao
Date: Wed Jan 2 11:38:51 2008 +0800
i915: Needn't adjust pixel centers. fix #12944
so we can just as well use COPY_DWORDS().
Signed-off-by:
From: Ville Syrjälä
The table used to map the GL primitive to the hw primitive never
changes so make it const.
Signed-off-by: Ville Syrjälä
---
src/mesa/drivers/dri/i915/intel_render.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i915/intel_render.c
From: Ville Syrjälä
Flip the cull bits when rendering to a user fbo on gen2. This
was already done on gen3 (since before git history starts)
but was missing from the gen2 code.
Fixes rendering of the driver+kart model in supertuxkart kart
selection screen.
Signed-off-by: Ville Syrjälä
---
src
From: Ville Syrjälä
The sub-pixel adjustment for points was killed off in
commit 60d762aa625095a8c1f9597d8530bb5a6fa61b4c
Author: Xiang, Haihao
Date: Wed Jan 2 11:38:51 2008 +0800
i915: Needn't adjust pixel centers. fix #12944
so if we don't need it in intel_tris.c we don't need it in
From: Ville Syrjälä
_tnl_RenderClippedPolygon and _tnl_RenderClippedLine already do most of
what we want so use them.
Signed-off-by: Ville Syrjälä
---
src/mesa/drivers/dri/i915/intel_tris.c | 19 ++-
1 file changed, 2 insertions(+), 17 deletions(-)
diff --git a/src/mesa/driver
From: Ville Syrjälä
i915 fragment programs utilize the texture coordinate registers
for both texture coordinates and varyings. Unfortunately the
code doesn't check if the same index might be in use for both.
It just naively uses the index to pick a texture unit, which
could lead to collisions.
A
From: Ville Syrjälä
Using c99 initializers for the primitive arrays makes things more
readable.
Signed-off-by: Ville Syrjälä
---
src/mesa/drivers/dri/i915/intel_render.c | 60
src/mesa/drivers/dri/i915/intel_tris.c | 40 ++---
2 files changed,
From: Ville Syrjälä
The hardware can draw lines 0.5 to 7.5 pixels wide. Adjust the limits
to 1.0-7.0. The old limits seems to be from the era when i915 and i965
were sharing this code.
Not really sure if 1.0-7.0 is correct. Maybe it could be 0.5.7.5 as
those are the hw limits, or maybe some comb
From: Ville Syrjälä
Bring the following commit over to i915:
commit ec542d74578bbef6b55125dd6aba1dc7f5079e65
Author: Eric Anholt
Date: Mon Mar 3 10:43:10 2014 -0800
i965: Drop broken front_buffer_reading/drawing optimization.
Not sure if it might fix anything, but since the i965 and i
From: Ville Syrjälä
t_vb_rendertmp.h reorder the vertices passed to the driver based on
the provoking vertex convention. The last vertex passed is always the
provoking vertex. For us however that's a bit bad since the hardware
itself handles the provoking vertex. Reorder the vertices back to the
From: Ville Syrjälä
These tables hold function pointers and they never change so
make them const.
Signed-off-by: Ville Syrjälä
---
src/mesa/tnl_dd/t_dd_dmatmp.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/mesa/tnl_dd/t_dd_dmatmp.h b/src/mesa/tnl_dd/t_dd_dmatmp.h
From: Ville Syrjälä
intelFastRenderClippedPoly() renders the polygon using triangles. For
polygons the provoking vertex is always the first one, and currently
this function assumes that the provoking vertex for triangles is the
last one. In case the user changed the provoking vertex convention,
t
From: Ville Syrjälä
Split the tri vs. tristrip paths in render_quad_strip_elts apart
and add the appropriate smooth vs. flat shading and provoking
vertex checks. Add the same checks to validate_render to make
sure we don't end up there under the wrong circumstances.
Signed-off-by: Ville Syrjälä
From: Ville Syrjälä
I830_UPLOAD_RASTER_RULES and I830_UPLOAD_TEX(0) are trying to occupy
the same bit. Move the texture bits upwards a bit to make room for
I830_UPLOAD_RASTER_RULES.
Now the driver will actually upload the raster rules which is rather
important to get the provoking vertex right.
From: Ville Syrjälä
No driver supports elts currently, and these make the validate_render
code a bit hard to follow. Just kill them.
Signed-off-by: Ville Syrjälä
---
src/mesa/tnl_dd/t_dd_dmatmp.h | 133 ++
1 file changed, 5 insertions(+), 128 deletions(-
From: Ville Syrjälä
I've had some of these i915 patches lying around for half a year or more,
so I figured it's time to post them.
This series fixes rendering problems in glxgears and supertuxkart. It
also fixes a few piglit tests (provoking vertex, and a few crashers).
No piglit regressions on
From: Ville Syrjälä
Calling render_tri_fan_verts() from render_poly_elts() doesn't seem sane.
I presume the intention was to call render_tri_fan_elts() instead.
Signed-off-by: Ville Syrjälä
---
src/mesa/tnl_dd/t_dd_dmatmp.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/sr
From: Ville Syrjälä
We can allow rendering flat shaded polygons using tri fans if we check
the provoking vertex convention.
Signed-off-by: Ville Syrjälä
---
src/mesa/tnl_dd/t_dd_dmatmp.h | 12 +---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/src/mesa/tnl_dd/t_dd_dmatm
From: Ville Syrjälä
When drawing quads using triangles we need to be careful to make
the provoking vertices match when flat shading.
Signed-off-by: Ville Syrjälä
---
src/mesa/tnl_dd/t_dd_dmatmp.h | 12 +---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/src/mesa/tnl_dd/t
From: Ville Syrjälä
When rendering quad strips via tri strips we can't get the provoking
vertex right, so disallow flat shading.
Signed-off-by: Ville Syrjälä
---
src/mesa/tnl_dd/t_dd_dmatmp.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/mesa/tnl_dd/t_dd_dmatmp.h
From: Ville Syrjälä
tnl/t_vertex_sse.c: In function ‘build_vertex_emit’:
tnl/t_vertex_sse.c:500:6: error: implicit declaration of function ‘printf’
[-Werror=implicit-function-declaration]
printf("Can't emit 1ub %x %x %d\n", a->vertoffset, a[-1].vertoffset,
a[-1].vertattrsize );
^
tn
From: Ville Syrjälä
Increase the device info .urb.size for CHV to match the default URB
size (192kB).
Signed-off-by: Ville Syrjälä
---
src/mesa/drivers/dri/i965/brw_device_info.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/brw_device_info.c
b/
From: Ville Syrjälä
Increase the device info .urb.size for BDW GT3 and CHV to match the
default URB size for each.
Also add all missing platforms (BYT,BDW,CHV) to the comment describing
the default URB size in gen7_urb.c.
Signed-off-by: Ville Syrjälä
---
src/mesa/drivers/dri/i965/brw_device_i
From: Ville Syrjälä
max_wm_threads depends on the GT SKU on gen8. Update the values to
match the spec.
The max number of threads in 3DSTATE_PS is always programmed to 64
and the hardware internally scales that depending on the GT SKU. So
this doesn't change the max number of threads actually use
From: Ville Syrjälä
According to BSpec the correct number for min_vs_entries is 34 for CHV.
Signed-off-by: Ville Syrjälä
---
src/mesa/drivers/dri/i965/brw_device_info.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/brw_device_info.c
b/src/mesa/d
From: Ville Syrjälä
i915 fragment programs utilize the texture coordinate registers
for both texture coordinates and varyings. Unfortunately the
code doesn't check if the same index might be in use for both.
It just naively uses the index to pick a texture unit, which
could lead to collisions.
A
From: Foo Bar
Using just one decimal place for dotclock and refresh rates loses quite
a bit of information. When dealing with 60Hz and 59.94Hz modes for
example it's useful to see at least two decimal places. Also for the
dotclock in the same cases three decimal places seems quite a bit better
th
From: Ville Syrjälä
Don't use the rounded vrefresh info to predict the frame duration.
Instead calculate if from the clock.
---
tests/kms_flip.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/tests/kms_flip.c b/tests/kms_flip.c
index 227a176..f609ac0 100644
--- a/tests/k
From: Foo Bar
Interlaced modes generally have an odd VTotal, so we lose half a line
from VTotal when we divide by two. That causes the final refresh rate
to be slightly off. Make VTotal a double to avoid the problem.
Signed-off-by: Foo Bar
---
xrandr.c | 2 +-
1 file changed, 1 insertion(+), 1
From: Ville Syrjälä
Gen2 doesn't support the A8 texture format. Currently the driver
substitutes it with I8, but that results in incorrect RGB values.
Use A8L8 instead. We end up wasting a bit of memory, but at least
we should get the correct results.
v2: Handle the fallback in _mesa_choose_tex_
From: Ville Syrjälä
The spec says using DOT4 for alpha is undefined unless DOT4 is also used
for color. It seems to do the right thing anyway, but better safe than sorry.
Also override numAlphaArgs to 2 for DOT4 since that's what it wants.
This migth fix something in case the specified alpha mod
From: Ville Syrjälä
gen2 doesn't supporte linear mip filter with anisotropic min/mag
filtering. The hardware would automagically downgrade the min/mag
filters to linear in such cases, which IMO looks worse than forcing
the mip filter to nearest.
Signed-off-by: Ville Syrjälä
---
src/mesa/driver
From: Ville Syrjälä
TEXTURE_SET() is the only register macro that forgets to wrap the
argument evaluation in parens. Only simple integers are passed to this
macro so there's no bug but sitll it seems prudent to add the
parens.
Signed-off-by: Ville Syrjälä
---
src/mesa/drivers/dri/i915/i830_reg
From: Ville Syrjälä
Gen2 doesn't have fragmnts shaders so we shouldn't be calling
_mesa_meta_glsl_Clear() on gen2. Restore the appropriate
ARB_fragment_shader check to the clear path which was lost in:
commit 94f22fbe787214580a1a13a774114d2650c166cb
Author: Tapani Pälli
Date: Wed Aug 8 20:
From: Ville Syrjälä
According to gen2 BSpec the pipeline must be flushed at least up to the
windower before changing the scissor rect enable field. Emitting the
3DSTATE_SCISSOR_RECTANGLE_0 before 3DSTATE_SCISSOR_ENABLE is sufficient
to do that.
gen3 BSpec no longer has that piece of text, but le
From: Ville Syrjälä
ctx.hw_stencil is not used anywhere so kill it.
Signed-off-by: Ville Syrjälä
---
src/mesa/drivers/dri/i915/intel_context.c | 1 -
src/mesa/drivers/dri/i915/intel_context.h | 1 -
2 files changed, 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i915/intel_context.c
b/src/
From: Ville Syrjälä
Gen2 doesn't support depth/stencil textures, and since
commit c1d4d4999303f9167b20f4e0674b9436e6295cf7
Author: Ville Syrjälä
Date: Thu Apr 24 14:11:43 2014 +0300
i915: Don't advertise Z formats in TextureFormatSupported on gen2
depth/stencil formats are no longer
From: Ville Syrjälä
Check that the target is GL_TEXTURE_CUBE_MAP before emitting
TEXCOORDTYPE_VECTOR texture coordinates.
I'm not sure if the hardware would like CARTESIAN coordinates
with cube maps, and as I'm too lazy to find out just emit the
VECTOR coordinates for cube maps always. For other
From: Ville Syrjälä
Gen2 doesn't support the A8 texture format. Currently the driver
substitutes it with I8, but that results in incorrect RGB values.
Use A8L8 instead. We end up wasting a bit of memory, but at least
we should get the correct results.
Bugzilla: https://bugs.freedesktop.org/show_
From: Ville Syrjälä
I had a few rainy days during my summer vacation so I decided to fix a
chromnium-bsu texturing problem that was nagging me for a while now. I
ended up fixing a few other things too that I spotted mostly from reading
the code.
The aniso vs. mip filter thing probably comes down
From: Ville Syrjälä
Fix an off by one in the texture unit walk during texblend
setup on gen2. This caused the last enabled texunit to be
skipped resulting in totally messed up texturing.
This is a regression introduced here:
commit 1ad443ecdd694dd9bf3c4a5050d749fb80db6fa2
Author: Eric Anholt
From: Ville Syrjälä
intel_alloc_renderbuffer_storage() will clobber rb->Format which was
already set up by intel_create_renderbuffer(). This causes the driver
to potentially create the depth buffer in the wrong format.
In practice this makes the depth buffer Z24 even if the visual has
depthBits=
From: Ville Syrjälä
intel_alloc_renderbuffer_storage() will clobber rb->Format which was
already set up by intel_create_renderbuffer(). This causes the driver
to potentially create the depth buffer in the wrong format.
Long time ago things worked by accident because
_mesa_choose_tex_format() che
From: Ville Syrjälä
Gen2 doesn't support texturing from Z formats, so state as much.
Signed-off-by: Ville Syrjälä
---
src/mesa/drivers/dri/i915/i915_context.c | 28 +++-
1 file changed, 15 insertions(+), 13 deletions(-)
diff --git a/src/mesa/drivers/dri/i915/i915_conte
From: Ville Syrjälä
I was a bit annoyed when chromium-bsu stopped rendering the spinning
title text on my gen2 machine. So I bisected it down and found the
problem with the renderbuffer code overwriting the selected depth
buffer format.
This series fixes that particular problem, and I included t
From: nick
Straightforward fix to properly load dest->color with color data, as
opposed to position data as previously implemented.
[vsyrjala: I noticed the patch languishing in bugzilla.
It looks correct to me so I refreshed it for master.
Looks like it's a regression introduced in:
commit
From: Ville Syrjälä
According to HSW Bspec L3$ evictions may land in LLC regardless of
LLC MOCS/PTE settings. That means we shouldn't set scanout buffers
as L3 cacheable when writing to them.
So far I've been unable to observe this phenomenon on my IVB, but
better safe than sorry. Especially sin
From: Ville Syrjälä
Juse spotted these unpopulated MOCS fields when comparing the code
against BSpec. No idea if this makes any difference anywhere, or if
it even makes any sense.
Signed-off-by: Ville Syrjälä
---
src/mesa/drivers/dri/i965/brw_misc_state.c | 4 +++-
src/mesa/drivers/dri/i965/ge
From: Ville Syrjälä
IVB/BYT also has the same L3 cacheability control in MOCS as HSW,
so let's make use of it.
pts/xonotic and pts/reaction @ 1920x1080 gain ~4% on my IVB GT2. Most
other things show less gains/no regressions, except furmark which
loses some 10 points.
I didn't have a BYT at han
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