https://bugs.freedesktop.org/show_bug.cgi?id=108841
--- Comment #4 from Timothy Arceri ---
I've created a merge request [1] that implements the spirv control masks.
[1] https://gitlab.freedesktop.org/mesa/mesa/merge_requests/490/
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From: Dave Airlie
I noticed we crashed piglit arb_texture_view-rendering-formats
when run on softpipe.
This fixes the clear tiles to use the surface format not the
underlying storage format.
This fixes a bunch of srgb piglits as well.
---
src/gallium/drivers/softpipe/sp_tile_cache.c | 11 +
https://bugs.freedesktop.org/show_bug.cgi?id=108841
--- Comment #3 from Timothy Arceri ---
(In reply to Alex Smith from comment #1)
> I'd also like to see these implemented. AMDVLK supports them and we've had
> several cases where we've been able to get significant performance
> improvements on c
https://bugs.freedesktop.org/show_bug.cgi?id=108841
--- Comment #2 from Timothy Arceri ---
I'll take a look at this it should hopefully not be too difficult.
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On Tue, Mar 19, 2019 at 9:28 AM Samuel Pitoiset
wrote:
>
> From: Rhys Perry
>
> Signed-off-by: Rhys Perry
> ---
> src/amd/common/ac_nir_to_llvm.c | 9 +++--
> 1 file changed, 7 insertions(+), 2 deletions(-)
>
> diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
>
r-b
On Tue, Mar 19, 2019 at 11:37 PM Samuel Pitoiset
wrote:
>
> Noticed with a Doom shader.
>
> 29077 shaders in 15096 tests
> Totals:
> SGPRS: 1282125 -> 1282133 (0.00 %)
> VGPRS: 908716 -> 908616 (-0.01 %)
> Spilled SGPRs: 24811 -> 24779 (-0.13 %)
> Code Size: 49048176 -> 48936488 (-0.23 %) byt
Noticed with a Doom shader.
29077 shaders in 15096 tests
Totals:
SGPRS: 1282125 -> 1282133 (0.00 %)
VGPRS: 908716 -> 908616 (-0.01 %)
Spilled SGPRs: 24811 -> 24779 (-0.13 %)
Code Size: 49048176 -> 48936488 (-0.23 %) bytes
Max Waves: 244232 -> 244226 (-0.00 %)
Totals from affected shaders:
SGPRS:
https://bugs.freedesktop.org/show_bug.cgi?id=109929
--- Comment #9 from Vinson Lee ---
(In reply to Timur Kristóf from comment #8)
> Can you tell me how to build libxatracker.la? Ie. what autotools command to
> use? Thanks!
./autogen.sh --enable-autotools --enable-opencl --with-dri-drivers=
--wi
https://bugs.freedesktop.org/show_bug.cgi?id=108620
Vladislav Kamenev changed:
What|Removed |Added
Resolution|--- |NOTOURBUG
Status|NEW
https://bugs.freedesktop.org/show_bug.cgi?id=109560
--- Comment #3 from Strangiato ---
dmesg shows no error.
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mesa-de
Reviewed-by: Bas Nieuwenhuizen
FYI since the new intrinsics don't merge voffset and soffset anymore,
you can remove the tbuffer variants for LLVM8+.
On Wed, Mar 13, 2019 at 5:38 PM Samuel Pitoiset
wrote:
>
> New buffer intrinsics have a separate soffset parameter.
>
> v3: - use ac_build_raw_tbu
On 3/19/19 8:24 PM, Bas Nieuwenhuizen wrote:
On Wed, Mar 13, 2019 at 5:38 PM Samuel Pitoiset
wrote:
Signed-off-by: Samuel Pitoiset
---
src/amd/common/ac_nir_to_llvm.c | 35 ++---
1 file changed, 6 insertions(+), 29 deletions(-)
diff --git a/src/amd/common/ac_ni
https://bugs.freedesktop.org/show_bug.cgi?id=109560
--- Comment #2 from jam...@amd.com ---
Can you add attachment of dmesg when issue occurred? Thanks! James
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There's a MR out to fix this:
https://gitlab.freedesktop.org/mesa/mesa/merge_requests/478/diffs
On Tue, Mar 19, 2019 at 5:32 AM Samuel Pitoiset
wrote:
> This commit breaks some CTS with RADV (eg.
> dEQP-VK.ssbo.phys.layout.single_basic_type.std430.bvec2) and it
> introduces one compiler warning
https://bugs.freedesktop.org/show_bug.cgi?id=109560
Strangiato changed:
What|Removed |Added
Version|18.3|19.0
--- Comment #1 from Strangiato ---
T
https://bugs.freedesktop.org/show_bug.cgi?id=110141
Parker Reed changed:
What|Removed |Added
CC||parker.l.r...@gmail.com
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On Wed, Mar 13, 2019 at 5:38 PM Samuel Pitoiset
wrote:
>
> Signed-off-by: Samuel Pitoiset
> ---
> src/amd/common/ac_nir_to_llvm.c | 35 ++---
> 1 file changed, 6 insertions(+), 29 deletions(-)
>
> diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to
---
src/compiler/nir/nir.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/src/compiler/nir/nir.h b/src/compiler/nir/nir.h
index 67304af1d64..e4f012809e5 100644
--- a/src/compiler/nir/nir.h
+++ b/src/compiler/nir/nir.h
@@ -59,6 +59,7 @@ extern "C" {
#define NIR_FALSE 0u
#de
https://bugs.freedesktop.org/show_bug.cgi?id=109393
--- Comment #18 from Samuel Pitoiset ---
Thanks for confirming. Feel free to re-open if needed, hopefully not. :)
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https://bugs.freedesktop.org/show_bug.cgi?id=110116
--- Comment #9 from QwertyChouskie ---
Created attachment 143734
--> https://bugs.freedesktop.org/attachment.cgi?id=143734&action=edit
apitrace from self-compiled Neverball 1.6.0
I seem to be unable to reproduce the issue using Neverball mast
Reviewed-by: Lionel Landwerlin
On 19/03/2019 17:08, Jason Ekstrand wrote:
We initially set this lower because we didn't have SIMD32 support yet
but we've supported SIMD32 for quite some time now. We should bump it
up to the real limit.
---
src/intel/vulkan/anv_device.c | 2 +-
1 file change
We initially set this lower because we didn't have SIMD32 support yet
but we've supported SIMD32 for quite some time now. We should bump it
up to the real limit.
---
src/intel/vulkan/anv_device.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/intel/vulkan/anv_device.c b/s
https://bugs.freedesktop.org/show_bug.cgi?id=109393
Jaap Buurman changed:
What|Removed |Added
Resolution|--- |FIXED
Status|NEW
On Sat, 2019-02-16 at 10:25 +1100, Timothy Arceri wrote:
> If the updated piglit tests pass on the Nvidia blob as per my reply to
> those patches and this patch passes on the new and old piglit tests.
> Then this patch is:
As commented in the piglit thread, the nVIDIA blob has many other
problem
After having a deeper look at the cache flushes when initializing DCC,
it seems like we are dumb.
In case the compute path is used for clearing DCC, we set the following
flags:
- CS_PARTIAL_FLUSH
- INV_VMEM_L1
- WRITEBACK_GLOBAL_L2
- FLUSH_AND_INV_CB
- FLUSH_ANV_INV_CB_META
On GFX9, the
On 3/19/19 1:56 PM, Bas Nieuwenhuizen wrote:
That it does not use it is exactly why we need to make sure the CB
data is not in the CB cache by flushing it?
Why only for DCC?
On Tue, Mar 19, 2019 at 12:15 PM Samuel Pitoiset
wrote:
The clear operation (ie. compute) doesn't use the CB caches.
That it does not use it is exactly why we need to make sure the CB
data is not in the CB cache by flushing it?
On Tue, Mar 19, 2019 at 12:15 PM Samuel Pitoiset
wrote:
>
> The clear operation (ie. compute) doesn't use the CB caches.
>
> Signed-off-by: Samuel Pitoiset
> ---
> src/amd/vulkan/radv_
On Mon, 2019-03-18 at 14:44 -0700, Lepton Wu wrote:
> virgl render complains about "Illegal resource" when running
> dEQP-EGL.functional.color_clears.single_context.gles2.rgb888_window,
> the reason is that a zero bind value was given for temp resource.
>
> Signed-off-by: Lepton Wu
> ---
> src/g
The clear operation (ie. compute) doesn't use the CB caches.
Signed-off-by: Samuel Pitoiset
---
src/amd/vulkan/radv_cmd_buffer.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index 5bb3b51684e..b6035dfbbc
If an image has CMASK/FMASK or FMASK/DCC it shouldn't be needed
to sync between the two clears because they don't initialize
the same memory range.
Signed-off-by: Samuel Pitoiset
---
src/amd/vulkan/radv_cmd_buffer.c | 31 +--
1 file changed, 13 insertions(+), 18 delet
Unnecessary to have a separate function for CMASK, and calling
the radv_clear_XXX() helpers will allow us to remove some
cache flushes.
Signed-off-by: Samuel Pitoiset
---
src/amd/vulkan/radv_cmd_buffer.c | 48
src/amd/vulkan/radv_private.h| 18
2
This commit breaks some CTS with RADV (eg.
dEQP-VK.ssbo.phys.layout.single_basic_type.std430.bvec2) and it
introduces one compiler warning (minor stuff).
Is the Rb tag missing too?
Thanks!
On 3/19/19 5:57 AM, GitLab Mirror wrote:
Module: Mesa
Branch: master
Commit: c95afe56a8033a87dca71cc931
This patch requires the typed vertex fetches series.
Totals from affected shaders:
SGPRS: 445574 -> 452638 (1.59 %)
VGPRS: 373392 -> 370436 (-0.79 %)
Spilled SGPRs: 77 -> 14 (-81.82 %)
Spilled VGPRs: 0 -> 0 (0.00 %)
Code Size: 14162288 -> 14413036 (1.77 %) bytes
Max Waves: 11 -> 120509 (0.43 %
From: Rhys Perry
Signed-off-by: Rhys Perry
---
src/amd/common/ac_nir_to_llvm.c | 65 -
1 file changed, 55 insertions(+), 10 deletions(-)
diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index 7a03e9c15b2..34c4e2a69fa 100644
--- a/sr
From: Rhys Perry
v2: remove 16-bit additions and rebase
Signed-off-by: Rhys Perry
---
src/amd/common/ac_nir_to_llvm.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index f3e8f89ba9b..c7212ff3293 100644
--- a/src/amd/com
From: Rhys Perry
Signed-off-by: Rhys Perry
---
src/amd/common/ac_nir_to_llvm.c | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index 34c4e2a69fa..f3e8f89ba9b 100644
--- a/src/amd/common/ac_nir_to_llvm
From: Rhys Perry
Signed-off-by: Rhys Perry
---
docs/features.txt | 2 +-
src/amd/vulkan/radv_device.c | 9 +
src/amd/vulkan/radv_extensions.py | 1 +
src/amd/vulkan/radv_shader.c | 1 +
4 files changed, 12 insertions(+), 1 deletion(-)
diff --git a/docs/feature
From: Rhys Perry
Signed-off-by: Rhys Perry
---
src/amd/common/ac_nir_to_llvm.c | 4
1 file changed, 4 insertions(+)
diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index c7212ff3293..f0b0c24ec08 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/comm
Signed-off-by: Samuel Pitoiset
---
src/amd/common/ac_llvm_build.c | 19 +++
src/amd/common/ac_llvm_build.h | 9 +
2 files changed, 28 insertions(+)
diff --git a/src/amd/common/ac_llvm_build.c b/src/amd/common/ac_llvm_build.c
index d52f1b3f42d..f6078634336 100644
--- a/sr
Signed-off-by: Samuel Pitoiset
---
src/amd/common/ac_llvm_build.c | 18 ++
src/amd/common/ac_llvm_build.h | 8
2 files changed, 26 insertions(+)
diff --git a/src/amd/common/ac_llvm_build.c b/src/amd/common/ac_llvm_build.c
index c5f1c85f269..d52f1b3f42d 100644
--- a/src/
Hi,
This series implements VK_KHR_8bit_storage for RADV. Original work
is from Rhys Perry, I did rebase, update some patches and test.
Please review,
thanks!
Rhys Perry (5):
ac/nir: implement 8-bit push constant, ssbo and ubo loads
ac/nir: implement 8-bit ssbo stores
ac/nir: add 8-bit type
Original patch by Rhys Perry.
Signed-off-by: Samuel Pitoiset
---
src/amd/common/ac_llvm_build.c | 10 --
src/amd/common/ac_llvm_build.h | 2 ++
2 files changed, 10 insertions(+), 2 deletions(-)
diff --git a/src/amd/common/ac_llvm_build.c b/src/amd/common/ac_llvm_build.c
index 541ad75c8
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