If an image has CMASK/FMASK or FMASK/DCC it shouldn't be needed
to sync between the two clears because they don't initialize
the same memory range.
Signed-off-by: Samuel Pitoiset <samuel.pitoi...@gmail.com>
---
src/amd/vulkan/radv_cmd_buffer.c | 31 +++++++++++++------------------
1 file changed, 13 insertions(+), 18 deletions(-)
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index b6035dfbbc5..e9df9da70bb 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -4540,6 +4540,14 @@ static void radv_init_color_image_metadata(struct
radv_cmd_buffer *cmd_buffer,
unsigned dst_queue_mask)
{
struct radv_cmd_state *state = &cmd_buffer->state;
+ enum radv_cmd_flush_bits post_flush = 0;
+
+ if (!radv_image_has_CB_metadata(image))
+ return;
+
+ /* XXX: Figure out if this is really needed! */
+ state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
+ RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
if (radv_image_has_cmask(image)) {
uint32_t value = 0xffffffffu; /* Fully expanded mode. */
@@ -4549,23 +4557,13 @@ static void radv_init_color_image_metadata(struct
radv_cmd_buffer *cmd_buffer,
value = 0xccccccccu;
}
- state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
- RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
-
- state->flush_bits |= radv_clear_cmask(cmd_buffer, image, value);
-
- state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
+ post_flush |= radv_clear_cmask(cmd_buffer, image, value);
}
if (radv_image_has_fmask(image)) {
uint32_t value = radv_image_get_fmask_init_value(image);
- state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
- RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
-
- state->flush_bits |= radv_clear_fmask(cmd_buffer, image, value);
-
- state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
+ post_flush |= radv_clear_fmask(cmd_buffer, image, value);
}
if (radv_image_has_dcc(image)) {
@@ -4578,12 +4576,7 @@ static void radv_init_color_image_metadata(struct
radv_cmd_buffer *cmd_buffer,
need_decompress_pass = true;
}
- state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
- RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
-
- state->flush_bits |= radv_clear_dcc(cmd_buffer, image, value);
-
- state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
+ post_flush |= radv_clear_dcc(cmd_buffer, image, value);
radv_update_fce_metadata(cmd_buffer, image,
need_decompress_pass);
@@ -4593,6 +4586,8 @@ static void radv_init_color_image_metadata(struct
radv_cmd_buffer *cmd_buffer,
uint32_t color_values[2] = {};
radv_set_color_clear_metadata(cmd_buffer, image, color_values);
}
+
+ state->flush_bits |= post_flush | RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
}
/**
--
2.21.0
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