Unnecessary to have a separate function for CMASK, and calling
the radv_clear_XXX() helpers will allow us to remove some
cache flushes.
Signed-off-by: Samuel Pitoiset <samuel.pitoi...@gmail.com>
---
src/amd/vulkan/radv_cmd_buffer.c | 48 ++++++++++++++++----------------
src/amd/vulkan/radv_private.h | 18 ++++++++++++
2 files changed, 42 insertions(+), 24 deletions(-)
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index ae8f50d0348..5bb3b51684e 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -4501,31 +4501,11 @@ static void radv_handle_depth_image_transition(struct
radv_cmd_buffer *cmd_buffe
}
}
-static void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
- struct radv_image *image, uint32_t value)
-{
- struct radv_cmd_state *state = &cmd_buffer->state;
-
- state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
- RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
-
- state->flush_bits |= radv_clear_cmask(cmd_buffer, image, value);
-
- state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
-}
-
void radv_initialize_fmask(struct radv_cmd_buffer *cmd_buffer,
struct radv_image *image)
{
struct radv_cmd_state *state = &cmd_buffer->state;
- static const uint32_t fmask_clear_values[4] = {
- 0x00000000,
- 0x02020202,
- 0xE4E4E4E4,
- 0x76543210
- };
- uint32_t log2_samples = util_logbase2(image->info.samples);
- uint32_t value = fmask_clear_values[log2_samples];
+ uint32_t value = radv_image_get_fmask_init_value(image);
state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
@@ -4559,6 +4539,8 @@ static void radv_init_color_image_metadata(struct
radv_cmd_buffer *cmd_buffer,
unsigned src_queue_mask,
unsigned dst_queue_mask)
{
+ struct radv_cmd_state *state = &cmd_buffer->state;
+
if (radv_image_has_cmask(image)) {
uint32_t value = 0xffffffffu; /* Fully expanded mode. */
@@ -4567,11 +4549,23 @@ static void radv_init_color_image_metadata(struct
radv_cmd_buffer *cmd_buffer,
value = 0xccccccccu;
}
- radv_initialise_cmask(cmd_buffer, image, value);
+ state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
+ RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
+
+ state->flush_bits |= radv_clear_cmask(cmd_buffer, image, value);
+
+ state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
}
if (radv_image_has_fmask(image)) {
- radv_initialize_fmask(cmd_buffer, image);
+ uint32_t value = radv_image_get_fmask_init_value(image);
+
+ state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
+ RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
+
+ state->flush_bits |= radv_clear_fmask(cmd_buffer, image, value);
+
+ state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
}
if (radv_image_has_dcc(image)) {
@@ -4584,7 +4578,13 @@ static void radv_init_color_image_metadata(struct
radv_cmd_buffer *cmd_buffer,
need_decompress_pass = true;
}
- radv_initialize_dcc(cmd_buffer, image, value);
+ state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
+ RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
+
+ state->flush_bits |= radv_clear_dcc(cmd_buffer, image, value);
+
+ state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
+ RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
radv_update_fce_metadata(cmd_buffer, image,
need_decompress_pass);
diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
index 39fa6110fde..064fe3b02a4 100644
--- a/src/amd/vulkan/radv_private.h
+++ b/src/amd/vulkan/radv_private.h
@@ -1603,6 +1603,24 @@ radv_image_has_CB_metadata(const struct radv_image
*image)
radv_image_has_dcc(image);
}
+/**
+ * Return the initial FMASK value.
+ */
+static inline uint32_t
+radv_image_get_fmask_init_value(const struct radv_image *image)
+{
+ static const uint32_t fmask_clear_values[4] = {
+ 0x00000000,
+ 0x02020202,
+ 0xE4E4E4E4,
+ 0x76543210
+ };
+ uint32_t log2_samples = util_logbase2(image->info.samples);
+ uint32_t value = fmask_clear_values[log2_samples];
+
+ return value;
+}
+
/**
* Return whether the image has HTILE metadata for depth surfaces.
*/
--
2.21.0
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