Yes, I agree, thanks for bringing it up.
Iago
On Tue, 2018-02-20 at 16:38 +0200, Andres Gomez wrote:
> Iago, this looks like a good candidate to nominate for inclusion in
> the
> 17.3 stable queue.
>
> What do you think?
>
> On Wed, 2017-11-29 at 11:49 +0100, Iago Toral Quiroga wrote:
> > 64-bi
As many of you know, I've been writing a Vulkan extension for DRM format
modifiers, named VK_EXT_image_drm_format_modifier.
The extension is very close to completion. I've submitted a branch to
Khronos for review. It's receiving active review inside Khronos from
some non-Mesa closed-source window-
Hi Nanley,
thanks for having a look at this, you're right that we should use the
framebuffer dimensions to decide on the number of layers to resolve.
I'll send a new version with the fix.
Iago
On Tue, 2018-02-20 at 15:18 -0800, Nanley Chery wrote:
> On Thu, Feb 15, 2018 at 09:40:16AM +0100, Ia
On Thu 21 Dec 2017, Daniel Vetter wrote:
> On Thu, Dec 21, 2017 at 12:22 AM, Kristian Kristensen
> wrote:
>> On Wed, Dec 20, 2017 at 12:41 PM, Miguel Angel Vico
>> wrote:
>>> On Wed, 20 Dec 2017 11:54:10 -0800 Kristian Høgsberg
>>> wrote:
I'd like to see concrete examples of actual displ
That makes sense. I guess whoever changed that aspect didn't remove the
assert. I only noticed it because I build with -Wextra, so it's not
surprising that nobody else noticed.
Reviewed-by: Ian Romanick
On 02/20/2018 07:42 PM, Timothy Arceri wrote:
> This was originally intended to make sure t
v2: Use assume() at the srcs[] definition instead.
Cc: Jason Ekstrand
Cc: Ian Romanick
Cc: Eric Engestrom
---
src/compiler/spirv/spirv_to_nir.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/compiler/spirv/spirv_to_nir.c
b/src/compiler/spirv/spirv_to_nir.c
index c6df764682ec..e22fe25
Fixes assert in glsl-1.50-gs-max-output-components piglit test.
Note that the double handling will only work for doubles that
don't take up multiple slots i.e. double and dvec2. However
dual slot double handling is an existing bug which is made no
worse by this patch.
---
src/gallium/drivers/rade
We need to mark the range as valid, and validate the resource using a
helper to ensure that the buffer status is marked properly.
Fixes some CTS pipeline stats query tests.
Signed-off-by: Ilia Mirkin
---
src/gallium/drivers/nouveau/nvc0/nvc0_query_hw.c | 8
1 file changed, 4 insertions
Align16 is no more.
---
src/intel/compiler/test_eu_validate.cpp | 16
1 file changed, 16 insertions(+)
diff --git a/src/intel/compiler/test_eu_validate.cpp
b/src/intel/compiler/test_eu_validate.cpp
index cb2fcd3d40f..f6c2b35625e 100644
--- a/src/intel/compiler/test_eu_validate.c
With the Align16 tests now disabled, we can run the rest of the tests in
ICL mode (and see them pass!)
---
src/intel/compiler/test_eu_validate.cpp | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/intel/compiler/test_eu_validate.cpp
b/src/intel/compiler/test_eu_validate.cpp
index f6c2b35625
---
src/intel/compiler/brw_fs_generator.cpp | 17 +
1 file changed, 13 insertions(+), 4 deletions(-)
diff --git a/src/intel/compiler/brw_fs_generator.cpp
b/src/intel/compiler/brw_fs_generator.cpp
index 0854709b272..f2bdac7d731 100644
--- a/src/intel/compiler/brw_fs_generator.cpp
The LRP instruction is no more.
---
src/intel/compiler/brw_compiler.c | 35 +
src/intel/compiler/brw_fs_builder.h | 2 +-
src/intel/compiler/brw_fs_generator.cpp | 2 +-
src/intel/compiler/brw_vec4_builder.h | 2 +-
src/intel/compiler/brw_vec4_visitor
Align16 is no more. We previously generated an align16 ADD instruction
to calculate DDY:
add(8) g11<1>F -g10<4>.xyxyF g10<4>.zwzwF { align16 1Q };
Without align16, we now implement it as two align1 instructions:
add(4) g11<2>F -g10<4,2,0>Fg10.2<4,2,0>F { align1 1N };
add(4) g1
If multiple instructions are emitted, special handling of things like
conditional mod, saturate, and NoDDClr/NoDDChk need to be performed.
I noticed that conditional mods were misapplied when adding support for
Gen11 (in the previous patch). The next patch fixes the same bug in the
Gen4 LINE/MAC c
The brw_reg() constructor just obfuscates things here, in my opinion.
---
src/intel/compiler/brw_fs_generator.cpp | 77 +++--
1 file changed, 35 insertions(+), 42 deletions(-)
diff --git a/src/intel/compiler/brw_fs_generator.cpp
b/src/intel/compiler/brw_fs_generator.c
---
src/intel/compiler/brw_eu.c | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/src/intel/compiler/brw_eu.c b/src/intel/compiler/brw_eu.c
index bc297a21b32..3646076a8e8 100644
--- a/src/intel/compiler/brw_eu.c
+++ b/src/intel/compiler/brw_eu.c
@@ -384,7 +384,8 @@ enu
In a future patch, generate_ddy will want to inspect inst->exec_size.
Change generate_ddx as well for consistency.
---
src/intel/compiler/brw_fs.h | 6 --
src/intel/compiler/brw_fs_generator.cpp | 12 ++--
2 files changed, 10 insertions(+), 8 deletions(-)
diff --git a/src
Like CHV et al., Gen11 does not support 32x32 -> 32/64-bit integer
multiplies.
---
src/intel/common/gen_device_info.c | 4
src/intel/common/gen_device_info.h | 1 +
src/intel/compiler/brw_fs.cpp | 6 +-
3 files changed, 6 insertions(+), 5 deletions(-)
diff --git a/src/intel/common/g
Gen11 only differs from SKL+ in that it uses a new datatype index table.
---
src/intel/compiler/brw_eu_compact.c | 42 +
1 file changed, 42 insertions(+)
diff --git a/src/intel/compiler/brw_eu_compact.c
b/src/intel/compiler/brw_eu_compact.c
index 8d33e2adffc..
The PLN instruction is no more. Its functionality is now implemented
using two MAD instructions with the new native-float type. Instead of
pln(16) r20.0<1>:F r10.4<0;1,0>:F r4.0<8;8,1>:F
we now have
mad(8) acc0<1>:NF r10.7<0;1,0>:F r4.0<8;8,1>:F r10.4<0;1,0>:F
mad(8) r20.0<1>:F acc0<8;8
[PATCH 01/17] intel: Add a preliminary device for Ice Lake
[PATCH 02/17] intel: Add icl pci id for INTEL_DEVID_OVERRIDE
[PATCH 03/17] intel: Disable 64-bit extensions on platforms without
[PATCH 04/17] intel/compiler: Add Gen11 register types
[PATCH 05/17] intel/compiler: Add Gen11+ native float ty
This new type exposes the additional precision offered by the
accumulator register and will be used in the next patch to implement the
functionality of the PLN instruction using a pair of MAD instructions.
One weird thing to note: align1 ternary instructions may only have an
accumulator in the dst
Gen11 does not support DF, Q, UQ types in hardware. As a result, we have
to disable some GL extensions until they can be reimplemented.
---
src/intel/common/gen_device_info.c | 3 +++
src/intel/common/gen_device_info.h | 1 +
src/mesa/drivers/dri/i965/intel_extensions.c | 9 +++
From: Anuj Phogat
Reviewed-by: Matt Turner
Signed-off-by: Anuj Phogat
---
src/mesa/drivers/dri/i965/intel_screen.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/mesa/drivers/dri/i965/intel_screen.c
b/src/mesa/drivers/dri/i965/intel_screen.c
index ef5aee894fa..0367feb47c2 100644
---
From: Anuj Phogat
Signed-off-by: Anuj Phogat
---
include/pci_ids/i965_pci_ids.h | 9 ++
src/intel/common/gen_device_info.c | 56 +-
2 files changed, 64 insertions(+), 1 deletion(-)
diff --git a/include/pci_ids/i965_pci_ids.h b/include/pci_ids/i965_p
The hardware register types' encodings have changed on Gen11. Good thing
we have that superfluous looking brw_reg_type abstraction lying around!
---
src/intel/compiler/brw_reg_type.c | 73 ++-
1 file changed, 65 insertions(+), 8 deletions(-)
diff --git a/src/in
On 18-02-20 09:15:01, Antognolli, Rafael wrote:
On Tue, Feb 20, 2018 at 08:11:14AM -0800, Rafael Antognolli wrote:
On Fri, Feb 16, 2018 at 06:37:55PM -0800, Ben Widawsky wrote:
> On 18-02-16 13:44:00, Antognolli, Rafael wrote:
> > "This field controls the granularity of the replay mechanism when
Two things were off:
- valid range was not updated, which could affect waiting for future
maps
- fencing was done manually instead of using the *_resource_validate
helper, which resulted in a missed dirty buffer flag being set
Fixes: KHR-GL45.direct_state_access.buffers_clear
Signed-off-by
On Wed, Feb 21, 2018 at 4:03 AM, Rob Herring wrote:
> On Tue, Feb 20, 2018 at 4:26 AM, Tomasz Figa wrote:
>> On Tue, Feb 20, 2018 at 6:51 PM, Robert Foss
>> wrote:
>>> Hey Tomasz,
>>>
>>> On 02/20/2018 09:55 AM, Tomasz Figa wrote:
Hi Rob,
On Fri, Feb 16, 2018 at 11:48 PM, To
Reviewed-by: Timothy Arceri
On 21/02/18 08:02, Karol Herbst wrote:
this is required for Nouveau
Signed-off-by: Karol Herbst
---
src/mesa/state_tracker/st_glsl_to_nir.cpp | 6 ++
1 file changed, 6 insertions(+)
diff --git a/src/mesa/state_tracker/st_glsl_to_nir.cpp
b/src/mesa/state_tr
On 21/02/18 07:29, Samuel Pitoiset wrote:
On VI, 3D images are considered as 2D arrays. RadeonSI sets DA for
loads/stores/atomics and RADV only for loads/stores, so I guess there is
a reason for that?
I've changed the nir->llvm code recently in order to fix some piglit
test on the radeonsi n
On 21/02/18 13:21, Ilia Mirkin wrote:
Is this worth doing for st/mesa as well? Some quick grepping suggests
it's enabled on the 18.0 branch there too, but it's behind a
conditional which perhaps is never set.
Yes the st will need a change too as it will be enable for any driver
that enables th
This was originally intended to make sure the remap location
was not -1. However the code has changed alot since then,
the location is now never set to -1 and we also handle
components meaning this old assert has been doing comparisions
with the pointer to the array of component data.
Bugzilla: ht
On Wed, Feb 21, 2018 at 2:21 AM, Timothy Arceri wrote:
>
>
> On 21/02/18 12:10, Marek Olšák wrote:
>>
>> On Wed, Feb 21, 2018 at 12:50 AM, Timothy Arceri
>> wrote:
>>>
>>> On 21/02/18 10:33, Marek Olšák wrote:
On Tue, Feb 20, 2018 at 11:51 PM, Timothy Arceri
wrote:
>
On Tue, Feb 20, 2018 at 5:49 PM, Dave Airlie wrote:
> From: Dave Airlie
>
> Since v2 might take a while to rollout, we should reduce
> these inside some gathered minimums and then v2 can increase
> them using host values.
>
> Signed-off-by: Dave Airlie
Reviewed-by: Stéphane Marchesin
> ---
>
On Tue, Feb 20, 2018 at 5:49 PM, Dave Airlie wrote:
> From: Dave Airlie
>
> This checks the kernel api is new enough and asks for the
> larger caps size since the kernel won't mess it up now.
>
> Signed-off-by: Dave Airlie
Reviewed-by: Stéphane Marchesin
> ---
> src/gallium/drivers/virgl/vir
Is this worth doing for st/mesa as well? Some quick grepping suggests
it's enabled on the 18.0 branch there too, but it's behind a
conditional which perhaps is never set.
On Tue, Feb 20, 2018 at 9:12 PM, Jordan Justen
wrote:
> The QT framework has a bug in their shader program cache, which is
> b
https://bugs.freedesktop.org/show_bug.cgi?id=105183
Ian Romanick changed:
What|Removed |Added
CC||t_arc...@yahoo.com.au
--
You are receiv
https://bugs.freedesktop.org/show_bug.cgi?id=105183
Bug ID: 105183
Summary: Weird assertion in NIR linker
Product: Mesa
Version: git
Hardware: Other
OS: All
Status: NEW
Severity: normal
Priority:
The QT framework has a bug in their shader program cache, which is
built on GL_ARB_get_program_binary.
In an effort to allow them to fix the bug we don't enable more than 1
binary format for compatibility profiles.
This is only being done on the 18.0 release branch.
Ref: https://bugreports.qt.io
From: Dave Airlie
Since v2 might take a while to rollout, we should reduce
these inside some gathered minimums and then v2 can increase
them using host values.
Signed-off-by: Dave Airlie
---
src/gallium/drivers/virgl/virgl_winsys.h | 16
1 file changed, 8 insertions(+), 8 dele
From: Dave Airlie
This checks the kernel api is new enough and asks for the
larger caps size since the kernel won't mess it up now.
Signed-off-by: Dave Airlie
---
src/gallium/drivers/virgl/virgl_winsys.h | 25 ++-
src/gallium/winsys/virgl/drm/virgl_drm_winsys.c| 52 ++
From: Dave Airlie
This moves the lds_size calcs into the shader so we have all
the size stuff in one file.
Signed-off-by: Dave Airlie
---
src/amd/common/ac_nir_to_llvm.c | 33 +
src/amd/common/ac_nir_to_llvm.h | 1 +
src/amd/vulkan/radv_pipeline.c | 30 ---
From: Dave Airlie
Move all calculations to shader generation.
Signed-off-by: Dave Airlie
---
src/amd/common/ac_nir_to_llvm.c | 39 +++
src/amd/vulkan/radv_pipeline.c | 11 +++
2 files changed, 30 insertions(+), 20 deletions(-)
diff --git a/src/amd/
From: Dave Airlie
This drops the now unneeded scanning and results in favour
of the ones in the info.
Signed-off-by: Dave Airlie
---
src/amd/common/ac_nir_to_llvm.c | 28
src/amd/common/ac_nir_to_llvm.h | 4
src/amd/vulkan/radv_pipeline.c | 7 +++
3 fil
From: Dave Airlie
This removes the last TES-specifc user sgpr.
Signed-off-by: Dave Airlie
---
src/amd/common/ac_nir_to_llvm.c | 51 +
src/amd/common/ac_nir_to_llvm.h | 4 ++--
src/amd/vulkan/radv_pipeline.c | 18 ++-
3 files changed, 20 ins
From: Dave Airlie
This removes the other geometry specific user sgpr.
Signed-off-by: Dave Airlie
---
src/amd/common/ac_nir_to_llvm.c | 37 +++--
src/amd/common/ac_nir_to_llvm.h | 1 -
src/amd/vulkan/radv_pipeline.c | 9 -
3 files changed, 19 insertion
From: Dave Airlie
This drops one of the geometry specific user sgprs,
we can work this out at compile time.
Signed-off-by: Dave Airlie
---
src/amd/common/ac_nir_to_llvm.c | 15 +++
src/amd/vulkan/radv_pipeline.c | 9 +
2 files changed, 8 insertions(+), 16 deletions(-)
di
From: Dave Airlie
TES needs num_patches to do some of the calculations.
Signed-off-by: Dave Airlie
---
src/amd/common/ac_nir_to_llvm.c | 4 +++-
src/amd/common/ac_nir_to_llvm.h | 3 ++-
src/amd/vulkan/radv_pipeline.c | 4
3 files changed, 9 insertions(+), 2 deletions(-)
diff --git a/src
From: Dave Airlie
Move all calculations to shader generation.
Signed-off-by: Dave Airlie
---
src/amd/common/ac_nir_to_llvm.c | 22 +-
src/amd/vulkan/radv_pipeline.c | 8 ++--
2 files changed, 15 insertions(+), 15 deletions(-)
diff --git a/src/amd/common/ac_nir_to_llv
From: Dave Airlie
This removes the last TCS specific user sgpr.
Signed-off-by: Dave Airlie
---
src/amd/common/ac_nir_to_llvm.c | 118 ++--
src/amd/common/ac_nir_to_llvm.h | 2 +-
src/amd/vulkan/radv_pipeline.c | 9 ---
src/amd/vulkan/radv_shader.c|
From: Dave Airlie
Instead of recalculating the value, use the shader calculated value.
Signed-off-by: Dave Airlie
---
src/amd/vulkan/radv_pipeline.c | 30 ++
1 file changed, 2 insertions(+), 28 deletions(-)
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulk
From: Dave Airlie
This gathers the ls outputs written by the vertex shader,
and the tcs outputs, these are needed to calculate certain
tcs parameters.
These have to be separate for combined gfx9 shaders.
Signed-off-by: Dave Airlie
---
src/amd/common/ac_shader_info.c | 48 +
It seems to be season for reducing sgpr usage, but I was looking
at the tess/gs sgprs on radv when I realised nothing in them wasn't
static from the pipeline at compile time, so there is no need to
go passing to the shader via the user sgprs.
This series removes all the tess/gs specific users sgpr
From: Dave Airlie
This just moves this function to an inline so the shader_info
pass can use it.
Signed-off-by: Dave Airlie
---
src/amd/common/ac_nir_to_llvm.c | 22 --
src/amd/common/ac_shader_info.h | 25 +
2 files changed, 25 insertions(+), 22 del
From: Dave Airlie
Inline all calcs at shader creation.
Signed-off-by: Dave Airlie
---
src/amd/common/ac_nir_to_llvm.c | 27 ++-
src/amd/common/ac_nir_to_llvm.h | 1 +
src/amd/vulkan/radv_pipeline.c | 12 ++--
3 files changed, 25 insertions(+), 15 deletions(-)
From: Dave Airlie
We can precalculate input_vertex_size at compile time.
Signed-off-by: Dave Airlie
---
src/amd/common/ac_nir_to_llvm.c | 30 --
src/amd/common/ac_nir_to_llvm.h | 1 -
src/amd/vulkan/radv_pipeline.c | 10 --
3 files changed, 4 insertions(+)
Delaying unrolling and allowing NIR to do it instead has been shown
to result in better code in drivers such as i965. shader-db results
appear to should the same is true for radeonsi.
The other advantage is that using NIR unrolling improves compile
times significantly.
Totals from affected shader
Nanley,
At your request, I did a little fact-finding. I ran all the Sascha demos,
and only one of them ever hits this resolve: computeshader. The demo only
hits it once for the entire run probably because it does
vkCmdCopyBufferToImage at the beginning and then uses it as a storage
image. I'll
On 21/02/18 12:10, Marek Olšák wrote:
On Wed, Feb 21, 2018 at 12:50 AM, Timothy Arceri wrote:
On 21/02/18 10:33, Marek Olšák wrote:
On Tue, Feb 20, 2018 at 11:51 PM, Timothy Arceri
wrote:
On 21/02/18 09:46, Marek Olšák wrote:
On Tue, Feb 20, 2018 at 11:42 PM, Marek Olšák wrote:
Fo
On Wed, Feb 21, 2018 at 12:50 AM, Timothy Arceri wrote:
> On 21/02/18 10:33, Marek Olšák wrote:
>>
>> On Tue, Feb 20, 2018 at 11:51 PM, Timothy Arceri
>> wrote:
>>>
>>> On 21/02/18 09:46, Marek Olšák wrote:
On Tue, Feb 20, 2018 at 11:42 PM, Marek Olšák wrote:
>
>
> For
extraction of linked binary program to a file using glGetProgramBinary.
This file is intended to be loaded by glProgramBinary in the graphic
application running on the target system.
A new option, '--out=' is available to be used for specifying
the output file name.
v2: 1. define MAX_LOG_LEN and
On Wed, Jan 24, 2018 at 11:20:07AM +0200, Pohjolainen, Topi wrote:
> On Fri, Jan 19, 2018 at 11:54:37AM -0800, Rafael Antognolli wrote:
> > Some instructions contain fields that are either an address or a value
> > of some type based on the content of other fields, such as clear color
> > values vs
On Wed, 2018-02-21 at 00:50 +0100, Dieter Nützel wrote:
> Thank you Jan,
>
> much appreciated, but now I get this:
>
> LLVM-CC amdgcn--/lib/math/half_exp.cl.tahiti.bc
> ./amdgcn/lib/workitem/get_global_offset.cl:6:3: error: casting
> '__attribute__((address_space(4)))
>unsigned char *' t
On 21/02/18 10:33, Marek Olšák wrote:
On Tue, Feb 20, 2018 at 11:51 PM, Timothy Arceri wrote:
On 21/02/18 09:46, Marek Olšák wrote:
On Tue, Feb 20, 2018 at 11:42 PM, Marek Olšák wrote:
For patches 1-5:
Reviewed-by: Marek Olšák
Actually no. Only patches 1, 3, 5 are reviewed by me.
Mar
Thank you Jan,
much appreciated, but now I get this:
LLVM-CC amdgcn--/lib/math/half_exp.cl.tahiti.bc
./amdgcn/lib/workitem/get_global_offset.cl:6:3: error: casting
'__attribute__((address_space(4)))
unsigned char *' to type '__attribute__((address_space(2))) uint
*' (aka
'__attribu
Fixes the following piglit tests:
tests/spec/arb_tessellation_shader/execution/double-array-vs-tcs-tes.shader_test
tests/spec/arb_tessellation_shader/execution/double-vs-tcs-tes.shader_test
---
src/gallium/drivers/radeonsi/si_shader.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
dif
We need this to be able to load 64bit varyings.
---
src/amd/common/ac_nir_to_llvm.c | 15 +--
src/amd/common/ac_shader_abi.h| 1 +
src/gallium/drivers/radeonsi/si_shader.c | 2 ++
src/gallium/drivers/radeonsi/si_shader_internal.h | 1 +
On Tue, Feb 20, 2018 at 11:51 PM, Timothy Arceri wrote:
> On 21/02/18 09:46, Marek Olšák wrote:
>>
>> On Tue, Feb 20, 2018 at 11:42 PM, Marek Olšák wrote:
>>>
>>> For patches 1-5:
>>>
>>> Reviewed-by: Marek Olšák
>>
>>
>> Actually no. Only patches 1, 3, 5 are reviewed by me.
>>
>> Marek
>
>
> Do
On Mon, Feb 19, 2018 at 10:01 AM, Chad Versace
wrote:
> On Wed 24 Jan 2018, Jason Ekstrand wrote:
> > We're about to start letting the intel_obj->_Format be the "real"
> > texture format. For depth/stencil textures, this may be a combined
> > depth stencil format. For ETC2 on gen7 and earlier,
On Thu, Feb 15, 2018 at 09:40:16AM +0100, Iago Toral Quiroga wrote:
> We were only resolving the first.
>
> v2:
> - Do not require that the number of layers on dst and src are an
> exact match, it is okay if the dst has more layers so long as
> it has at least the same that we are going
---
src/mesa/drivers/dri/i965/brw_blorp.c | 12 +---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c
b/src/mesa/drivers/dri/i965/brw_blorp.c
index 3c4aef9..6a87e54 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.c
+++ b/src/mesa/drivers
If we use any invalid CCS ops for a particular platform, we will hit an
unreachable() in the blorp back-end. The only on CCS op not supported
by this function at the moment is fast-clear.
---
src/intel/blorp/blorp_clear.c | 12 +---
1 file changed, 1 insertion(+), 11 deletions(-)
diff --
This commit renames blorp_fast_clear to blorp_mcs_clear, pulls in the
fast clear rectangle calculation into the function, and removes the
unneeded level parameter. We could have also removed the x0, y0, x1,
and y1 parameters because all of the callers only do full-slice clears.
However, partial cl
---
src/intel/blorp/blorp_clear.c | 199 +++---
1 file changed, 88 insertions(+), 111 deletions(-)
diff --git a/src/intel/blorp/blorp_clear.c b/src/intel/blorp/blorp_clear.c
index 17d47a1..8d729a2 100644
--- a/src/intel/blorp/blorp_clear.c
+++ b/src/intel/blorp
This little series makes a bunch of mostly small changes to blorp. The end
objective is to get to the point where you just call blorp_ccs_op and hand
it an isl_aux_op instead of having different entrypoints for everything.
This is similar to what we do for HiZ. For MCS, we still have two
function
---
src/intel/vulkan/anv_blorp.c | 28 ++--
1 file changed, 2 insertions(+), 26 deletions(-)
diff --git a/src/intel/vulkan/anv_blorp.c b/src/intel/vulkan/anv_blorp.c
index 3a89ea4..d894b6a 100644
--- a/src/intel/vulkan/anv_blorp.c
+++ b/src/intel/vulkan/anv_blorp.c
@@ -164
The data in the commit message is a bit sketchy for Ivybridge. We don't
run dEQP or any of the CTSs on Ivybridge in CI so all the data we have
is piglit. On Haswell, piglit didn't catch anything so we don't have
anything to go off of for Ivybridge besides the fact that the restriction
wasn't adde
Now that anv uses blorp_ccs_op for everything, we no longer need to
expose the ccs_ambiguate function directly. It's much better tucked
away as an implementation detail.
---
src/intel/blorp/blorp.h | 5 -
src/intel/blorp/blorp_clear.c | 21 ++---
2 files changed, 10 ins
We also make it capable of handling any aux op including fast-clear and
ambiguate.
---
src/intel/blorp/blorp.h | 10
src/intel/blorp/blorp_clear.c | 46 ---
src/intel/vulkan/anv_blorp.c | 4 +--
src/mesa/drivers/dri/i965/brw_
Cannonlake hardware adds a new resolve type in 3DSTATE_PS called
FAST_CLEAR_0 which does an ambiguate. Now that the hardware can do it
directly, we should use that instead of binding the CCS as a render
target and doing it manually. This was tested with a full Vulkan CTS
run on Cannonlake.
---
s
---
src/intel/vulkan/genX_cmd_buffer.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/src/intel/vulkan/genX_cmd_buffer.c
b/src/intel/vulkan/genX_cmd_buffer.c
index 939a795..8015a42 100644
--- a/src/intel/vulkan/genX_cmd_buffer.c
+++ b/src/intel/vulkan/genX_cmd_buffer.c
@@
On 21/02/18 09:46, Marek Olšák wrote:
On Tue, Feb 20, 2018 at 11:42 PM, Marek Olšák wrote:
For patches 1-5:
Reviewed-by: Marek Olšák
Actually no. Only patches 1, 3, 5 are reviewed by me.
Marek
Do you have an issue with patch 4?
___
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On Tue, Feb 20, 2018 at 11:42 PM, Marek Olšák wrote:
> For patches 1-5:
>
> Reviewed-by: Marek Olšák
Actually no. Only patches 1, 3, 5 are reviewed by me.
Marek
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mai
For patches 1-5:
Reviewed-by: Marek Olšák
Marek
On Tue, Feb 20, 2018 at 4:42 AM, Timothy Arceri wrote:
> We also fix the base_index for bindless by using the driver
> location.
> ---
> src/amd/common/ac_nir_to_llvm.c | 14 +++---
> src/amd/common/ac_shader_abi.h
On Tue, Feb 20, 2018 at 4:42 AM, Timothy Arceri wrote:
> ---
> src/gallium/drivers/radeonsi/si_shader_nir.c | 41
> +++-
> 1 file changed, 34 insertions(+), 7 deletions(-)
>
> diff --git a/src/gallium/drivers/radeonsi/si_shader_nir.c
> b/src/gallium/drivers/radeonsi/si_s
On 02/20/2018 04:42 AM, Timothy Arceri wrote:
---
src/gallium/drivers/radeonsi/si_shader_nir.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/src/gallium/drivers/radeonsi/si_shader_nir.c
b/src/gallium/drivers/radeonsi/si_shader_nir.c
index ea9f2076da..974068b88f 10
Quoting Daniel Schürmann (2018-02-20 11:06:37)
> From: Dave Airlie
>
> Signed-off-by: Daniel Schürmann
> ---
> src/amd/common/ac_nir_to_llvm.c | 51 +++
> src/amd/vulkan/radv_extensions.py | 1 +
> src/compiler/nir/meson.build | 1 +
> src/compiler/nir/n
Reviewed-by: Samuel Pitoiset
On 02/20/2018 04:42 AM, Timothy Arceri wrote:
---
src/compiler/glsl/glsl_to_nir.cpp | 1 +
src/compiler/nir/nir.h| 6 ++
2 files changed, 7 insertions(+)
diff --git a/src/compiler/glsl/glsl_to_nir.cpp
b/src/compiler/glsl/glsl_to_nir.cpp
index 7
Thanks for the review. I put my comments below yours.
On Wed, Feb 14, 2018 at 10:56:14AM +0200, Eero Tamminen wrote:
> Hi,
>
> On 13.02.2018 03:26, Dongwon Kim wrote:
> >extraction of linked binary program to a file using glGetProgramBinary.
> >This file is intended to be loaded by glProgramBinar
v2 (Jason Ekstrand):
- Return the correct enum values from anv_layout_to_fast_clear_type
v3 (Jason Ekstrand):
- Always return ANV_FAST_CLEAR_NONE and leave doing the right thing for
the patch which adds a modifier which supports fast-clears.
---
src/intel/vulkan/anv_formats.c | 9
https://bugs.freedesktop.org/show_bug.cgi?id=105179
Gregor Münch changed:
What|Removed |Added
QA Contact|mesa-dev@lists.freedesktop. |dri-devel@lists.freedesktop
On Tue, Feb 20, 2018 at 1:57 PM, Nanley Chery wrote:
> On Tue, Feb 20, 2018 at 11:31:08AM -0800, Jason Ekstrand wrote:
> > On Tue, Feb 20, 2018 at 11:26 AM, Jason Ekstrand
> > wrote:
> >
> > > On Tue, Feb 20, 2018 at 11:25 AM, Nanley Chery
> > > wrote:
> > >
> > >> On Fri, Feb 16, 2018 at 09:28
Acked-by: Pierre Moreau
On 2018-02-20 — 22:02, Karol Herbst wrote:
> v2: allow for non debug builds as well
> v3: move reading out env var more global
> disable tg4 with multiple offsets with nir
> disable caps for 64 bit types
>
> Signed-off-by: Karol Herbst
> ---
> src/gallium/driver
On 02/20/2018 02:25 AM, Dave Airlie wrote:
These are just some cleanups that popped out of a series I was working
on to remove all the tcs/tes user sgprs stuff.
I've got the full patchset working on VI, just need to test on Vega now.
Would be nice to also double-check with a game that needs
Acked-by: Pierre Moreau
On 2018-02-20 — 22:02, Karol Herbst wrote:
> not all those nir options are actually required, it just made the work a
> little easier.
>
> v2: fix asserts
> parse compute shaders
> don't lower bitfield_insert
> v3: fix memory leak
> v4: don't lower fmod32
> v5: se
https://bugs.freedesktop.org/show_bug.cgi?id=105179
--- Comment #1 from Ilia Mirkin ---
(In reply to Gregor Münch from comment #0)
> https://lists.freedesktop.org/archives/mesa-dev/2018-February/185134.html
>
> "except I got a few ltc errors in DiRT
> Rally. Unclear if it's related to this patch
With the variables “dt”, “st” and “std” renamed to match existing code, this
patch is
Reviewed-by: Pierre Moreau
On 2018-02-20 — 22:02, Karol Herbst wrote:
> this is mostly usefull for lazy IR converters not wanting to deal with 64 bit
> lowering and other illegal stuff
>
> v5: also handle SAT
On Tue, Feb 20, 2018 at 11:31:08AM -0800, Jason Ekstrand wrote:
> On Tue, Feb 20, 2018 at 11:26 AM, Jason Ekstrand
> wrote:
>
> > On Tue, Feb 20, 2018 at 11:25 AM, Nanley Chery
> > wrote:
> >
> >> On Fri, Feb 16, 2018 at 09:28:43AM -0800, Jason Ekstrand wrote:
> >> > ---
> >> > src/intel/vulkan
---
src/intel/vulkan/genX_cmd_buffer.c | 53 +-
1 file changed, 35 insertions(+), 18 deletions(-)
diff --git a/src/intel/vulkan/genX_cmd_buffer.c
b/src/intel/vulkan/genX_cmd_buffer.c
index 5c36fc7..8bd824b 100644
--- a/src/intel/vulkan/genX_cmd_buffer.c
+++ b/
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