From: Dave Airlie <airl...@redhat.com>
This drops the now unneeded scanning and results in favour
of the ones in the info.
Signed-off-by: Dave Airlie <airl...@redhat.com>
---
src/amd/common/ac_nir_to_llvm.c | 28 ----------------------------
src/amd/common/ac_nir_to_llvm.h | 4 ----
src/amd/vulkan/radv_pipeline.c | 7 +++----
3 files changed, 3 insertions(+), 36 deletions(-)
diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index d43c0ab7fe9..c235c5314be 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -117,8 +117,6 @@ struct radv_shader_context {
unsigned gs_max_out_vertices;
unsigned tes_primitive_mode;
- uint64_t tess_outputs_written;
- uint64_t tess_patch_outputs_written;
uint32_t tcs_patch_outputs_read;
uint64_t tcs_outputs_read;
@@ -2852,17 +2850,6 @@ static LLVMValueRef
get_tcs_tes_buffer_address_params(struct radv_shader_context
return get_tcs_tes_buffer_address(ctx, vertex_index, param_index);
}
-static void
-mark_tess_output(struct radv_shader_context *ctx,
- bool is_patch, uint32_t param)
-
-{
- if (is_patch) {
- ctx->tess_patch_outputs_written |= (1ull << param);
- } else
- ctx->tess_outputs_written |= (1ull << param);
-}
-
static LLVMValueRef
get_dw_address(struct radv_shader_context *ctx,
LLVMValueRef dw_addr,
@@ -2986,8 +2973,6 @@ store_tcs_output(struct ac_shader_abi *abi,
dw_addr = get_tcs_out_current_patch_data_offset(ctx);
}
- mark_tess_output(ctx, is_patch, param);
-
dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact,
vertex_index, stride,
param_index);
buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index,
is_compact,
@@ -6273,9 +6258,6 @@ handle_ls_outputs_post(struct radv_shader_context *ctx)
if (i == VARYING_SLOT_CLIP_DIST0)
length = ctx->num_output_clips + ctx->num_output_culls;
int param = shader_io_get_unique_index(i);
- mark_tess_output(ctx, false, param);
- if (length > 4)
- mark_tess_output(ctx, false, param + 1);
LLVMValueRef dw_addr = LLVMBuildAdd(ctx->ac.builder,
base_dw_addr,
LLVMConstInt(ctx->ac.i32,
param * 4, false),
"");
@@ -6419,13 +6401,11 @@ write_tess_factors(struct radv_shader_context *ctx)
if (inner_comps) {
tess_inner_index =
shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
- mark_tess_output(ctx, true, tess_inner_index);
lds_inner = LLVMBuildAdd(ctx->ac.builder, lds_base,
LLVMConstInt(ctx->ac.i32,
tess_inner_index * 4, false), "");
}
tess_outer_index =
shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
- mark_tess_output(ctx, true, tess_outer_index);
lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_base,
LLVMConstInt(ctx->ac.i32, tess_outer_index *
4, false), "");
@@ -6910,7 +6890,6 @@ LLVMModuleRef
ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
for(int i = 0; i < shader_count; ++i) {
ctx.stage = shaders[i]->info.stage;
ctx.output_mask = 0;
- ctx.tess_outputs_written = 0;
ctx.num_output_clips =
shaders[i]->info.clip_distance_array_size;
ctx.num_output_culls =
shaders[i]->info.cull_distance_array_size;
@@ -7001,14 +6980,7 @@ LLVMModuleRef
ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
shader_info->gs.max_gsvs_emit_size =
shader_info->gs.gsvs_vertex_size *
shaders[i]->info.gs.vertices_out;
} else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
- shader_info->tcs.outputs_written =
ctx.tess_outputs_written;
- shader_info->tcs.patch_outputs_written =
ctx.tess_patch_outputs_written;
shader_info->tcs.num_patches = ctx.tcs_num_patches;
- assert(ctx.tess_outputs_written ==
ctx.shader_info->info.tcs.outputs_written);
- assert(ctx.tess_patch_outputs_written ==
ctx.shader_info->info.tcs.patch_outputs_written);
- } else if (shaders[i]->info.stage == MESA_SHADER_VERTEX &&
ctx.options->key.vs.as_ls) {
- shader_info->vs.outputs_written =
ctx.tess_outputs_written;
- assert(ctx.tess_outputs_written ==
ctx.shader_info->info.vs.ls_outputs_written);
}
}
diff --git a/src/amd/common/ac_nir_to_llvm.h b/src/amd/common/ac_nir_to_llvm.h
index 48a4a5b2049..62ce72fb7d2 100644
--- a/src/amd/common/ac_nir_to_llvm.h
+++ b/src/amd/common/ac_nir_to_llvm.h
@@ -172,7 +172,6 @@ struct ac_shader_variant_info {
unsigned vgpr_comp_cnt;
bool as_es;
bool as_ls;
- uint64_t outputs_written;
} vs;
struct {
unsigned num_interp;
@@ -199,9 +198,6 @@ struct ac_shader_variant_info {
struct {
unsigned tcs_vertices_out;
/* Which outputs are actually written */
- uint64_t outputs_written;
- /* Which patch outputs are actually written */
- uint32_t patch_outputs_written;
uint32_t num_patches;
} tcs;
struct {
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index c7c23a85ac1..195daf6abde 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -1317,11 +1317,10 @@ calculate_tess_state(struct radv_pipeline *pipeline,
/* This calculates how shader inputs and outputs among VS, TCS, and TES
* are laid out in LDS. */
- num_tcs_inputs =
util_last_bit64(radv_get_vertex_shader(pipeline)->info.vs.outputs_written);
-
- num_tcs_outputs =
util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.outputs_written);
//tcs->outputs_written
+ num_tcs_inputs =
util_last_bit64(radv_get_vertex_shader(pipeline)->info.info.vs.ls_outputs_written);
+ num_tcs_outputs =
util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.info.tcs.outputs_written);
//tcs->outputs_written
num_tcs_output_cp =
pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.tcs_vertices_out; //TCS
VERTICES OUT
- num_tcs_patch_outputs =
util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.patch_outputs_written);
+ num_tcs_patch_outputs =
util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.info.tcs.patch_outputs_written);
/* Ensure that we only need one wave per SIMD so we don't need to check
* resource usage. Also ensures that the number of tcs in and out
--
2.14.3
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