From: Dave Airlie <airl...@redhat.com>
Inline all calcs at shader creation.
Signed-off-by: Dave Airlie <airl...@redhat.com>
---
src/amd/common/ac_nir_to_llvm.c | 27 ++++++++++++++++++---------
src/amd/common/ac_nir_to_llvm.h | 1 +
src/amd/vulkan/radv_pipeline.c | 12 ++++++------
3 files changed, 25 insertions(+), 15 deletions(-)
diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index ce3679abedc..923bfaabb97 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -84,7 +84,6 @@ struct radv_shader_context {
LLVMValueRef tcs_offchip_layout;
LLVMValueRef tcs_out_offsets;
LLVMValueRef tcs_out_layout;
- LLVMValueRef tcs_in_layout;
LLVMValueRef oc_lds;
LLVMValueRef merged_wave_info;
LLVMValueRef tess_factor_offset;
@@ -127,6 +126,7 @@ struct radv_shader_context {
uint32_t tcs_patch_outputs_read;
uint64_t tcs_outputs_read;
uint32_t tcs_vertices_per_patch;
+ uint32_t tcs_num_inputs;
};
static inline struct radv_shader_context *
@@ -345,7 +345,11 @@ static LLVMValueRef
get_tcs_in_patch_stride(struct radv_shader_context *ctx)
{
assert (ctx->stage == MESA_SHADER_TESS_CTRL);
- return unpack_param(&ctx->ac, ctx->tcs_in_layout, 0, 13);
+ uint32_t input_vertex_size = ctx->tcs_num_inputs * 16;
+ uint32_t input_patch_size = ctx->options->key.tcs.input_vertices *
input_vertex_size;
+
+ input_patch_size /= 4;
+ return LLVMConstInt(ctx->ac.i32, input_patch_size, false);
}
static LLVMValueRef
@@ -529,7 +533,7 @@ static void allocate_user_sgprs(struct radv_shader_context
*ctx,
if (previous_stage == MESA_SHADER_VERTEX)
user_sgpr_info->sgpr_count +=
count_vs_user_sgprs(ctx);
}
- user_sgpr_info->sgpr_count += 4;
+ user_sgpr_info->sgpr_count += 3;
break;
case MESA_SHADER_TESS_EVAL:
user_sgpr_info->sgpr_count += 1;
@@ -802,8 +806,6 @@ static void create_function(struct radv_shader_context *ctx,
&ctx->tcs_out_offsets);
add_arg(&args, ARG_SGPR, ctx->ac.i32,
&ctx->tcs_out_layout);
- add_arg(&args, ARG_SGPR, ctx->ac.i32,
- &ctx->tcs_in_layout);
if (needs_view_index)
add_arg(&args, ARG_SGPR, ctx->ac.i32,
&ctx->abi.view_index);
@@ -827,8 +829,6 @@ static void create_function(struct radv_shader_context *ctx,
&ctx->tcs_out_offsets);
add_arg(&args, ARG_SGPR, ctx->ac.i32,
&ctx->tcs_out_layout);
- add_arg(&args, ARG_SGPR, ctx->ac.i32,
- &ctx->tcs_in_layout);
if (needs_view_index)
add_arg(&args, ARG_SGPR, ctx->ac.i32,
&ctx->abi.view_index);
@@ -1037,7 +1037,7 @@ static void create_function(struct radv_shader_context
*ctx,
case MESA_SHADER_TESS_CTRL:
set_vs_specific_input_locs(ctx, stage, has_previous_stage,
previous_stage, &user_sgpr_idx);
- set_loc_shader(ctx, AC_UD_TCS_OFFCHIP_LAYOUT, &user_sgpr_idx,
4);
+ set_loc_shader(ctx, AC_UD_TCS_OFFCHIP_LAYOUT, &user_sgpr_idx,
3);
if (ctx->abi.view_index)
set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx,
1);
break;
@@ -2857,7 +2857,9 @@ load_tcs_varyings(struct ac_shader_abi *abi,
unsigned param = shader_io_get_unique_index(location);
if (load_input) {
- stride = unpack_param(&ctx->ac, ctx->tcs_in_layout, 13, 8);
+ uint32_t input_vertex_size = ctx->tcs_num_inputs * 16;
+ input_vertex_size /= 4;
+ stride = LLVMConstInt(ctx->ac.i32, input_vertex_size, false);
dw_addr = get_tcs_in_current_patch_offset(ctx);
} else {
if (!is_patch) {
@@ -6863,6 +6865,10 @@ LLVMModuleRef
ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
ctx.abi.load_patch_vertices_in = load_patch_vertices_in;
ctx.abi.store_tcs_outputs = store_tcs_output;
ctx.tcs_vertices_per_patch =
shaders[i]->info.tess.tcs_vertices_out;
+ if (shader_count == 1)
+ ctx.tcs_num_inputs =
ctx.options->key.tcs.num_inputs;
+ else
+ ctx.tcs_num_inputs =
util_last_bit64(shader_info->info.vs.ls_outputs_written);
} else if (shaders[i]->info.stage == MESA_SHADER_TESS_EVAL) {
ctx.tes_primitive_mode =
shaders[i]->info.tess.primitive_mode;
ctx.abi.load_tess_varyings = load_tes_input;
@@ -6934,8 +6940,11 @@ LLVMModuleRef
ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
} else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
shader_info->tcs.outputs_written =
ctx.tess_outputs_written;
shader_info->tcs.patch_outputs_written =
ctx.tess_patch_outputs_written;
+ assert(ctx.tess_outputs_written ==
ctx.shader_info->info.tcs.outputs_written);
+ assert(ctx.tess_patch_outputs_written ==
ctx.shader_info->info.tcs.patch_outputs_written);
} else if (shaders[i]->info.stage == MESA_SHADER_VERTEX &&
ctx.options->key.vs.as_ls) {
shader_info->vs.outputs_written =
ctx.tess_outputs_written;
+ assert(ctx.tess_outputs_written ==
ctx.shader_info->info.vs.ls_outputs_written);
}
}
diff --git a/src/amd/common/ac_nir_to_llvm.h b/src/amd/common/ac_nir_to_llvm.h
index b1cc2b742b4..5f8dcd3b9b4 100644
--- a/src/amd/common/ac_nir_to_llvm.h
+++ b/src/amd/common/ac_nir_to_llvm.h
@@ -55,6 +55,7 @@ struct ac_tcs_variant_key {
struct ac_vs_variant_key vs_key;
unsigned primitive_mode;
unsigned input_vertices;
+ unsigned num_inputs;
uint32_t tes_reads_tess_factors:1;
};
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index 67bf3550b7c..79a9c1f6c87 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -62,7 +62,6 @@ struct radv_blend_state {
struct radv_tessellation_state {
uint32_t ls_hs_config;
- uint32_t tcs_in_layout;
uint32_t tcs_out_layout;
uint32_t tcs_out_offsets;
uint32_t offchip_layout;
@@ -1383,8 +1382,6 @@ calculate_tess_state(struct radv_pipeline *pipeline,
tess.lds_size = lds_size;
- tess.tcs_in_layout = (input_patch_size / 4) |
- ((input_vertex_size / 4) << 13);
tess.tcs_out_layout = (output_patch_size / 4) |
((output_vertex_size / 4) << 13);
tess.tcs_out_offsets = (output_patch0_offset / 16) |
@@ -1597,6 +1594,7 @@ radv_fill_shader_keys(struct ac_shader_variant_key *keys,
if (nir[MESA_SHADER_TESS_CTRL]) {
keys[MESA_SHADER_VERTEX].vs.as_ls = true;
+ keys[MESA_SHADER_TESS_CTRL].tcs.num_inputs = 0;
keys[MESA_SHADER_TESS_CTRL].tcs.input_vertices =
key->tess_input_vertices;
keys[MESA_SHADER_TESS_CTRL].tcs.primitive_mode =
nir[MESA_SHADER_TESS_EVAL]->info.tess.primitive_mode;
@@ -1811,6 +1809,9 @@ void radv_create_shaders(struct radv_pipeline *pipeline,
for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
if(modules[i] && !pipeline->shaders[i]) {
+ if (i == MESA_SHADER_TESS_CTRL) {
+ keys[MESA_SHADER_TESS_CTRL].tcs.num_inputs =
util_last_bit64(pipeline->shaders[MESA_SHADER_VERTEX]->info.info.vs.ls_outputs_written);
+ }
pipeline->shaders[i] =
radv_shader_variant_create(device, modules[i], &nir[i], 1,
pipeline->layout,
keys
+ i, &codes[i],
@@ -2614,13 +2615,12 @@ radv_pipeline_generate_tess_shaders(struct
radeon_winsys_cs *cs,
loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_TESS_CTRL,
AC_UD_TCS_OFFCHIP_LAYOUT);
if (loc->sgpr_idx != -1) {
uint32_t base_reg =
pipeline->user_data_0[MESA_SHADER_TESS_CTRL];
- assert(loc->num_sgprs == 4);
+ assert(loc->num_sgprs == 3);
assert(!loc->indirect);
- radeon_set_sh_reg_seq(cs, base_reg + loc->sgpr_idx * 4, 4);
+ radeon_set_sh_reg_seq(cs, base_reg + loc->sgpr_idx * 4, 3);
radeon_emit(cs, tess->offchip_layout);
radeon_emit(cs, tess->tcs_out_offsets);
radeon_emit(cs, tess->tcs_out_layout);
- radeon_emit(cs, tess->tcs_in_layout);
}
loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_TESS_EVAL,
AC_UD_TES_OFFCHIP_LAYOUT);
--
2.14.3
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