> +LLVMValueRef
> +ac_build_subgroup_inclusive_scan(struct ac_llvm_context *ctx,
> +LLVMValueRef src,
> +ac_reduce_op reduce,
> +LLVMValueRef identity)
> +{
> + /* See http://gpuopen.com/amd-gcn-as
On Monday, October 30, 2017 2:14:24 PM PDT Plamena Manolova wrote:
> This patch modifies the ARB_indirect_parameters logic in
> brw_draw_prims, so that our implementation isn't affected if
> another application attempts to use predicates. Previously we
> were using a predicate with a DELTAS_EQUAL c
Hi Dylan,
I took a crack at testing this one. My BARTS (Radeon 6850) seems to
be running through piglit with a reasonable pass-rate afterwards, a
restart of GDM/gnome went fine, and at least xonotic launched and is
running.
I did attempt to build it with vdpau/va gallium-media api support (as
de
In RADV we need to offset the writemask because
nir_lower_clip_cull_distance_arrays() combines the arrays. However
we can't use this with radeonsi currently so don't offset the
writemask.
Fixes the following piglit tests:
arb_cull_distance/clip-cull-3.shader_test
arb_cull_distance/clip-cull-4.sha
On Sun, Oct 22, 2017 at 9:07 PM, Nicolai Hähnle wrote:
> @@ -107,20 +138,46 @@ static boolean si_fence_finish(struct pipe_screen
> *screen,
>uint64_t timeout)
> {
> struct radeon_winsys *rws = ((struct r600_common_screen*)screen)->ws;
> struct si_m
From: Dave Airlie
I was hacking something stupid in doom, and hit an assert for the bitcast
following this, it definitely looks like this should be the number of 32-bit
components, not the instr level ones.
Signed-off-by: Dave Airlie
---
src/amd/common/ac_nir_to_llvm.c | 2 +-
1 file changed,
Dylan Baker writes:
> This is done in autotools, and is an oversight in the meson build.
>
> Signed-off-by: Dylan Baker
Both are:
Reviewed-by: Eric Anholt
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R-b
On 31 Oct 2017 01:35, "Timothy Arceri" wrote:
> Fixes regression in:
>
> dEQP-VK.api.object_management.alloc_callback_fail.graphics_pipeline
>
> Fixes: 1e84e53712ae "radv: add cache items to in memory cache when reading
> from disk"
> ---
> src/amd/vulkan/radv_pipeline_cache.c | 15
On Thu, Oct 12, 2017 at 11:38 AM, Jose Maria Casanova Crespo <
jmcasan...@igalia.com> wrote:
> From: Eduardo Lima Mitev
>
> Currently, we use byte-scattered write messages for storing 16-bit
> into an SSBO. This is because untyped surface messages have a fixed
> 32-bit size.
>
> This patch optimi
Fixes regression in:
dEQP-VK.api.object_management.alloc_callback_fail.graphics_pipeline
Fixes: 1e84e53712ae "radv: add cache items to in memory cache when reading from
disk"
---
src/amd/vulkan/radv_pipeline_cache.c | 15 ++-
1 file changed, 14 insertions(+), 1 deletion(-)
diff --g
On Fri, Oct 06, 2017 at 04:30:47PM -0700, Anuj Phogat wrote:
> There are few other (duplicate) workarounds which have similar
> recommendations:
> WaFlushHangWhenNonPipelineStateAndMarkerStalled
> WaCSStallBefore3DSamplePattern
> WaPipeControlBefore3DStateSamplePattern
>
> WaPipeControlBefore3DSt
Patches 1-5, 8-11, and 13-18 are
Reviewed-by: Jason Ekstrand
On Mon, Oct 16, 2017 at 8:23 AM, Pohjolainen, Topi <
topi.pohjolai...@gmail.com> wrote:
> On Mon, Oct 16, 2017 at 08:03:41AM -0700, Jason Ekstrand wrote:
> > FYI: I'm planning to review this some time this week. Probably not today
>
On Thu, Oct 12, 2017 at 11:38 AM, Jose Maria Casanova Crespo <
jmcasan...@igalia.com> wrote:
> From: Alejandro Piñeiro
>
> We need to rely on byte scattered writes as untyped writes are 32-bit
> size. We could try to keep using 32-bit messages when we have two or
> four 16-bit elements, but for s
This patch should really be squashed in with the next one.
On Thu, Oct 12, 2017 at 11:38 AM, Jose Maria Casanova Crespo <
jmcasan...@igalia.com> wrote:
> From: Alejandro Piñeiro
>
> ---
> src/intel/compiler/brw_fs_nir.cpp | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --
On Thu, Oct 12, 2017 at 11:38 AM, Jose Maria Casanova Crespo <
jmcasan...@igalia.com> wrote:
> Signed-off-by: Jose Maria Casanova Crespo
> Signed-off-by: Alejandro Piñeiro
> ---
> src/intel/compiler/brw_eu.h| 6 ++
> src/intel/compiler/brw_eu_defines.h| 17 +
Kenneth Graunke writes:
> Groups containing fields smaller than a byte probably not being decoded
> correctly. For example:
>
>
>
>
>
> gen_field_iterator_next would properly walk over each element of the
> array, incrementing group_iter. However, the code to print the actual
>
On Thu, Oct 12, 2017 at 11:38 AM, Jose Maria Casanova Crespo <
jmcasan...@igalia.com> wrote:
> We enable the use of 16-bit values in push constants
> modifying the assign_constant_locations function to work
> with 16-bit types.
>
> The API to access buffers in Vulkan use multiples of 4-byte for
>
On Sunday, October 29, 2017 5:21:47 PM PDT Jordan Justen wrote:
> On 2017-10-29 01:11:32, Kenneth Graunke wrote:
> > On Sunday, October 22, 2017 1:01:36 PM PDT Jordan Justen wrote:
> > > If the i965 gen program cannot be loaded from the cache, then we
> > > fallback to using a serialized nir progra
On Sunday, October 22, 2017 1:01:42 PM PDT Jordan Justen wrote:
> Double negative FTW!
>
> For now, the shader cache is disabled by default on i965 to allow us
> to verify its stability.
>
> In other words, to enable the shader cache on i965, set
> MESA_GLSL_CACHE_DISABLE to false or 0. If the va
On Sunday, October 22, 2017 1:01:41 PM PDT Jordan Justen wrote:
> Cc: Dylan Baker
> Signed-off-by: Jordan Justen
> ---
> src/mesa/drivers/dri/Makefile.am | 1 +
> src/mesa/drivers/dri/meson.build | 2 +-
> 2 files changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/src/mesa/drivers/dri/Mak
On Sunday, October 22, 2017 1:01:40 PM PDT Jordan Justen wrote:
> This would cause the read of the metadata content to fail, which would
> prevent the linking from being skipped.
>
> Seen on Rocket League with i965 shader cache.
>
> Cc: Timothy Arceri
> Signed-off-by: Jordan Justen
> Reviewed-b
On Sunday, October 22, 2017 1:01:38 PM PDT Jordan Justen wrote:
> Signed-off-by: Jordan Justen
> Reviewed-by: Timothy Arceri
> ---
> src/mesa/drivers/dri/i965/brw_context.c | 4
> src/mesa/drivers/dri/i965/brw_context.h | 1 +
> 2 files changed, 5 insertions(+)
>
> diff --git a/src/mesa/dr
On Mon, Oct 30, 2017 at 12:54:43AM -0700, Kenneth Graunke wrote:
> Due to a gaffe on my part, we were re-emitting all binding table entries
> on every single draw call. The push_constant_packets atom listens to
> BRW_NEW_DRAW_CALL, but skips emitting 3DSTATE_CONSTANT_XS for each stage
> unless sta
On Mon, Oct 30, 2017 at 2:02 PM, Nanley Chery wrote:
> On Mon, Oct 02, 2017 at 04:07:58PM -0700, Anuj Phogat wrote:
>> Cc: mesa-sta...@lists.freedesktop.org
>> Signed-off-by: Anuj Phogat
>> ---
>> src/mesa/drivers/dri/i965/brw_pipe_control.c | 19 +++
>> 1 file changed, 19 insert
On Sunday, October 22, 2017 1:01:37 PM PDT Jordan Justen wrote:
> Signed-off-by: Jordan Justen
> Cc: Timothy Arceri
> ---
> src/mesa/drivers/dri/i965/brw_link.cpp | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_link.cpp
> b/src/mesa/drivers/dri/i965/br
Dylan Baker writes:
> This allows a user to not care whether they're setting a tristate or a
> boolean option, which is a nice user facing feature, and something I've
> personally run into.
>
> Suggested-by: Adam Jackson
> Signed-off-by: Dylan Baker
Reviewed-by: Eric Anholt
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Erik Faye-Lund writes:
> The u_format_other.c users sqrtf, which on some systems require
> a math-library. So let's make sure we link with it.
>
> Signed-off-by: Erik Faye-Lund
Reviewed-by: Eric Anholt
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m
On Thu, Oct 12, 2017 at 11:38 AM, Jose Maria Casanova Crespo <
jmcasan...@igalia.com> wrote:
> From: Alejandro Piñeiro
>
> By default we don't set the rounding mode. We only set
> round-to-near-even or round-to-zero mode if explicitly set from nir.
>
> v2: Use a single SHADER_OPCODE_RND_MODE opco
https://bugs.freedesktop.org/show_bug.cgi?id=103496
Ian Romanick changed:
What|Removed |Added
Resolution|--- |FIXED
Status|NEW
On Mon, Oct 30, 2017 at 3:08 PM, Jason Ekstrand
wrote:
> On Thu, Oct 12, 2017 at 11:38 AM, Jose Maria Casanova Crespo <
> jmcasan...@igalia.com> wrote:
>
>> From: Alejandro Piñeiro
>>
>> Returns the brw_type for a given ssa.bit_size, and a reference type.
>> So if bit_size is 64, and the referen
On Thu, Oct 12, 2017 at 11:38 AM, Jose Maria Casanova Crespo <
jmcasan...@igalia.com> wrote:
> From: Alejandro Piñeiro
>
> Returns the brw_type for a given ssa.bit_size, and a reference type.
> So if bit_size is 64, and the reference type is BRW_REGISTER_TYPE_F,
> it returns BRW_REGISTER_TYPE_DF.
On Thu, Oct 12, 2017 at 11:37 AM, Jose Maria Casanova Crespo <
jmcasan...@igalia.com> wrote:
> SpvOpFConvert now manages the FPRoundingMode decorator for the
> returning values enabling the nir_rounding_mode in the conversion
> operation to fp16 values.
>
> v2: Fixed breaking of specialization con
On Thu, Oct 12, 2017 at 11:37 AM, Jose Maria Casanova Crespo <
jmcasan...@igalia.com> wrote:
> From: Eduardo Lima Mitev
>
> v2: Added more missing implementations of 16-bit types. (Jason Ekstrand)
>
> Signed-off-by: Jose Maria Casanova Crespo
> Signed-off-by: Eduardo Lima
> ---
> src/compiler/
On Thu, Oct 12, 2017 at 11:37 AM, Jose Maria Casanova Crespo <
jmcasan...@igalia.com> wrote:
> nir_type_conversion enables new operations to handle rounding modes to
> convert to fp16 values. Two new opcodes are enabled nir_op_f2f16_rtne
> and nir_op_f2f16_rtz.
>
> The undefined behaviour doesn't
This patch modifies the ARB_indirect_parameters logic in
brw_draw_prims, so that our implementation isn't affected if
another application attempts to use predicates. Previously we
were using a predicate with a DELTAS_EQUAL comparison operation
and relying on the MI_PREDICATE_DATA register being 0.
On Mon, Oct 02, 2017 at 04:07:58PM -0700, Anuj Phogat wrote:
> Cc: mesa-sta...@lists.freedesktop.org
> Signed-off-by: Anuj Phogat
> ---
> src/mesa/drivers/dri/i965/brw_pipe_control.c | 19 +++
> 1 file changed, 19 insertions(+)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_pipe_
Bump. Any update on this?
On Tue, 2017-10-24 at 14:03 -0700, Jason Ekstrand wrote:
> On Tue, Oct 24, 2017 at 9:06 AM, Chris Wilson
> wrote:
> > Through the use of mocs, we can define the cache usage for any surface
> >
> > used by the GPU. In particular, we can request that L3 cache be
> >
> > a
On Mon, Oct 30, 2017 at 11:53 AM, Jason Ekstrand
wrote:
> On Mon, Oct 30, 2017 at 5:10 AM, Iago Toral wrote:
>
>> On Wed, 2017-10-25 at 16:26 -0700, Jason Ekstrand wrote:
>> > Ballot intrinsics return a bitfield of subgroups. In GLSL and some
>> > SPIR-V extensions, they return a uint64_t. In
On Mon, Oct 30, 2017 at 12:28:53PM -0700, Anuj Phogat wrote:
> On Mon, Oct 30, 2017 at 11:08 AM, Nanley Chery wrote:
> > On Mon, Oct 02, 2017 at 04:08:00PM -0700, Anuj Phogat wrote:
> >> Cc: mesa-sta...@lists.freedesktop.org
> >> Signed-off-by: Anuj Phogat
> >> ---
> >> src/mesa/drivers/dri/i965
The u_format_other.c users sqrtf, which on some systems require
a math-library. So let's make sure we link with it.
Signed-off-by: Erik Faye-Lund
---
I noticed this while debugging something else, thought I'd just send it
upstream directly.
src/gallium/auxiliary/meson.build | 2 +-
1 file chan
On Mon, Oct 30, 2017 at 11:03 AM, Nanley Chery wrote:
> On Mon, Oct 02, 2017 at 04:07:59PM -0700, Anuj Phogat wrote:
>> This optimization is enabled for previous generations too.
>> See Mesa commit c17e214a6b
>> On CNL this bit is moved to 3DSTATE_3D_MODE.
>
> Is this true? Looking at the HW docs,
On Mon, Oct 30, 2017 at 11:08 AM, Nanley Chery wrote:
> On Mon, Oct 02, 2017 at 04:08:00PM -0700, Anuj Phogat wrote:
>> Cc: mesa-sta...@lists.freedesktop.org
>> Signed-off-by: Anuj Phogat
>> ---
>> src/mesa/drivers/dri/i965/brw_state_upload.c | 7 +--
>> 1 file changed, 5 insertions(+), 2 de
On Mon, Oct 30, 2017 at 5:10 AM, Iago Toral wrote:
> On Wed, 2017-10-25 at 16:26 -0700, Jason Ekstrand wrote:
> > Ballot intrinsics return a bitfield of subgroups. In GLSL and some
> > SPIR-V extensions, they return a uint64_t. In SPV_KHR_shader_ballot,
> > they return a uvec4. Also, some back
On Mon, Oct 30, 2017 at 4:38 AM, Iago Toral wrote:
> On Wed, 2017-10-25 at 16:26 -0700, Jason Ekstrand wrote:
> > This commit pulls nir_lower_read_invocations_to_scalar along with
> > most
> > of the guts of nir_opt_intrinsics (which mostly does subgroup
> > lowering)
> > into a new nir_lower_sub
On Mon, Oct 30, 2017 at 12:43 AM, Iago Toral wrote:
> On Fri, 2017-10-27 at 12:43 -0700, Jason Ekstrand wrote:
>
> On Fri, Oct 27, 2017 at 12:35 AM, Iago Toral wrote:
>
> This sounds good to me, but I guess it is not really fixing anything,
> right? I ask because the subject claims that this pat
Signed-off-by: Samuel Pitoiset
---
src/amd/vulkan/radv_cmd_buffer.c | 18 --
1 file changed, 16 insertions(+), 2 deletions(-)
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index 00ed7182a7..4b38ece10f 100644
--- a/src/amd/vulkan/radv_cmd_buffer.
On Mon, Oct 30, 2017 at 12:33 AM, Iago Toral wrote:
> On Fri, 2017-10-27 at 12:37 -0700, Jason Ekstrand wrote:
>
> On Fri, Oct 27, 2017 at 2:11 AM, Iago Toral wrote:
>
> On Wed, 2017-10-25 at 16:26 -0700, Jason Ekstrand wrote:
> > Previously, brw_nir_lower_intrinsics added the param and then emi
Quoting Eric Engestrom (2017-10-30 10:29:25)
> On Monday, 2017-10-30 10:21:50 -0700, Dylan Baker wrote:
> > This allows drivers to be set by OS/arch in a sane manner.
> >
> > Signed-off-by: Dylan Baker
> > ---
> > meson.build | 37 +++--
> > meson_options.tx
It's supposed to be linked with pthread-stubs (if the platform needs
pthread-stubs). Pthread stubs support isn't (yet) implemented in the
meson build, so add a TODO.
Signed-off-by: Dylan Baker
---
src/gbm/meson.build | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/gbm/mes
This is done in autotools, and is an oversight in the meson build.
Signed-off-by: Dylan Baker
---
src/gbm/meson.build | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/gbm/meson.build b/src/gbm/meson.build
index fc1816cc17a..2fad2a2a8e3 100644
--- a/src/gbm/meson.build
+++
On Mon, Oct 30, 2017 at 12:15 AM, Iago Toral wrote:
> On Fri, 2017-10-27 at 12:21 -0700, Jason Ekstrand wrote:
>
> On Thu, Oct 26, 2017 at 11:53 PM, Iago Toral wrote:
>
> On Wed, 2017-10-25 at 16:25 -0700, Jason Ekstrand wrote:
> > ---
> > src/intel/compiler/brw_fs_nir.cpp | 33
On Mon, Oct 02, 2017 at 04:08:00PM -0700, Anuj Phogat wrote:
> Cc: mesa-sta...@lists.freedesktop.org
> Signed-off-by: Anuj Phogat
> ---
> src/mesa/drivers/dri/i965/brw_state_upload.c | 7 +--
> 1 file changed, 5 insertions(+), 2 deletions(-)
>
Assuming my comment in patch 3 is correct, we n
On Mon, Oct 02, 2017 at 04:07:59PM -0700, Anuj Phogat wrote:
> This optimization is enabled for previous generations too.
> See Mesa commit c17e214a6b
> On CNL this bit is moved to 3DSTATE_3D_MODE.
Is this true? Looking at the HW docs, I actually found this bit to exist
in CACHE_MODE_SS. Bit 9 of
On Mon, Oct 30, 2017 at 10:40 AM, Rafael Antognolli <
rafael.antogno...@intel.com> wrote:
> On Thu, Oct 05, 2017 at 10:53:42AM -0700, Anuj Phogat wrote:
> > On Wed, Oct 4, 2017 at 9:29 PM, Jason Ekstrand
> wrote:
> > > On Wed, Oct 4, 2017 at 3:11 PM, Anuj Phogat
> wrote:
> > >>
> > >> On Mon, Oc
On 30 October 2017 at 17:05, Dylan Baker wrote:
> So I think the consensus is this is okay?
>
> Emil, is the autotools right here?
>
Without a clear separation or cleanup of the the existing code, this
such move brings no technical benefit.
If anything, it makes it harder for people [roughly] fam
On Thu, Oct 05, 2017 at 10:53:42AM -0700, Anuj Phogat wrote:
> On Wed, Oct 4, 2017 at 9:29 PM, Jason Ekstrand wrote:
> > On Wed, Oct 4, 2017 at 3:11 PM, Anuj Phogat wrote:
> >>
> >> On Mon, Oct 2, 2017 at 7:46 PM, Jason Ekstrand
> >> wrote:
> >> > On Mon, Oct 2, 2017 at 4:08 PM, Anuj Phogat
> >
On Mon, Oct 23, 2017 at 08:46:26AM -0700, Anuj Phogat wrote:
> Ping. Patches 2-4 in this series are still waiting for review.
> Anyone interested?
> Thanks!
>
>
>
> On Fri, Oct 13, 2017 at 3:35 PM, Rafael Antognolli
> wrote:
> > Hi Anuj, sorry that I missed this patch. Please see below.
> >
> >
On Fri, Oct 27, 2017 at 05:14:16PM -0700, Jason Ekstrand wrote:
> On Fri, Oct 27, 2017 at 3:16 PM, Nanley Chery wrote:
>
> > On Fri, Oct 27, 2017 at 12:52:30PM -0700, Jason Ekstrand wrote:
> > > On Fri, Oct 27, 2017 at 12:24 PM, Nanley Chery
> > > wrote:
> > >
> > > > Only use CCS_E to render to
This allows a user to not care whether they're setting a tristate or a
boolean option, which is a nice user facing feature, and something I've
personally run into.
Suggested-by: Adam Jackson
Signed-off-by: Dylan Baker
---
meson.build | 6 +++---
meson_options.txt | 6 +++---
2 files chang
https://bugs.freedesktop.org/show_bug.cgi?id=102677
Neil Roberts changed:
What|Removed |Added
Resolution|--- |FIXED
Status|NEW
On Monday, 2017-10-30 10:21:50 -0700, Dylan Baker wrote:
> This allows drivers to be set by OS/arch in a sane manner.
>
> Signed-off-by: Dylan Baker
> ---
> meson.build | 37 +++--
> meson_options.txt | 8
> 2 files changed, 39 insertions(+), 6 del
https://bugs.freedesktop.org/show_bug.cgi?id=103496
--- Comment #3 from Eric Engestrom ---
(In reply to Dylan Baker from comment #2)
> I think Eric Engstrom sent a fix for this that's been reviewed but hasn't
> landed yet.
Indeed, I just pushed it:
commit 2117d0331020874c28bb66b0596467f960259eb
This allows drivers to be set by OS/arch in a sane manner.
Signed-off-by: Dylan Baker
---
meson.build | 37 +++--
meson_options.txt | 8
2 files changed, 39 insertions(+), 6 deletions(-)
diff --git a/meson.build b/meson.build
index 24d997b3e0a..43
https://bugs.freedesktop.org/show_bug.cgi?id=103496
--- Comment #2 from Dylan Baker ---
I think Eric Engstrom sent a fix for this that's been reviewed but hasn't
landed yet.
--
You are receiving this mail because:
You are the QA Contact for the bug.
You are the assignee for the bug.
On Mon, Oct 30, 2017 at 05:10:53PM +0100, Chema Casanova wrote:
> El 30/10/17 a las 07:44, Pohjolainen, Topi escribió:
> > On Sun, Oct 29, 2017 at 11:17:11PM +0100, Chema Casanova wrote:
> >> On 29/10/17 19:55, Pohjolainen, Topi wrote:
> >>> On Thu, Oct 12, 2017 at 08:38:08PM +0200, Jose Maria Casa
So I think the consensus is this is okay?
Emil, is the autotools right here?
Quoting Dylan Baker (2017-10-20 18:00:13)
> This very short series creates a new src/wsi folder, and moves wayland-drm
> into
> it. Basically wsi stuff is scattered about, and is needed by multiple
> components
> withi
https://bugs.freedesktop.org/show_bug.cgi?id=103496
--- Comment #1 from Brian Paul ---
Hi Vinson, can you re-test with ToT? The scons build is working for me,
testing at 134a40d2a67.
--
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You are the assignee for the bug.
You are the QA Contact for the bug.__
"Output Read Offset" is a bit non-sensical, let's just make this match
"Output Length".
Signed-off-by: Lionel Landwerlin
---
src/intel/genxml/gen10.xml| 6 +++---
src/intel/genxml/gen8.xml | 6 +++---
src/intel/genxml/gen9.xml | 6 +++--
Signed-off-by: Lionel Landwerlin
---
src/intel/common/gen_decoder.c | 7 ---
src/intel/common/gen_decoder.h | 3 ++-
2 files changed, 6 insertions(+), 4 deletions(-)
diff --git a/src/intel/common/gen_decoder.c b/src/intel/common/gen_decoder.c
index 050926f5642..94e7e15399f 100644
--- a/src/i
Signed-off-by: Lionel Landwerlin
---
src/intel/genxml/gen10.xml | 8
src/intel/genxml/gen4.xml | 2 +-
src/intel/genxml/gen45.xml | 2 +-
src/intel/genxml/gen5.xml | 2 +-
src/intel/genxml/gen6.xml | 2 +-
src/intel/genxml/gen7.xml
Signed-off-by: Lionel Landwerlin
---
src/intel/tools/disasm.c | 34 ++
src/intel/tools/gen_disasm.h | 2 ++
2 files changed, 36 insertions(+)
diff --git a/src/intel/tools/disasm.c b/src/intel/tools/disasm.c
index e2f5c11f6f5..c038949d9ec 100644
--- a/src/inte
Signed-off-by: Lionel Landwerlin
---
src/intel/common/gen_decoder.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/src/intel/common/gen_decoder.h b/src/intel/common/gen_decoder.h
index 658dd7f7b09..81b5beb5baf 100644
--- a/src/intel/common/gen_decoder.h
+++ b/src/intel/common/gen_decoder.h
On Mon, Oct 30, 2017 at 12:43 PM, Andres Gomez wrote:
> On Mon, 2017-10-30 at 11:39 -0400, Ilia Mirkin wrote:
>> On Mon, Oct 30, 2017 at 11:29 AM, Emil Velikov
>> wrote:
>> > On 28 October 2017 at 21:35, Andres Gomez wrote:
>> > > On Fri, 2017-10-27 at 14:14 -0400, Ilia Mirkin wrote:
>> > > > O
Signed-off-by: Lionel Landwerlin
---
src/intel/common/gen_decoder.c | 8
src/intel/common/gen_decoder.h | 3 ++-
2 files changed, 10 insertions(+), 1 deletion(-)
diff --git a/src/intel/common/gen_decoder.c b/src/intel/common/gen_decoder.c
index b0bd161fef3..1d57d350855 100644
--- a/src/
Another step into decoupling memory access from pointers.
Signed-off-by: Lionel Landwerlin
---
src/intel/common/gen_decoder.c| 4 ++--
src/intel/common/gen_decoder.h| 2 +-
src/intel/tools/aubinator.c | 2 +-
src/intel/tools/aubinator_error_decod
Signed-off-by: Lionel Landwerlin
---
src/intel/common/gen_decoder.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/src/intel/common/gen_decoder.c b/src/intel/common/gen_decoder.c
index 94e7e15399f..91076e901fe 100644
--- a/src/intel/common/gen_decoder.c
+++ b/src/intel/
Signed-off-by: Lionel Landwerlin
---
src/intel/common/gen_decoder.c | 37 +
src/intel/common/gen_decoder.h | 14 ++
2 files changed, 51 insertions(+)
diff --git a/src/intel/common/gen_decoder.c b/src/intel/common/gen_decoder.c
index 1d57d350855..bd
We want to introduce a reader interface for accessing memory, so that
later on we can use different ways of storing the content of the GTT
address space that don't involve a pointer to a linear buffer.
Signed-off-by: Lionel Landwerlin
---
src/intel/common/gen_decoder.c| 75 ++
Due to the new way we handle fields, we need *not* to forget the first
field when decoding instructions. The issue was that the advance
function was called first and skipped the first field.
Signed-off-by: Lionel Landwerlin
---
src/intel/common/gen_decoder.c | 31 +--
This is required to have output redirected to something else than a
file descriptor (stdout).
Signed-off-by: Lionel Landwerlin
---
src/intel/compiler/brw_compile_clip.c | 5 +-
src/intel/compiler/brw_compile_sf.c | 5 +-
src/intel/compiler/brw_disasm.c | 645 +
This is a first step in not accessing the dwords through pointers.
Signed-off-by: Lionel Landwerlin
---
src/intel/common/gen_decoder.c| 27 +--
src/intel/common/gen_decoder.h| 2 +-
src/intel/tools/aubinator.c | 4 ++--
Signed-off-by: Lionel Landwerlin
---
src/intel/common/gen_decoder.c | 7 +++
src/intel/common/gen_decoder.h | 1 +
2 files changed, 8 insertions(+)
diff --git a/src/intel/common/gen_decoder.c b/src/intel/common/gen_decoder.c
index cd18580aea8..2562aa56175 100644
--- a/src/intel/common/gen_de
Signed-off-by: Lionel Landwerlin
---
src/intel/common/gen_decoder.c | 59 ++
1 file changed, 37 insertions(+), 22 deletions(-)
diff --git a/src/intel/common/gen_decoder.c b/src/intel/common/gen_decoder.c
index a63c09cd37e..b0bd161fef3 100644
--- a/src/inte
We would like to avoid collisions with variables named field.
Signed-off-by: Lionel Landwerlin
---
src/intel/common/gen_decoder.c | 36 ++--
1 file changed, 18 insertions(+), 18 deletions(-)
diff --git a/src/intel/common/gen_decoder.c b/src/intel/common/gen_decod
Signed-off-by: Lionel Landwerlin
---
src/intel/common/gen_decoder.h | 9 +
src/intel/common/gen_device_info.h | 8
src/intel/tools/gen_disasm.h | 8
3 files changed, 25 insertions(+)
diff --git a/src/intel/common/gen_decoder.h b/src/intel/common/gen_decoder.h
Signed-off-by: Lionel Landwerlin
---
src/intel/common/gen_decoder.c | 4
1 file changed, 4 deletions(-)
diff --git a/src/intel/common/gen_decoder.c b/src/intel/common/gen_decoder.c
index 0bf705fa9e1..6a6a1f0aca4 100644
--- a/src/intel/common/gen_decoder.c
+++ b/src/intel/common/gen_decoder.
Signed-off-by: Lionel Landwerlin
---
src/intel/common/gen_decoder.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/src/intel/common/gen_decoder.c b/src/intel/common/gen_decoder.c
index 2562aa56175..050926f5642 100644
--- a/src/intel/common/gen_decoder.c
+++ b/src/intel/common/gen_decoder.c
If we have more programs than what we can store,
aubinator_error_decode will assert. Instead let's have a rolling
window of programs.
v2: Fix overflowing issues (Eric Engestrom)
Signed-off-by: Lionel Landwerlin
Reviewed-by: Eric Engestrom
---
src/intel/tools/aubinator_error_decode.c | 24 +
This makes use of ralloc to simplify the destruction. We can also
store instructions in hash tables.
Signed-off-by: Lionel Landwerlin
---
src/intel/common/gen_decoder.c | 176 +++--
src/intel/common/gen_decoder.h | 15 ++--
2 files changed, 90 insertions(+),
Signed-off-by: Lionel Landwerlin
---
src/intel/common/gen_decoder.c | 19 ---
1 file changed, 8 insertions(+), 11 deletions(-)
diff --git a/src/intel/common/gen_decoder.c b/src/intel/common/gen_decoder.c
index 6a6a1f0aca4..cd18580aea8 100644
--- a/src/intel/common/gen_decoder.c
+
Signed-off-by: Lionel Landwerlin
---
src/intel/tools/aubinator.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/src/intel/tools/aubinator.c b/src/intel/tools/aubinator.c
index 48d4456cc16..2c4eaab1701 100644
--- a/src/intel/tools/aubinator.c
+++ b/src/intel/tools/aubin
These fields are of little importance as they're used to recognize
instructions.
Signed-off-by: Lionel Landwerlin
---
src/intel/common/gen_decoder.c | 6 +++---
src/intel/common/gen_decoder.h | 1 +
2 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/src/intel/common/gen_decoder.c b/s
Making the next change more readable.
Signed-off-by: Lionel Landwerlin
---
src/intel/common/gen_decoder.c | 28 ++--
1 file changed, 14 insertions(+), 14 deletions(-)
diff --git a/src/intel/common/gen_decoder.c b/src/intel/common/gen_decoder.c
index 040201541ff..ef39c1c1
For example, we were skipping Dword 3 in this PIPE_CONTROL :
0x000ce130: 0x7a04: PIPE_CONTROL
DWord Length: 4
0x000ce134: 0x0010 : Dword 1
Flush LLC: false
Destination Address Type: 0 (PPGTT)
LRI Post Sync Operation: 0 (No LRI Operation)
Store Data Index: 0
Comma
The xml files don't always have fields in order. This might confuse
our parsing of the commands. Let's have the fields in order. To do
this, the easiest way it to use a linked list. It also helps a bit
with the iterator.
Signed-off-by: Lionel Landwerlin
---
src/intel/common/gen_decoder.c | 52 ++
Signed-off-by: Lionel Landwerlin
---
src/intel/common/gen_decoder.c | 13 -
src/intel/common/gen_decoder.h | 13 +
2 files changed, 13 insertions(+), 13 deletions(-)
diff --git a/src/intel/common/gen_decoder.c b/src/intel/common/gen_decoder.c
index 85880143f00..395ff02908
We used to print invalid data when the last field was being clamped to
32bits due to Dword Length of the whole instruction. Here is an
example where the decoder read part of the next instruction instead of
stopping at the 32bit limit:
0x000ce0b4: 0x1002: MI_STORE_DATA_IMM
0x000ce0b4: 0x1000
Hi all,
This is a proposal for a tool to help debug intel driver through
aubdumps. Having gone through implementing (& mostly debugging) the
ycbcr extension for anv, I wished I had a better tool than the text
output of aubinator.
This is the current state of about 1 & 1/2 month of experimenting w
Signed-off-by: Lionel Landwerlin
---
src/intel/common/gen_decoder.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/intel/common/gen_decoder.c b/src/intel/common/gen_decoder.c
index 395ff02908a..55e7305117c 100644
--- a/src/intel/common/gen_decoder.c
+++ b/src/intel/common
This should be inside the function that actually decodes fields.
Signed-off-by: Lionel Landwerlin
---
src/intel/common/gen_decoder.c | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/src/intel/common/gen_decoder.c b/src/intel/common/gen_decoder.c
index ef39c1c14db..833
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