Signed-off-by: Lionel Landwerlin <lionel.g.landwer...@intel.com>
---
src/intel/genxml/gen10.xml | 8 ++++----
src/intel/genxml/gen4.xml | 2 +-
src/intel/genxml/gen45.xml | 2 +-
src/intel/genxml/gen5.xml | 2 +-
src/intel/genxml/gen6.xml | 2 +-
src/intel/genxml/gen7.xml | 4 ++--
src/intel/genxml/gen75.xml | 8 ++++----
src/intel/genxml/gen8.xml | 8 ++++----
src/intel/genxml/gen9.xml | 8 ++++----
src/intel/vulkan/genX_cmd_buffer.c | 6 +++---
src/intel/vulkan/genX_gpu_memcpy.c | 4 ++--
src/intel/vulkan/genX_query.c | 20 ++++++++++----------
12 files changed, 37 insertions(+), 37 deletions(-)
diff --git a/src/intel/genxml/gen10.xml b/src/intel/genxml/gen10.xml
index bb33526e6dc..5bb46f819a8 100644
--- a/src/intel/genxml/gen10.xml
+++ b/src/intel/genxml/gen10.xml
@@ -3195,7 +3195,7 @@
<field name="Use Global GTT" start="22" end="22" type="bool"/>
<field name="Async Mode Enable" start="21" end="21" type="bool"/>
<field name="DWord Length" start="0" end="7" type="uint" default="2"/>
- <field name="Register Address" start="34" end="54" type="offset"/>
+ <field name="Register Offset" start="34" end="54" type="offset"/>
<field name="Memory Address" start="66" end="127" type="address"/>
</instruction>
@@ -3203,8 +3203,8 @@
<field name="Command Type" start="29" end="31" type="uint" default="0"/>
<field name="MI Command Opcode" start="23" end="28" type="uint"
default="42"/>
<field name="DWord Length" start="0" end="7" type="uint" default="1"/>
- <field name="Source Register Address" start="34" end="54" type="offset"/>
- <field name="Destination Register Address" start="66" end="86"
type="offset"/>
+ <field name="Source Register Offset" start="34" end="54" type="offset"/>
+ <field name="Destination Register Offset" start="66" end="86"
type="offset"/>
</instruction>
<instruction name="MI_LOAD_SCAN_LINES_EXCL" bias="2" length="2">
@@ -3405,7 +3405,7 @@
<field name="Use Global GTT" start="22" end="22" type="bool"/>
<field name="Predicate Enable" start="21" end="21" type="bool"/>
<field name="DWord Length" start="0" end="7" type="uint" default="2"/>
- <field name="Register Address" start="34" end="54" type="offset"/>
+ <field name="Register Offset" start="34" end="54" type="offset"/>
<field name="Memory Address" start="66" end="127" type="address"/>
</instruction>
diff --git a/src/intel/genxml/gen4.xml b/src/intel/genxml/gen4.xml
index fc24329535d..6345b75c48f 100644
--- a/src/intel/genxml/gen4.xml
+++ b/src/intel/genxml/gen4.xml
@@ -1100,7 +1100,7 @@
<field name="Use Global GTT" start="22" end="22" type="bool"/>
<field name="DWord Length" start="0" end="7" type="uint" default="1"/>
<field name="Physical Start Address Extension" start="60" end="63"
type="address"/>
- <field name="Register Address" start="34" end="54" type="offset"/>
+ <field name="Register Offset" start="34" end="54" type="offset"/>
<field name="Memory Address" start="66" end="95" type="address"/>
</instruction>
diff --git a/src/intel/genxml/gen45.xml b/src/intel/genxml/gen45.xml
index c91085831ea..dd9ca262030 100644
--- a/src/intel/genxml/gen45.xml
+++ b/src/intel/genxml/gen45.xml
@@ -1130,7 +1130,7 @@
<field name="Use Global GTT" start="22" end="22" type="bool"/>
<field name="DWord Length" start="0" end="7" type="uint" default="1"/>
<field name="Physical Start Address Extension" start="60" end="63"
type="address"/>
- <field name="Register Address" start="34" end="54" type="offset"/>
+ <field name="Register Offset" start="34" end="54" type="offset"/>
<field name="Memory Address" start="66" end="95" type="address"/>
</instruction>
diff --git a/src/intel/genxml/gen5.xml b/src/intel/genxml/gen5.xml
index 93e687a32bd..4c822df67f8 100644
--- a/src/intel/genxml/gen5.xml
+++ b/src/intel/genxml/gen5.xml
@@ -1216,7 +1216,7 @@
<field name="MI Command Opcode" start="23" end="28" type="uint"
default="36"/>
<field name="Use Global GTT" start="22" end="22" type="bool"/>
<field name="DWord Length" start="0" end="7" type="uint" default="1"/>
- <field name="Register Address" start="34" end="57" type="offset"/>
+ <field name="Register Offset" start="34" end="57" type="offset"/>
<field name="Memory Address" start="66" end="95" type="address"/>
</instruction>
diff --git a/src/intel/genxml/gen6.xml b/src/intel/genxml/gen6.xml
index 0707a33cd2a..317529b4065 100644
--- a/src/intel/genxml/gen6.xml
+++ b/src/intel/genxml/gen6.xml
@@ -1833,7 +1833,7 @@
<field name="MI Command Opcode" start="23" end="28" type="uint"
default="36"/>
<field name="Use Global GTT" start="22" end="22" type="bool"/>
<field name="DWord Length" start="0" end="7" type="uint" default="1"/>
- <field name="Register Address" start="34" end="54" type="offset"/>
+ <field name="Register Offset" start="34" end="54" type="offset"/>
<field name="Memory Address" start="66" end="95" type="address"/>
</instruction>
diff --git a/src/intel/genxml/gen7.xml b/src/intel/genxml/gen7.xml
index bda3b82e718..09d45818c3a 100644
--- a/src/intel/genxml/gen7.xml
+++ b/src/intel/genxml/gen7.xml
@@ -2254,7 +2254,7 @@
<field name="Use Global GTT" start="22" end="22" type="bool"/>
<field name="Async Mode Enable" start="21" end="21" type="bool"/>
<field name="DWord Length" start="0" end="7" type="uint" default="1"/>
- <field name="Register Address" start="34" end="54" type="offset"/>
+ <field name="Register Offset" start="34" end="54" type="offset"/>
<field name="Memory Address" start="66" end="95" type="address"/>
</instruction>
@@ -2347,7 +2347,7 @@
<field name="MI Command Opcode" start="23" end="28" type="uint"
default="36"/>
<field name="Use Global GTT" start="22" end="22" type="bool"/>
<field name="DWord Length" start="0" end="7" type="uint" default="1"/>
- <field name="Register Address" start="34" end="54" type="offset"/>
+ <field name="Register Offset" start="34" end="54" type="offset"/>
<field name="Memory Address" start="66" end="95" type="address"/>
</instruction>
diff --git a/src/intel/genxml/gen75.xml b/src/intel/genxml/gen75.xml
index b6aa9c55031..0bd1ce6ace6 100644
--- a/src/intel/genxml/gen75.xml
+++ b/src/intel/genxml/gen75.xml
@@ -2614,7 +2614,7 @@
<field name="Use Global GTT" start="22" end="22" type="bool"/>
<field name="Async Mode Enable" start="21" end="21" type="bool"/>
<field name="DWord Length" start="0" end="7" type="uint" default="1"/>
- <field name="Register Address" start="34" end="54" type="offset"/>
+ <field name="Register Offset" start="34" end="54" type="offset"/>
<field name="Memory Address" start="66" end="95" type="address"/>
</instruction>
@@ -2622,8 +2622,8 @@
<field name="Command Type" start="29" end="31" type="uint" default="0"/>
<field name="MI Command Opcode" start="23" end="28" type="uint"
default="42"/>
<field name="DWord Length" start="0" end="7" type="uint" default="1"/>
- <field name="Source Register Address" start="34" end="54" type="offset"/>
- <field name="Destination Register Address" start="66" end="86"
type="offset"/>
+ <field name="Source Register Offset" start="34" end="54" type="offset"/>
+ <field name="Destination Register Offset" start="66" end="86"
type="offset"/>
</instruction>
<instruction name="MI_LOAD_SCAN_LINES_EXCL" bias="2" length="2">
@@ -2796,7 +2796,7 @@
<field name="Use Global GTT" start="22" end="22" type="bool"/>
<field name="Predicate Enable" start="21" end="21" type="bool"/>
<field name="DWord Length" start="0" end="7" type="uint" default="1"/>
- <field name="Register Address" start="34" end="54" type="offset"/>
+ <field name="Register Offset" start="34" end="54" type="offset"/>
<field name="Memory Address" start="66" end="95" type="address"/>
</instruction>
diff --git a/src/intel/genxml/gen8.xml b/src/intel/genxml/gen8.xml
index 9f0fa48ce66..7ccb8046796 100644
--- a/src/intel/genxml/gen8.xml
+++ b/src/intel/genxml/gen8.xml
@@ -2835,7 +2835,7 @@
<field name="Use Global GTT" start="22" end="22" type="bool"/>
<field name="Async Mode Enable" start="21" end="21" type="bool"/>
<field name="DWord Length" start="0" end="7" type="uint" default="2"/>
- <field name="Register Address" start="34" end="54" type="offset"/>
+ <field name="Register Offset" start="34" end="54" type="offset"/>
<field name="Memory Address" start="66" end="127" type="address"/>
</instruction>
@@ -2843,8 +2843,8 @@
<field name="Command Type" start="29" end="31" type="uint" default="0"/>
<field name="MI Command Opcode" start="23" end="28" type="uint"
default="42"/>
<field name="DWord Length" start="0" end="7" type="uint" default="1"/>
- <field name="Source Register Address" start="34" end="54" type="offset"/>
- <field name="Destination Register Address" start="66" end="86"
type="offset"/>
+ <field name="Source Register Offset" start="34" end="54" type="offset"/>
+ <field name="Destination Register Offset" start="66" end="86"
type="offset"/>
</instruction>
<instruction name="MI_LOAD_SCAN_LINES_EXCL" bias="2" length="2">
@@ -3056,7 +3056,7 @@
<field name="Use Global GTT" start="22" end="22" type="bool"/>
<field name="Predicate Enable" start="21" end="21" type="bool"/>
<field name="DWord Length" start="0" end="7" type="uint" default="2"/>
- <field name="Register Address" start="34" end="54" type="offset"/>
+ <field name="Register Offset" start="34" end="54" type="offset"/>
<field name="Memory Address" start="66" end="127" type="address"/>
</instruction>
diff --git a/src/intel/genxml/gen9.xml b/src/intel/genxml/gen9.xml
index 0e2dddeacfb..db4b608f61f 100644
--- a/src/intel/genxml/gen9.xml
+++ b/src/intel/genxml/gen9.xml
@@ -3120,7 +3120,7 @@
<field name="Use Global GTT" start="22" end="22" type="bool"/>
<field name="Async Mode Enable" start="21" end="21" type="bool"/>
<field name="DWord Length" start="0" end="7" type="uint" default="2"/>
- <field name="Register Address" start="34" end="54" type="offset"/>
+ <field name="Register Offset" start="34" end="54" type="offset"/>
<field name="Memory Address" start="66" end="127" type="address"/>
</instruction>
@@ -3128,8 +3128,8 @@
<field name="Command Type" start="29" end="31" type="uint" default="0"/>
<field name="MI Command Opcode" start="23" end="28" type="uint"
default="42"/>
<field name="DWord Length" start="0" end="7" type="uint" default="1"/>
- <field name="Source Register Address" start="34" end="54" type="offset"/>
- <field name="Destination Register Address" start="66" end="86"
type="offset"/>
+ <field name="Source Register Offset" start="34" end="54" type="offset"/>
+ <field name="Destination Register Offset" start="66" end="86"
type="offset"/>
</instruction>
<instruction name="MI_LOAD_SCAN_LINES_EXCL" bias="2" length="2">
@@ -3341,7 +3341,7 @@
<field name="Use Global GTT" start="22" end="22" type="bool"/>
<field name="Predicate Enable" start="21" end="21" type="bool"/>
<field name="DWord Length" start="0" end="7" type="uint" default="2"/>
- <field name="Register Address" start="34" end="54" type="offset"/>
+ <field name="Register Offset" start="34" end="54" type="offset"/>
<field name="Memory Address" start="66" end="127" type="address"/>
</instruction>
diff --git a/src/intel/vulkan/genX_cmd_buffer.c
b/src/intel/vulkan/genX_cmd_buffer.c
index 20a885c4381..fd395ff3077 100644
--- a/src/intel/vulkan/genX_cmd_buffer.c
+++ b/src/intel/vulkan/genX_cmd_buffer.c
@@ -37,7 +37,7 @@ emit_lrm(struct anv_batch *batch,
uint32_t reg, struct anv_bo *bo, uint32_t offset)
{
anv_batch_emit(batch, GENX(MI_LOAD_REGISTER_MEM), lrm) {
- lrm.RegisterAddress = reg;
+ lrm.RegisterOffset = reg;
lrm.MemoryAddress = (struct anv_address) { bo, offset };
}
}
@@ -56,8 +56,8 @@ static void
emit_lrr(struct anv_batch *batch, uint32_t dst, uint32_t src)
{
anv_batch_emit(batch, GENX(MI_LOAD_REGISTER_REG), lrr) {
- lrr.SourceRegisterAddress = src;
- lrr.DestinationRegisterAddress = dst;
+ lrr.SourceRegisterOffset = src;
+ lrr.DestinationRegisterOffset = dst;
}
}
#endif
diff --git a/src/intel/vulkan/genX_gpu_memcpy.c
b/src/intel/vulkan/genX_gpu_memcpy.c
index 5b00b314f6f..0ef2fec53a3 100644
--- a/src/intel/vulkan/genX_gpu_memcpy.c
+++ b/src/intel/vulkan/genX_gpu_memcpy.c
@@ -78,11 +78,11 @@ genX(cmd_buffer_mi_memcpy)(struct anv_cmd_buffer
*cmd_buffer,
*/
#define TEMP_REG 0x2440 /* GEN7_3DPRIM_BASE_VERTEX */
anv_batch_emit(&cmd_buffer->batch, GENX(MI_LOAD_REGISTER_MEM), load) {
- load.RegisterAddress = TEMP_REG;
+ load.RegisterOffset = TEMP_REG;
load.MemoryAddress = src_addr;
}
anv_batch_emit(&cmd_buffer->batch, GENX(MI_STORE_REGISTER_MEM), store) {
- store.RegisterAddress = TEMP_REG;
+ store.RegisterOffset = TEMP_REG;
store.MemoryAddress = dst_addr;
}
#undef TEMP_REG
diff --git a/src/intel/vulkan/genX_query.c b/src/intel/vulkan/genX_query.c
index 7683d0d1e31..e28bae5c6b8 100644
--- a/src/intel/vulkan/genX_query.c
+++ b/src/intel/vulkan/genX_query.c
@@ -367,11 +367,11 @@ emit_pipeline_stat(struct anv_cmd_buffer *cmd_buffer,
uint32_t stat,
uint32_t reg = vk_pipeline_stat_to_reg[stat];
anv_batch_emit(&cmd_buffer->batch, GENX(MI_STORE_REGISTER_MEM), lrm) {
- lrm.RegisterAddress = reg,
+ lrm.RegisterOffset = reg,
lrm.MemoryAddress = (struct anv_address) { bo, offset };
}
anv_batch_emit(&cmd_buffer->batch, GENX(MI_STORE_REGISTER_MEM), lrm) {
- lrm.RegisterAddress = reg + 4,
+ lrm.RegisterOffset = reg + 4,
lrm.MemoryAddress = (struct anv_address) { bo, offset + 4 };
}
}
@@ -481,11 +481,11 @@ void genX(CmdWriteTimestamp)(
switch (pipelineStage) {
case VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT:
anv_batch_emit(&cmd_buffer->batch, GENX(MI_STORE_REGISTER_MEM), srm) {
- srm.RegisterAddress = TIMESTAMP;
+ srm.RegisterOffset = TIMESTAMP;
srm.MemoryAddress = (struct anv_address) { &pool->bo, offset + 8 };
}
anv_batch_emit(&cmd_buffer->batch, GENX(MI_STORE_REGISTER_MEM), srm) {
- srm.RegisterAddress = TIMESTAMP + 4;
+ srm.RegisterOffset = TIMESTAMP + 4;
srm.MemoryAddress = (struct anv_address) { &pool->bo, offset + 12
};
}
break;
@@ -530,11 +530,11 @@ emit_load_alu_reg_u64(struct anv_batch *batch, uint32_t
reg,
struct anv_bo *bo, uint32_t offset)
{
anv_batch_emit(batch, GENX(MI_LOAD_REGISTER_MEM), lrm) {
- lrm.RegisterAddress = reg,
+ lrm.RegisterOffset = reg,
lrm.MemoryAddress = (struct anv_address) { bo, offset };
}
anv_batch_emit(batch, GENX(MI_LOAD_REGISTER_MEM), lrm) {
- lrm.RegisterAddress = reg + 4;
+ lrm.RegisterOffset = reg + 4;
lrm.MemoryAddress = (struct anv_address) { bo, offset + 4 };
}
}
@@ -559,8 +559,8 @@ static void
emit_load_alu_reg_reg32(struct anv_batch *batch, uint32_t src, uint32_t dst)
{
anv_batch_emit(batch, GENX(MI_LOAD_REGISTER_REG), lrr) {
- lrr.SourceRegisterAddress = src;
- lrr.DestinationRegisterAddress = dst;
+ lrr.SourceRegisterOffset = src;
+ lrr.DestinationRegisterOffset = dst;
}
}
@@ -645,7 +645,7 @@ gpu_write_query_result(struct anv_batch *batch,
dst_offset += value_index * 4;
anv_batch_emit(batch, GENX(MI_STORE_REGISTER_MEM), srm) {
- srm.RegisterAddress = reg;
+ srm.RegisterOffset = reg;
srm.MemoryAddress = (struct anv_address) {
.bo = dst_buffer->bo,
.offset = dst_buffer->offset + dst_offset,
@@ -654,7 +654,7 @@ gpu_write_query_result(struct anv_batch *batch,
if (flags & VK_QUERY_RESULT_64_BIT) {
anv_batch_emit(batch, GENX(MI_STORE_REGISTER_MEM), srm) {
- srm.RegisterAddress = reg + 4;
+ srm.RegisterOffset = reg + 4;
srm.MemoryAddress = (struct anv_address) {
.bo = dst_buffer->bo,
.offset = dst_buffer->offset + dst_offset + 4,
--
2.15.0.rc2
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