On Sat, Aug 26, 2017 at 02:21:44AM -0400, Matt Turner wrote:
> Kind of a stupid false-positive as far as Coverity goes, but
>
> Reviewed-by: Matt Turner
Yeah, I had mixed feelings writing the patch. Thanks!
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Kind of a stupid false-positive as far as Coverity goes, but
Reviewed-by: Matt Turner
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Makes coverity happier.
CC: Matt Turner
CID: 1416799
Fixes: c1ac1a3d25 (i965: Add a brw_hw_type_to_reg_type() function)
Signed-off-by: Topi Pohjolainen
---
src/intel/compiler/brw_reg_type.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/intel/compiler/brw_reg_type.
On Fri, Aug 25, 2017 at 8:59 PM, Matt Turner wrote:
> Both are
>
> Reviewed-by: Matt Turner
>
> (Typo in the title of this patch)
>
> Should 2/2 go to stable? I'm not really sure how that code gets used.
>
Probably wouldn't hurt. Doing a quick grep for the function, I don't see
anywhere that i
Both are
Reviewed-by: Matt Turner
(Typo in the title of this patch)
Should 2/2 go to stable? I'm not really sure how that code gets used.
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Brave man,
with the little 'squash! st/glsl_to_tgsi: inline src_register into
translate_src' on top of your series, both issues are _solved_.
So you have my
Tested-by: Dieter Nützel
for the series.
BTW
Running this together with:
Prehash-all-the-things.mbox (Thomas Helland)
mesa-st-glsl_to
A couple of the cases were backwards
---
src/compiler/nir/nir.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/src/compiler/nir/nir.c b/src/compiler/nir/nir.c
index e9e0489..afd4d1a 100644
--- a/src/compiler/nir/nir.c
+++ b/src/compiler/nir/nir.c
@@ -1992,10 +1992,10 @
Somehow tabs got in there...
---
src/compiler/nir/nir.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/src/compiler/nir/nir.c b/src/compiler/nir/nir.c
index 841b7f4..e9e0489 100644
--- a/src/compiler/nir/nir.c
+++ b/src/compiler/nir/nir.c
@@ -1928,15 +1928,15 @@ nir
https://bugs.freedesktop.org/show_bug.cgi?id=102377
Brian Paul changed:
What|Removed |Added
Resolution|--- |FIXED
Status|NEW
Ack. Not a review though.
On August 25, 2017 6:38:46 PM Emil Velikov wrote:
From: Emil Velikov
The functionality is used by glsl and mesa. With the latter already
depending on the former.
With this in place the src/util/ static library libmesautil.la no longer
has a C++ dependency. Thus o
On Sat, Aug 26, 2017 at 3:07 AM, Eric Anholt wrote:
> Qiang Yu writes:
>
>> Hi Eric,
>>
>> I'm working on lima gp compiler which should benefit from nir lowering
>> uniform load to scalar.
>> I notice you write the nir_lower_io_to_scalar.c which support lowering
>> shader_in/shader_out
>> but lef
From: Emil Velikov
The functionality is used by glsl and mesa. With the latter already
depending on the former.
With this in place the src/util/ static library libmesautil.la no longer
has a C++ dependency. Thus objects which use it (like libEGL) don't need
the C++ link.
Cc: Jason Ekstrand
Sug
On Fri, Aug 25, 2017 at 8:23 PM, Karol Herbst wrote:
> On Sat, Aug 26, 2017 at 1:38 AM, Ilia Mirkin wrote:
>> On Fri, Aug 25, 2017 at 7:37 PM, Karol Herbst wrote:
>>> On Sat, Aug 26, 2017 at 1:30 AM, Ilia Mirkin wrote:
Why is this necessary? If data is not initialized, then presumably
The documentation says it applies only to Gens 8 and 9.
---
src/intel/compiler/brw_fs_generator.cpp | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/intel/compiler/brw_fs_generator.cpp
b/src/intel/compiler/brw_fs_generator.cpp
index 03ee26ccd4..07fd6307f0 100644
--- a/src/intel/compiler/br
---
src/intel/compiler/brw_eu_defines.h | 35 +++
1 file changed, 35 insertions(+)
diff --git a/src/intel/compiler/brw_eu_defines.h
b/src/intel/compiler/brw_eu_defines.h
index da482b73c5..3af55e830c 100644
--- a/src/intel/compiler/brw_eu_defines.h
+++ b/src/intel/
---
src/intel/compiler/brw_disasm.c | 399 +---
src/intel/compiler/brw_eu_defines.h | 11 -
2 files changed, 322 insertions(+), 88 deletions(-)
diff --git a/src/intel/compiler/brw_disasm.c b/src/intel/compiler/brw_disasm.c
index 3726172e5d..7215735967 100644
-
---
src/intel/compiler/brw_inst.h | 114 ++
1 file changed, 114 insertions(+)
diff --git a/src/intel/compiler/brw_inst.h b/src/intel/compiler/brw_inst.h
index e6169057e3..b9c03fa88f 100644
--- a/src/intel/compiler/brw_inst.h
+++ b/src/intel/compiler/brw_ins
Align1 mode offers some nice features over align16, like access to more
data types and the ability to use a 16-bit immediate. This patch does
not start using any new features. It just emits ternary instructions in
align1 mode.
---
src/intel/compiler/brw_fs_generator.cpp | 12
1 file c
Put hw_ in the name so that it's clear these are the hardware encodings.
Similar to commit 9fb832332868 ("i965: Rename brw_inst's functions that
access the register type")
---
src/intel/compiler/brw_disasm.c | 16
src/intel/compiler/brw_eu_emit.c | 16
src/intel
---
src/intel/compiler/brw_reg_type.c | 50 +++
src/intel/compiler/brw_reg_type.h | 8 +++
2 files changed, 58 insertions(+)
diff --git a/src/intel/compiler/brw_reg_type.c
b/src/intel/compiler/brw_reg_type.c
index a0f674f0d7..d65ebaee48 100644
--- a/src/i
---
src/intel/compiler/brw_eu_emit.c | 196 ---
1 file changed, 143 insertions(+), 53 deletions(-)
diff --git a/src/intel/compiler/brw_eu_emit.c b/src/intel/compiler/brw_eu_emit.c
index f1a2283de8..7f3980f83e 100644
--- a/src/intel/compiler/brw_eu_emit.c
+++ b/
Cannonlake (Gen10) adds align1 access mode to ternary instructions. In align1
mode, instructions can use more (and mixed) datatypes and a single 16-bit
immediate value. This series adds the infrastructure to emit and disassemble
such instructions. Patch 12 switches ternary instructions to align1 mo
The instruction word contains SubRegNum[4:2] so it's in units of dwords
(hence the * 4 to get it in terms of bytes). Before this patch, the
subreg would have been wrong for DF arguments.
---
src/intel/compiler/brw_disasm.c | 31 ++-
1 file changed, 26 insertions(+), 5 d
---
src/intel/compiler/brw_disasm.c | 46 +++
src/intel/compiler/brw_eu_compact.c | 30 -
src/intel/compiler/brw_eu_emit.c| 46 +++
src/intel/compiler/brw_inst.h | 54 ++---
4
---
src/intel/compiler/brw_disasm.c | 12 ---
src/intel/compiler/brw_inst.h | 4 +--
src/intel/compiler/brw_reg_type.c | 76 ---
src/intel/compiler/brw_reg_type.h | 7 ++--
4 files changed, 79 insertions(+), 20 deletions(-)
diff --git a/src/intel/co
---
src/intel/compiler/brw_eu_emit.c | 22 ++
src/intel/compiler/brw_inst.h| 21 +
2 files changed, 23 insertions(+), 20 deletions(-)
diff --git a/src/intel/compiler/brw_eu_emit.c b/src/intel/compiler/brw_eu_emit.c
index e4fcbe908d..f1a2283de8 100644
--
I'm going to call this from brw_inst.h, and I don't want to have to
include all of brw_reg.h.
---
src/intel/compiler/brw_reg.h | 13 -
src/intel/compiler/brw_reg_type.h | 15 +++
2 files changed, 15 insertions(+), 13 deletions(-)
diff --git a/src/intel/compiler/brw_re
On 25 August 2017 at 23:25, Jason Ekstrand wrote:
> On Fri, Aug 25, 2017 at 1:20 PM, Emil Velikov
> wrote:
>>
>> From: Emil Velikov
>>
>> Originally required for the u_vector implementation, which was inlined
>> in u_vector.h with previous commit.
>>
>> Using libmesautil pulled the C++ runtime (
On Sat, Aug 26, 2017 at 1:38 AM, Ilia Mirkin wrote:
> On Fri, Aug 25, 2017 at 7:37 PM, Karol Herbst wrote:
>> On Sat, Aug 26, 2017 at 1:30 AM, Ilia Mirkin wrote:
>>> Why is this necessary? If data is not initialized, then presumably
>>> pipe->get_query_result will have returned false.
>>>
>>
>>
https://bugs.freedesktop.org/show_bug.cgi?id=102377
--- Comment #4 from Bruce Cherniak ---
The proposed patch looks good. Regressions with the 4BYTE_ALIGNED_ONLY caps
set are fixed.
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On Fri, Aug 25, 2017 at 7:37 PM, Karol Herbst wrote:
> On Sat, Aug 26, 2017 at 1:30 AM, Ilia Mirkin wrote:
>> Why is this necessary? If data is not initialized, then presumably
>> pipe->get_query_result will have returned false.
>>
>
> but it didn't. It might be the drivers fault (in my case nouv
Why is this necessary? If data is not initialized, then presumably
pipe->get_query_result will have returned false.
On Fri, Aug 25, 2017 at 7:15 PM, Karol Herbst wrote:
> otherwise the result might contain random data.
>
> fixes on nvc0:
> * KHR-GL45.pipeline_statistics_query_tests_ARB.functiona
otherwise the result might contain random data.
fixes on nvc0:
* KHR-GL45.pipeline_statistics_query_tests_ARB.functional_default_qo_values
*
KHR-GL45.pipeline_statistics_query_tests_ARB.functional_non_rendering_commands_do_not_affect_queries
Signed-off-by: Karol Herbst
Cc: mesa-sta...@lists.f
On 26/08/17 00:50, Nicolai Hähnle wrote:
On 25.08.2017 13:58, Marek Olšák wrote:
Nicolai,
Have you thought about switching to NIR for radeonsi completely to get
16-bit support? We need NIR support anyway for spirv, right? Would be
it be easier than adding 16-bit support into TGSI, glsl2tgsi
On Fri, Aug 25, 2017 at 1:20 PM, Emil Velikov
wrote:
> From: Emil Velikov
>
> Originally required for the u_vector implementation, which was inlined
> in u_vector.h with previous commit.
>
> Using libmesautil pulled the C++ runtime (string_to_uint_map.cpp),
> which is something don't want to imp
On August 25, 2017 12:14:20 PM Eric Anholt wrote:
Qiang Yu writes:
Hi Eric,
I'm working on lima gp compiler which should benefit from nir lowering
uniform load to scalar.
I notice you write the nir_lower_io_to_scalar.c which support lowering
shader_in/shader_out
but left the uniform lowerin
Hello list,
The candidate for the Mesa 17.1.8 is now available. Currently we have:
- 15 queued
- 0 nominated (outstanding)
- and 2 rejected patches
In the current queue we have:
In Mesa Core we include a fix to prevent a crash in
glCompressedTextureSubImage3D.
The GLSL compiler now includes
Leo Liu wrote:
+ }
Should we bail out with an error here when it's the other
way around?
Although I cannot think of any of case that to get buffer
Interlaced now, It's still a good idea to bail out here
when it happnens Will add it in v4.
It's not a error when case like buffer is de
On Fri, 2017-08-25 at 14:41 +0100, Emil Velikov wrote:
> Should we drop the "if (n != -1 && n < sizeof(buf))" part as well with
> this patch?
Meh. I've got some other changes coming in the area so that'll probably
happen soon anyway. At least for this change I just wanted to make
things determini
If we merge a mapping with the mapping before it, we also need
to not only change the offset, but also the bo offset.
Fixes: 715df30a4e2 "radv/amdgpu: Add winsys implementation of virtual buffers."
---
src/amd/vulkan/winsys/amdgpu/radv_amdgpu_bo.c | 1 +
1 file changed, 1 insertion(+)
diff --git
From: Emil Velikov
Originally required for the u_vector implementation, which was inlined
in u_vector.h with previous commit.
Using libmesautil pulled the C++ runtime (string_to_uint_map.cpp),
which is something don't want to impose in our libEGL.
We could consider rewriting string_to_uint_map
From: Emil Velikov
Inlining the implementation does not cause additional overhead in
terms of build time while the binary is increased only marginally (~1k)
At the same time the compiler should be able to optimise better, although
this is not a path where we'll notice much difference.
Use a loc
+ }
Should we bail out with an error here when it's the other way
around?
Although I cannot think of any of case that to get buffer
Interlaced now, It's still a good idea to bail out here when it
happnens
Will add it in v4.
It's not a error when case like buffer is deinterlaced, an
Leo Liu wrote:
On 08/25/2017 03:16 PM, Christian König wrote:
Am 25.08.2017 um 17:15 schrieb Leo Liu:
On 08/25/2017 10:53 AM, Leo Liu wrote:
On 08/25/2017 02:57 AM, Christian König wrote:
Am 24.08.2017 um 20:49 schrieb Leo Liu:
v2: use deinterlace common function
v3: make sure deinterl
From: Brian Paul
For software drivers where we want "fake" msaa support for GL 3.x, we
treat 1 sample as being msaa.
For drivers with real msaa support, start format probing at 2x msaa.
For drivers with fake msaa support, start format probing at 1x msaa.
This also tweaks the MaxSamples code in
Accompanying patch "st/mesa: only try to create 1x msaa surfaces for
'fake' msaa" requires driver to report max_samples=1 to enable "fake"
msaa. Previously, 0 and 1 were treated equivalently in st_init_extensions()
and either could enable "fake" msaa.
This patch raises the swr default msaa_max_cou
On 08/25/2017 03:16 PM, Christian König wrote:
Am 25.08.2017 um 17:15 schrieb Leo Liu:
On 08/25/2017 10:53 AM, Leo Liu wrote:
On 08/25/2017 02:57 AM, Christian König wrote:
Am 24.08.2017 um 20:49 schrieb Leo Liu:
v2: use deinterlace common function
v3: make sure deinterlace only
Signed
On Fri, Aug 25, 2017 at 8:42 PM, Marek Olšák wrote:
> On Tue, Aug 22, 2017 at 2:15 PM, Nicolai Hähnle wrote:
>> On 22.08.2017 14:10, Nicolai Hähnle wrote:
>>>
>>> On 22.08.2017 13:00, Marek Olšák wrote:
On Tue, Aug 22, 2017 at 9:37 AM, Nicolai Hähnle
wrote:
>
> On 18.08.20
Am 25.08.2017 um 17:15 schrieb Leo Liu:
On 08/25/2017 10:53 AM, Leo Liu wrote:
On 08/25/2017 02:57 AM, Christian König wrote:
Am 24.08.2017 um 20:49 schrieb Leo Liu:
v2: use deinterlace common function
v3: make sure deinterlace only
Signed-off-by: Leo Liu
---
src/gallium/state_trackers
https://bugs.freedesktop.org/show_bug.cgi?id=102017
--- Comment #17 from Thomas Jollans ---
Thanks everyone for looking into this. I can confirm that the issue was a
missing libtxc_dxtn for me too.
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Qiang Yu writes:
> Hi Eric,
>
> I'm working on lima gp compiler which should benefit from nir lowering
> uniform load to scalar.
> I notice you write the nir_lower_io_to_scalar.c which support lowering
> shader_in/shader_out
> but left the uniform lowering in vc4 driver, any reason why not
> impl
In order to implement VK_KHR_external_fence, we need to back our fences
with something that's shareable. Since the kernel wait interface for
sync objects already supports waiting for multiple fences in one go, it
makes anv_WaitForFences much simpler if we only have one type of fence.
---
src/inte
---
src/intel/vulkan/anv_wsi.c | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/src/intel/vulkan/anv_wsi.c b/src/intel/vulkan/anv_wsi.c
index 9369f26..00edb22 100644
--- a/src/intel/vulkan/anv_wsi.c
+++ b/src/intel/vulkan/anv_wsi.c
@@ -364,22 +364,25 @@ VkResult anv_Get
---
src/intel/vulkan/anv_batch_chain.c | 19 -
src/intel/vulkan/anv_extensions.py | 5 ++
src/intel/vulkan/anv_queue.c | 142 -
3 files changed, 161 insertions(+), 5 deletions(-)
diff --git a/src/intel/vulkan/anv_batch_chain.c
b/src/intel/vulkan/a
---
src/intel/vulkan/anv_gem.c | 4 ++--
src/intel/vulkan/anv_gem_stubs.c | 2 +-
src/intel/vulkan/anv_private.h | 2 +-
src/intel/vulkan/anv_queue.c | 2 +-
4 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/src/intel/vulkan/anv_gem.c b/src/intel/vulkan/anv_gem.c
index 57a
---
src/vulkan/util/vk_alloc.h | 14 ++
1 file changed, 14 insertions(+)
diff --git a/src/vulkan/util/vk_alloc.h b/src/vulkan/util/vk_alloc.h
index 2915021..f58a806 100644
--- a/src/vulkan/util/vk_alloc.h
+++ b/src/vulkan/util/vk_alloc.h
@@ -37,6 +37,20 @@ vk_alloc(const VkAllocationC
This commit changes fences to work a bit more like BO semaphores.
Instead of the fence being a batch, it's simply a BO that gets added
to the validation list for the last execbuf call in the QueueSubmit
operation. It's a bit annoying finding the last submit in the execbuf
but this allows us to avo
This is just a refactor, similar to what we did for semaphores, in
preparation for handling VK_KHR_external_fence.
---
src/intel/vulkan/anv_batch_chain.c | 22 --
src/intel/vulkan/anv_private.h | 42 ++-
src/intel/vulkan/anv_queue.c | 144 ++-
---
src/intel/vulkan/anv_gem.c | 28 +
src/intel/vulkan/anv_gem_stubs.c | 13 ++
src/intel/vulkan/anv_private.h | 4 +++
src/intel/vulkan/anv_queue.c | 53 +++-
4 files changed, 87 insertions(+), 11 deletions(-)
diff --g
---
src/intel/vulkan/anv_gem.c | 62
src/intel/vulkan/anv_gem_stubs.c | 20 +
src/intel/vulkan/anv_private.h | 5
3 files changed, 87 insertions(+)
diff --git a/src/intel/vulkan/anv_gem.c b/src/intel/vulkan/anv_gem.c
index 9bd37f4
This adds the DRM_SYNCOBJ_CREATE_SIGNALED flag as well as the ioctls:
- DRM_IOCTL_SYNCOBJ_WAIT
- DRM_IOCTL_SYNCOBJ_RESET
- DRM_IOCTL_SYNCOBJ_SIGNAL
---
include/drm-uapi/drm.h | 22 ++
1 file changed, 22 insertions(+)
diff --git a/include/drm-uapi/drm.h b/include/drm-uapi/d
It only applies to legacy BO fences.
---
src/intel/vulkan/anv_batch_chain.c | 2 +-
src/intel/vulkan/anv_private.h | 10 +-
src/intel/vulkan/anv_queue.c | 24
3 files changed, 18 insertions(+), 18 deletions(-)
diff --git a/src/intel/vulkan/anv_batch_cha
We didn't allow them before because it didn't look like the spec allowed
it. It certainly doesn't make much sense. However, there are CTS tests
that apparently hit this. What the spec actually says is:
"Importing a payload using handle types with copy transference
creates a duplicate co
https://bugs.freedesktop.org/show_bug.cgi?id=102038
--- Comment #17 from Brad King ---
After applying the two patches I can confirm that the VTK test I used to
produce the apitrace now passes again. Thanks!
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Alejandro Piñeiro writes:
> On 24/08/17 21:07, Connor Abbott wrote:
>>
>> Hi Alejandro,
>
> Hi Connor,
>
>>
>> This seems really suspicious. If the live ranges are really
>> independent, then the register allocator should be able to assign the
>> two virtual registers to the same physical registe
On Tue, Aug 22, 2017 at 2:15 PM, Nicolai Hähnle wrote:
> On 22.08.2017 14:10, Nicolai Hähnle wrote:
>>
>> On 22.08.2017 13:00, Marek Olšák wrote:
>>>
>>> On Tue, Aug 22, 2017 at 9:37 AM, Nicolai Hähnle
>>> wrote:
On 18.08.2017 19:06, Marek Olšák wrote:
>
>
> Ping.
>
Alejandro Piñeiro writes:
> Although it is possible to emit them directly as AND/OR on brw_fs_nir,
> having specific opcodes makes it easier to remove duplicate settings
> later.
>
> Signed-off-by: Alejandro Piñeiro
> Signed-off-by: Jose Maria Casanova Crespo
> ---
> src/intel/compiler/brw_e
Signed-off-by: Leo Liu
---
src/gallium/drivers/radeon/radeon_uvd.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/src/gallium/drivers/radeon/radeon_uvd.c
b/src/gallium/drivers/radeon/radeon_uvd.c
index 228f654af1..00d6267018 100644
--- a/src/gallium/drivers/radeon/radeon_uvd.c
Signed-off-by: Leo Liu
---
src/gallium/drivers/radeon/radeon_uvd.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/gallium/drivers/radeon/radeon_uvd.c
b/src/gallium/drivers/radeon/radeon_uvd.c
index 648a493b59..228f654af1 100644
--- a/src/gallium/drivers/radeon/radeon_uvd
Am 24.08.2017 um 20:40 schrieb Adam Jackson:
> The only difference from the EXT version is bumping the minmax to 16, so
> just hit all the drivers at once.
>
> v2: Fix driver names, add to 17.3 release notes (Ilia Mirkin)
>
> Reviewed-by: Ilia Mirkin
> Signed-off-by: Adam Jackson
> ---
> docs/
On 08/25/2017 12:42 PM, Andy Furniss wrote:
Leo Liu wrote:
v2: use deinterlace common function
v3: make sure deinterlace only
Doesn't apply to master with git.
I will attach you another one. should be good. Too much patches on the fly.
Thanks,
Leo
patch was less fussy
patch -p 1 < ~
On Thu, 2017-08-24 at 23:27 -0700, Kenneth Graunke wrote:
> > diff --git a/src/glx/glxextensions.h b/src/glx/glxextensions.h
> > index 21ad02a44b..2a595516ee 100644
> > --- a/src/glx/glxextensions.h
> > +++ b/src/glx/glxextensions.h
> > @@ -101,6 +101,7 @@ enum
> > GL_ARB_texture_env_combine_b
Leo Liu wrote:
v2: use deinterlace common function
v3: make sure deinterlace only
Doesn't apply to master with git.
patch was less fussy
patch -p 1 < ~/Leo-va-interl-patches/02-3
patching file src/gallium/state_trackers/va/picture.c
Hunk #1 succeeded at 619 with fuzz 1 (offset 6 lines).
Hunk
On Aug 25, 2017 4:10 PM, "Matt Turner" wrote:
On Fri, Aug 25, 2017 at 10:50 AM, Nicolai Hähnle wrote:
> On 25.08.2017 13:58, Marek Olšák wrote:
>>
>> Nicolai,
>>
>> Have you thought about switching to NIR for radeonsi completely to get
>> 16-bit support? We need NIR support anyway for spirv, rig
On 25 August 2017 at 12:40, Andres Gomez wrote:
> Completed the 17.2 cycle and added the beginning of the 17.3 one.
>
> Cc: Emil Velikov
> Cc: Juan A. Suarez Romero
> Signed-off-by: Andres Gomez
> ---
> docs/release-calendar.html | 86
> ++
> 1 file
Reviewed-by: Emil Velikov
Thanks
Emil
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On 24 August 2017 at 15:22, Eric Engestrom wrote:
> On Thursday, 2017-08-24 08:54:04 -0500, Rob Herring wrote:
>> On Thu, Aug 24, 2017 at 7:49 AM, Eric Engestrom
>> wrote:
>> > Khronos: https://github.com/KhronosGroup/EGL-Registry/pull/22
>> > Cc: Rob Herring
>> > Cc: Emil Velikov
>> > Signed-o
Reviewed-by: Emil Velikov
-Emil
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This structure contains two fields, binding and index, that store the
binding in the descriptor set and the index inside the binding.
These structures are defined as uint8_t, but the types in Vulkan
specification are uint32_t, so big values are clamp.
This fixes
dEQP-VK.binding_model.shader_acce
On Fri, 2017-08-25 at 09:08 +0300, Tapani Pälli wrote:
> On 08/24/2017 01:12 PM, Juan A. Suarez Romero wrote:
> > This structure contains two fields, binding and index, that store
> > the
> > binding in the descriptor set and the index inside the binding.
> >
> > These structures are defined as ui
On 08/25/2017 10:53 AM, Leo Liu wrote:
On 08/25/2017 02:57 AM, Christian König wrote:
Am 24.08.2017 um 20:49 schrieb Leo Liu:
v2: use deinterlace common function
v3: make sure deinterlace only
Signed-off-by: Leo Liu
---
src/gallium/state_trackers/va/picture.c | 22 --
On Fri, Aug 25, 2017 at 10:50 AM, Nicolai Hähnle wrote:
> On 25.08.2017 13:58, Marek Olšák wrote:
>>
>> Nicolai,
>>
>> Have you thought about switching to NIR for radeonsi completely to get
>> 16-bit support? We need NIR support anyway for spirv, right? Would be it be
>> easier than adding 16-bit
On 08/24/2017 02:48 PM, Leo Liu wrote:
On 08/24/2017 11:34 AM, Christian König wrote:
Am 24.08.2017 um 17:11 schrieb Leo Liu:
Signed-off-by: Leo Liu
Reviewed-by: Christian König for the series.
Andy do you want to test this? Should make VA-API transcoding simpler
to use.
Just got ch
When reallocation for encoder
v2: use deinterlace common function
v3: make sure deinterlace only
v4: bail out when reallocation for interlaced buffer
Signed-off-by: Leo Liu
---
src/gallium/state_trackers/va/picture.c | 25 -
1 file changed, 20 insertions(+), 5 deletions
On 08/25/2017 02:57 AM, Christian König wrote:
Am 24.08.2017 um 20:49 schrieb Leo Liu:
v2: use deinterlace common function
v3: make sure deinterlace only
Signed-off-by: Leo Liu
---
src/gallium/state_trackers/va/picture.c | 22 --
1 file changed, 16 insertions(+), 6 del
On 25.08.2017 13:58, Marek Olšák wrote:
Nicolai,
Have you thought about switching to NIR for radeonsi completely to get
16-bit support? We need NIR support anyway for spirv, right? Would be it
be easier than adding 16-bit support into TGSI, glsl2tgsi, and tgsi2llvm?
Well. What's missing from
From: Nicolai Hähnle
The result written by the shader workaround needs to be written back, or
the CP may read stale data.
Fixes: 78476cfe071a ("radeonsi: enable ARB_transform_feedback_overflow_query")
---
src/gallium/drivers/radeon/r600_pipe_common.h | 5 +
src/gallium/drivers/radeon/r600_q
From: Nicolai Hähnle
The data is read when the render_cond_atom is emitted, so we must
delay emitting the atom until after the flush.
Fixes: 0fe0320dc074 ("radeonsi: use optimal packet order when doing a pipeline
sync")
---
src/gallium/drivers/radeon/r600_pipe_common.h | 3 ++-
src/gallium/dr
From: Nicolai Hähnle
Fixes: 420c438589c8 ("radeonsi: log draw and compute state into log context")
---
src/gallium/drivers/radeonsi/si_debug.c | 17 +++--
1 file changed, 11 insertions(+), 6 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_debug.c
b/src/gallium/drivers/rad
v2: - store record_result in radv_CmdBeginRenderPass()
Signed-off-by: Samuel Pitoiset
---
src/amd/vulkan/radv_cmd_buffer.c | 24 +---
1 file changed, 17 insertions(+), 7 deletions(-)
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index 21e2d
Signed-off-by: Samuel Pitoiset
---
src/amd/vulkan/radv_cmd_buffer.c | 23 ---
1 file changed, 16 insertions(+), 7 deletions(-)
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index 21e2dfd9f7..cc9aeafefa 100644
--- a/src/amd/vulkan/radv_cmd_bu
This will allow to propagate VK_ERROR_OUT_OF_HOST_MEMORY to
vkEndCommandBuffer() when necessary.
Signed-off-by: Samuel Pitoiset
---
src/amd/vulkan/radv_cmd_buffer.c | 16
src/amd/vulkan/radv_private.h| 2 +-
2 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/src
From: Marek Olšák
The discard range codepath takes precedence, so if we get both
unsynchronized and discard_range, choose unsynchronized.
---
src/gallium/auxiliary/util/u_threaded_context.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/src/gallium/auxiliary/util/u_thread
From: Marek Olšák
---
src/gallium/auxiliary/util/u_threaded_context.c | 4 ++--
src/gallium/auxiliary/util/u_threaded_context.h | 4 ++--
src/gallium/drivers/radeon/r600_buffer_common.c | 2 +-
3 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/src/gallium/auxiliary/util/u_threaded_c
On 24 August 2017 at 19:52, Adam Jackson wrote:
> The snprintf stuff here already constructs the right name for the device
> node, and if it doesn't, you configured Mesa wrong, don't do that.
>
I think the idea was that "snprintf can fail" even though in practise
it will never do.
In all fairness
Hi Lucas,
On Fri, Aug 25, 2017 at 4:57 AM, Lucas Stach wrote:
> There is no fix for this. The terrain shaders are simply too big to be
> executed on GC2000. (You remember that 512 instruction limit mentioned
> in the reference manual? That's it.)
>
> This demo runs fine on GC3000.
Thanks for th
Thanks Bas!
This fixes CTS
dEQP-VK.pipeline.vertex_input.max_attributes.32_attributes.binding_one_to_one.interleaved
Tested-by: Samuel Pitoiset
On 08/25/2017 02:15 PM, Bas Nieuwenhuizen wrote:
e.g. 0 + 32 <= 32 should be valid.
Fixes: f4e499ec791 "radv: add initial non-conformant radv vulk
On Friday, 2017-08-25 14:40:25 +0300, Andres Gomez wrote:
> Completed the 17.2 cycle and added the beginning of the 17.3 one.
>
> Cc: Emil Velikov
> Cc: Juan A. Suarez Romero
> Signed-off-by: Andres Gomez
> ---
> docs/release-calendar.html | 86
> ++
On Fri, 2017-08-25 at 14:40 +0300, Andres Gomez wrote:
> The first email updates the calendar with a proposal for the future
> releases until the end of 2017. It also removes versions that have
> already been released.
>
> The second patch is a proposal to add yet another final iteration to
> the
On Friday, 2017-08-25 13:39:05 +0200, Christian Gmeiner wrote:
> Found by code inspection.
>
> Fixes: c9e8b49b885 ("etnaviv: gallium driver for Vivante GPUs")
> Cc: mesa-sta...@lists.freedesktop.org
> Signed-off-by: Christian Gmeiner
Good catch!
Reviewed-by: Eric Engestrom
> ---
> src/gallium
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