Cannonlake (Gen10) adds align1 access mode to ternary instructions. In align1 mode, instructions can use more (and mixed) datatypes and a single 16-bit immediate value. This series adds the infrastructure to emit and disassemble such instructions. Patch 12 switches ternary instructions to align1 mode, but does not begin using any of the new features. I'm not sure if that's worth committing on its own.
i965: Move brw_reg_type_is_floating_point to brw_reg_type.h i965: Add functions for brw_reg_type <-> hw 3src type i965: Print subreg in units of type-size on ternary instructions i965: Rename brw_inst 3src functions in preparation for align1 i965: Rename brw_inst's functions that access the 3src register type i965: Add functions to abstract access to 3src register types i965: Add align1 ternary instruction field encodings i965: Add align1 ternary instruction support to conversion functions i965: Add align1 ternary instruction-word support i965: Add align1 ternary instruction disassembler support i965: Add align1 ternary instruction emission support i965/fs: Use align1 mode on ternary instructions on Gen10+ i965/fs: Don't apply POW/FDIV workaround on Gen10+ _______________________________________________ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
