Align1 mode offers some nice features over align16, like access to more data types and the ability to use a 16-bit immediate. This patch does not start using any new features. It just emits ternary instructions in align1 mode. --- src/intel/compiler/brw_fs_generator.cpp | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/src/intel/compiler/brw_fs_generator.cpp b/src/intel/compiler/brw_fs_generator.cpp index afaec5c949..03ee26ccd4 100644 --- a/src/intel/compiler/brw_fs_generator.cpp +++ b/src/intel/compiler/brw_fs_generator.cpp @@ -1728,14 +1728,16 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width) case BRW_OPCODE_MAD: assert(devinfo->gen >= 6); - brw_set_default_access_mode(p, BRW_ALIGN_16); + if (devinfo->gen < 10) + brw_set_default_access_mode(p, BRW_ALIGN_16); brw_MAD(p, dst, src[0], src[1], src[2]); break; case BRW_OPCODE_LRP: assert(devinfo->gen >= 6); brw_set_default_access_mode(p, BRW_ALIGN_16); - brw_LRP(p, dst, src[0], src[1], src[2]); + if (devinfo->gen < 10) + brw_LRP(p, dst, src[0], src[1], src[2]); break; case BRW_OPCODE_FRC: @@ -1834,7 +1836,8 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width) case BRW_OPCODE_BFE: assert(devinfo->gen >= 7); - brw_set_default_access_mode(p, BRW_ALIGN_16); + if (devinfo->gen < 10) + brw_set_default_access_mode(p, BRW_ALIGN_16); brw_BFE(p, dst, src[0], src[1], src[2]); break; @@ -1844,7 +1847,8 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width) break; case BRW_OPCODE_BFI2: assert(devinfo->gen >= 7); - brw_set_default_access_mode(p, BRW_ALIGN_16); + if (devinfo->gen < 10) + brw_set_default_access_mode(p, BRW_ALIGN_16); brw_BFI2(p, dst, src[0], src[1], src[2]); break; -- 2.13.5 _______________________________________________ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev