Re: [Mesa-dev] Exposing (or lack of) EGL device support on platforms lacking DRM devices (Was Re: [Piglit] [PATCH 1/2] egl: Add sanity test for EGL_EXT_device_query (v3))

Hi, On Wednesday, 7 September 2016 12:41:46 CEST Emil Velikov wrote: > On 6 September 2016 at 18:32, Mathias Fröhlich > wrote: > > >> * Systems with fb only, disabled render nodes and/or alike. > >> EGL implementations (in our case the libdrm API provides all the info > >> about available DRM d

Re: [Mesa-dev] [PATCH 01/57] i965/fs: Replace fs_reg::reg_offset with fs_reg::offset expressed in bytes.

On Wed, 2016-09-07 at 18:48 -0700, Francisco Jerez wrote: (...) > diff --git a/src/mesa/drivers/dri/i965/brw_shader.cpp > b/src/mesa/drivers/dri/i965/brw_shader.cpp > index ea39252..29435f6 100644 > --- a/src/mesa/drivers/dri/i965/brw_shader.cpp > +++ b/src/mesa/drivers/dri/i965/brw_shader.cpp > @@

Re: [Mesa-dev] [PATCH 4/4] radeonsi: unify si_set_optimal_micro_tile_mode call sites

For the series: Reviewed-by: Nicolai Hähnle On 07.09.2016 13:46, Marek Olšák wrote: From: Marek Olšák There is nothing special happening in those code blocks. --- src/gallium/drivers/radeon/r600_texture.c | 12 1 file changed, 4 insertions(+), 8 deletions(-) diff --git a/src/g

Re: [Mesa-dev] [PATCH] gallium: remove PIPE_BIND_TRANSFER_READ/WRITE

Reviewed-by: Nicolai Hähnle On 07.09.2016 21:37, Marek Olšák wrote: From: Marek Olšák not used in any useful way --- src/gallium/auxiliary/util/u_debug.c| 2 -- src/gallium/docs/source/screen.rst | 2 -- src/gallium/drivers/freedreno/a2xx/fd2_screen.c | 5

Re: [Mesa-dev] [PATCH] gallium: fix return value check

Thanks. With the int changed to off_t as remarked by others, and the then redundant (off_t) cast in the if-condition removed, this patch is Reviewed-by: Nicolai Hähnle On 07.09.2016 16:34, Martina Kollarova wrote: A possible error (-1) was being lost because it was first converted to an unsig

Re: [Mesa-dev] [PATCH] vl/dri3: handle the case of different GPU

On 08/09/16 01:13 PM, Nayan Deshmukh wrote: > On Thu, Sep 8, 2016 at 9:03 AM, Michel Dänzer > wrote: > On 08/09/16 02:48 AM, Nayan Deshmukh wrote: > > use a linear buffer in case of back buffer > > > > Signed-off-by: Nayan Deshmukh

[Mesa-dev] [PATCH] gm107/ir: allow indirect inputs to be loaded by frag shader

Looks like the GM107 IPA op does not allow a separate offset when using an indirect register. Instead generate an add when legalizing the SSA. (Ideally such lowering would be done earlier, but there are opt passes that might attempt to stuff an offset directly into such an access.) Signed-off-by:

Re: [Mesa-dev] [4.1/6] i965: Add sanity check for non-compressible texture views

On Wed, Sep 07, 2016 at 03:28:41PM -0700, Jason Ekstrand wrote: >On Sep 7, 2016 10:24 AM, "Topi Pohjolainen" ><[1]topi.pohjolai...@gmail.com> wrote: >> >> Signed-off-by: Topi Pohjolainen <[2]topi.pohjolai...@intel.com> >> --- >> src/mesa/drivers/dri/i965/brw_wm_surface_stat

Re: [Mesa-dev] [v3 4/6] i965/rbc: Consult rb settings for texture surface setup

On Wed, Sep 07, 2016 at 03:25:30PM -0700, Jason Ekstrand wrote: >On Sep 7, 2016 10:24 AM, "Topi Pohjolainen" ><[1]topi.pohjolai...@gmail.com> wrote: >> >> Once mcs buffer gets allocated without delay for lossless >> compression (same as we do for msaa), one gets regression in: >

Re: [Mesa-dev] [PATCH] vl/dri3: handle the case of different GPU

Hi Michel, Sorry for the bad patch. I'll fix the coding style in the next patch. On Thu, Sep 8, 2016 at 9:03 AM, Michel Dänzer wrote: > On 08/09/16 02:48 AM, Nayan Deshmukh wrote: > > use a linear buffer in case of back buffer > > > > Signed-off-by: Nayan Deshmukh > > [...] > > > @@ -226,8 +2

Re: [Mesa-dev] [PATCH 3/3] nir/spirv: Use fill_common_atomic_sources for image atomics

Hi Jason, Am 07.09.2016 um 00:17 schrieb Jason Ekstrand: > We had two almost identical copies of this code and they were both broken > but in different ways. The previous two commits fixed both of them. This > one just unifies them so that it's easier to handle in the future. > > Signed-off-by:

Re: [Mesa-dev] [PATCH] vl/dri3: handle the case of different GPU

On 08/09/16 02:48 AM, Nayan Deshmukh wrote: > use a linear buffer in case of back buffer > > Signed-off-by: Nayan Deshmukh [...] > @@ -226,8 +227,13 @@ dri3_alloc_back_buffer(struct vl_dri3_screen *scrn) >goto close_fd; > > memset(&templ, 0, sizeof(templ)); > + if (scrn->is_diff

[Mesa-dev] [PATCH] anv: Link to libX11-xcb only when unneeded

The Makefile unconditionally linked libX11-xcb into libvulkan_intel.so. But it's needed only if HAVE_PLATFORM_X11. Fixes build of libvulkan_intel.so on Chromium OS, which has no X11 libraries. Cc: Kevin Strasser Cc: Jason Ekstrand Change-Id: Ib42db7db582c4531cf13db65f2ad5d57db1d774d --- src/in

Re: [Mesa-dev] [PATCH 00/57] i965/ir: Switch representation of register offsets and sizes to byte units.

On Sep 7, 2016 6:51 PM, "Francisco Jerez" wrote: > > This series reworks the representation of register region offsets in > the i965 IR to be universally byte-based instead of the rather awkward > split between reg_offset and subreg_offset we have in the FS back-end > right now, or the reg_offset

Re: [Mesa-dev] [PATCH 3/4] radeonsi: add more unlikely() uses into si_draw_vbo

On 07/09/16 11:01 PM, Nicolai Hähnle wrote: > On 07.09.2016 12:23, Marek Olšák wrote: >> On Wed, Sep 7, 2016 at 11:47 AM, Michel Dänzer >> wrote: >>> On 07/09/16 06:02 PM, Marek Olšák wrote: Based on the comments so far, it looks like all annotations in the patch are very well place

[Mesa-dev] [PATCH 19/57] i965/fs: Don't consider LOAD_PAYLOAD with sub-GRF offset to behave like a raw copy.

This was likely the original intention, and at least register coalesce relies on it. --- src/mesa/drivers/dri/i965/brw_fs.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp index 51c0d55..f6a9ec1 1006

[Mesa-dev] [PATCH 36/57] i965/fs: Simplify a bunch of fs_inst::size_written calculations by using component_size().

Using component_size() is easier and generally more correct because it takes into account the register type and stride for you. --- src/mesa/drivers/dri/i965/brw_fs.cpp | 2 +- src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 28 -- .../drivers/dri/i965/brw_f

[Mesa-dev] [PATCH 52/57] i965/vec4: Assign correct destination offset to rewritten instruction in register coalesce.

Because the pass already checks that the destination offset of each 'scan_inst' that needs to be rewritten matches 'inst->src[0].offset' exactly, the final offset of the rewritten instruction is just the original destination offset of the copy. This is in preparation for adding support for sub-GRF

[Mesa-dev] [PATCH 07/57] i965/fs: Replace fs_inst::regs_written with ::size_written field in bytes.

The previous regs_written field can be recovered by rewriting each rvalue reference of regs_written like 'x = i.regs_written' to 'x = DIV_ROUND_UP(i.size_written, reg_unit)', and each lvalue reference like 'i.regs_written = x' to 'i.size_written = x * reg_unit'. For the same reason as in the previ

[Mesa-dev] [PATCH 54/57] i965/vec4: Fix copy propagation for non-register-aligned regions.

This prevents it from trying to propagate a copy through a register-misaligned region. MOV instructions with a misaligned destination shouldn't be treated as a direct GRF copy, because they only define the destination GRFs partially. Also fix the interference check implemented with is_channel_upd

[Mesa-dev] [PATCH 29/57] i965/fs: Fix bogus sub-MRF offset calculation in compute-to-mrf.

The 'scan_inst->dst.offset % REG_SIZE' term in the final 'scan_inst->dst.offset' calculation is obviously bogus. The offset from the start of the copy destination register 'inst->dst' where the destination of the generating instruction 'scan_inst' would be written to (before compute-to-mrf runs) i

[Mesa-dev] [PATCH 24/57] i965/fs: Drop fs_inst::overwrites_reg() in favor of regions_overlap().

fs_inst::overwrites_reg is rather easy to misuse because it cannot tell how large the register region starting at 'reg' is, so in cases where the destination region starts after 'reg' it may give a misleading result. regions_overlap() is somewhat more verbose to use but handles arbitrary overlap c

[Mesa-dev] [PATCH 51/57] i965/vec4: Don't coalesce registers with overlapping writes not matching the MOV source.

In preparation for adding support for sub-GRF offsets to the VEC4 IR. --- src/mesa/drivers/dri/i965/brw_vec4.cpp | 10 ++ 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_vec4.cpp b/src/mesa/drivers/dri/i965/brw_vec4.cpp index d9dbc4c..8f8d262 10

[Mesa-dev] [PATCH 49/57] i965/vec4: Check that the write offsets match when setting dependency controls.

For simplicity just assume that two writes to the same GRF with different sub-GRF offsets will potentially interfere and break the dependency control chain. This is in preparation for adding sub-GRF offset support to the VEC4 IR. --- src/mesa/drivers/dri/i965/brw_vec4.cpp | 2 ++ 1 file changed,

[Mesa-dev] [PATCH 44/57] i965/vec4: Print src/dst_reg::offset field consistently for all register files.

C.f. 'i965/fs: Print fs_reg::offset field consistently for all register files.'. --- src/mesa/drivers/dri/i965/brw_vec4.cpp | 21 +++-- 1 file changed, 15 insertions(+), 6 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_vec4.cpp b/src/mesa/drivers/dri/i965/brw_vec4.cpp in

[Mesa-dev] [PATCH 53/57] i965/vec4: Compare full register offsets in cmod propagation.

Cmod propagation would misoptimize the program if the destination offset of the generating instruction wasn't exactly the same as the source region offset of the copy instruction. In preparation for adding support for sub-GRF offsets to the VEC4 IR. --- src/mesa/drivers/dri/i965/brw_vec4_cmod_pro

[Mesa-dev] [PATCH 48/57] i965/vec4: Change opt_vector_float to keep track of the last offset seen in bytes.

This simplifies things slightly and makes the pass more correct in presence of sub-GRF offsets. --- src/mesa/drivers/dri/i965/brw_vec4.cpp | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_vec4.cpp b/src/mesa/drivers/dri/i965/brw_vec4.cpp inde

[Mesa-dev] [PATCH 31/57] i965/fs: Fix signedness of the return value of fs_inst::size_read().

--- src/mesa/drivers/dri/i965/brw_fs.cpp | 2 +- src/mesa/drivers/dri/i965/brw_ir_fs.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp index e033a65..c9d3d7d 100644 --- a/src/mesa/drivers/dri/i965/

[Mesa-dev] [PATCH 26/57] i965/vec4: Port regions_overlap() to the vec4 IR.

This is copy-pasted almost line by line from the FS back-end. The only reason it cannot be implemented in terms of backend_reg is that the backend_reg::nr field doesn't have the same meaning for uniforms on both back-ends. It could be easily deduplicated by using a template function. --- src/mes

[Mesa-dev] [PATCH 32/57] i965/fs: Simplify byte_offset().

In the most common case this can now be implemented as a simple addition because the offset is already encoded as a single scalar value in bytes. --- src/mesa/drivers/dri/i965/brw_ir_fs.h | 12 1 file changed, 4 insertions(+), 8 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw

[Mesa-dev] [PATCH 42/57] i965/fs: Misc simplification.

Get rid of some leftover redundant arithmetic introduced during the conversion to byte offsets and sizes that can be simplified easily. --- src/mesa/drivers/dri/i965/brw_fs_combine_constants.cpp | 2 +- src/mesa/drivers/dri/i965/brw_fs_nir.cpp| 2 +- src/mesa/drivers/dri/i965/brw_

[Mesa-dev] [PATCH 25/57] i965/fs: Stop using fs_reg::in_range() in favor of regions_overlap().

Its only use left in the FS back-end should be using regions_overlap() instead to avoid getting a false negative result in cases where source and destination overlap but the former starts before the latter in the VGRF file. --- src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 3 ++- 1 file changed, 2 in

[Mesa-dev] [PATCH 14/57] i965/fs: Handle arbitrary offsets in brw_reg_from_fs_reg for MRF/VGRF registers.

This restriction seemed rather artificial... Removing it actually simplifies things slightly. --- src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp b/src/mesa/drivers/dri/i965/brw

[Mesa-dev] [PATCH 35/57] i965/fs: Simplify result_live calculation in dead_code_eliminate().

No need to unroll the first iteration of the loop manually. --- src/mesa/drivers/dri/i965/brw_fs_dead_code_eliminate.cpp | 12 +++- 1 file changed, 3 insertions(+), 9 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_fs_dead_code_eliminate.cpp b/src/mesa/drivers/dri/i965/brw_fs_dea

[Mesa-dev] [PATCH 33/57] i965/fs: Simplify get_fpu_lowered_simd_width() by using inequalities instead of rounding.

--- src/mesa/drivers/dri/i965/brw_fs.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp index c9d3d7d..743929a 100644 --- a/src/mesa/drivers/dri/i965/brw_fs.cpp +++ b/src/mesa/drivers/dri/i965/brw

[Mesa-dev] [PATCH 41/57] i965/fs: Get rid of fs_inst::set_smear().

component() was generally a better alternative because of several issues set_smear() had: - It wouldn't take the original stride and offset of the register into account, which means that set_smear() on the result of e.g. another set_smear() call or an offset() call would give a bogus reg

[Mesa-dev] [PATCH 21/57] i965/fs: Compare full register offsets in cmod propagation pass.

This could potentially have misoptimized a program in cases where inst->src[0] had a non-zero sub-GRF offset. --- src/mesa/drivers/dri/i965/brw_fs_cmod_propagation.cpp | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_fs_cmod_propagation.cpp b/src

[Mesa-dev] [PATCH 39/57] i965/fs: Move region_contained_in to the IR header and fix for non-VGRF files.

Also changed the argument names since 'src' and 'dst' don't make that much sense outside of the context of copy propagation. --- src/mesa/drivers/dri/i965/brw_fs_copy_propagation.cpp | 14 -- src/mesa/drivers/dri/i965/brw_ir_fs.h | 13 + 2 files changed, 13

[Mesa-dev] [PATCH 30/57] i965/fs: Switch mask_relative_to() used in compute-to-mrf to byte units.

This makes the helper function less annoying to use and somewhat more accurate. --- src/mesa/drivers/dri/i965/brw_fs.cpp | 20 ++-- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp index 703

[Mesa-dev] [PATCH 08/57] i965/vec4: Replace vec4_instruction::regs_written with ::size_written field in bytes.

The previous regs_written field can be recovered by rewriting each rvalue reference of regs_written like 'x = i.regs_written' to 'x = DIV_ROUND_UP(i.size_written, reg_unit)', and each lvalue reference like 'i.regs_written = x' to 'i.size_written = x * reg_unit'. For the same reason as in the previ

[Mesa-dev] [PATCH 23/57] i965/fs: Fix LOAD_PAYLOAD handling in register coalesce is_nop_mov().

is_nop_mov() was broken for LOAD_PAYLOAD instructions in two ways: On the one hand the original destination register offset wasn't being taken into account which would give incorrect results if it was already non-zero, and on the other hand all source registers were being treated as if they had a s

[Mesa-dev] [PATCH 15/57] i965/fs: Handle fixed HW GRF subnr in reg_offset().

This will be useful later on when we start using reg_offset() on fixed hardware registers. --- src/mesa/drivers/dri/i965/brw_ir_fs.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/mesa/drivers/dri/i965/brw_ir_fs.h b/src/mesa/drivers/dri/i965/brw_ir_fs.h index 2e5c8e5..4

[Mesa-dev] [PATCH 06/57] i965/vec4: Add wrapper functions for vec4_instruction::regs_read and ::regs_written.

This is in preparation for dropping vec4_instruction::regs_read and ::regs_written in favor of more accurate alternatives expressed in byte units. The main reason these wrappers are useful is that a number of optimization passes implement dataflow analysis with register granularity, so these helpe

[Mesa-dev] [PATCH 46/57] i965/ir: Update several stale comments.

--- src/mesa/drivers/dri/i965/brw_defines.h| 2 +- src/mesa/drivers/dri/i965/brw_fs.cpp | 18 +++--- src/mesa/drivers/dri/i965/brw_fs_live_variables.cpp| 12 ++-- .../drivers/dri/i965/brw_schedule_instructions.cpp | 8 src/me

[Mesa-dev] [PATCH 56/57] i965/vec4: Assert that ATTR regions are register-aligned.

It might be useful to actually handle this once copy propagation becomes smarter about register-misaligned offsets. --- src/mesa/drivers/dri/i965/brw_vec4.cpp | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mesa/drivers/dri/i965/brw_vec4.cpp b/src/mesa/drivers/dri/i965/brw_vec4.cpp index

[Mesa-dev] [PATCH 28/57] i965/fs: Take into account copy register offset during compute-to-mrf.

This was dropping 'inst->dst.offset' on the floor. Nothing in the code above seems to guarantee that it's zero and in that case the offset of the register being coalesced into wouldn't be taken into account while rewriting the generating instruction. --- src/mesa/drivers/dri/i965/brw_fs.cpp | 2 +

[Mesa-dev] [PATCH 12/57] i965/fs: Return more accurate read size from fs_inst::size_read for IMM and UNIFORM files.

--- src/mesa/drivers/dri/i965/brw_fs.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp index 5979461..7473f07 100644 --- a/src/mesa/drivers/dri/i965/brw_fs.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs.

[Mesa-dev] [PATCH 18/57] i965/vec4: Take into account misalignment in regs_written() and regs_read().

Unlike the FS counterpart of this commit this was likely not (yet) a bug, but let's fix it already in preparation for implementing support for sub-GRF offsets in the VEC4 back-end. --- src/mesa/drivers/dri/i965/brw_ir_vec4.h | 10 ++ 1 file changed, 6 insertions(+), 4 deletions(-) diff --

[Mesa-dev] [PATCH 55/57] i965/vec4: Don't spill non-GRF-aligned register regions.

A better fix would be to do something along the lines of the FS back-end spilling code and emit a scratch read before any instruction that overwrites the register to spill partially due to a non-zero sub-register offset. In the meantime mark registers used with a non-zero sub-register offset as no

[Mesa-dev] [PATCH 57/57] i965/vec4: Assert that pull constant load offsets are 16B-aligned.

Non-16B-aligned pull constant loads are unlikely to be particularly useful given that you can get roughly the same effect by using swizzles on the result. --- src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mesa/drivers/dri/i965/brw_vec4_visit

[Mesa-dev] [PATCH 20/57] i965/fs: Don't consider LOAD_PAYLOAD with stride > 1 source to behave like a raw copy.

Noticed the problem by inspection while typing in the previous commit. --- src/mesa/drivers/dri/i965/brw_fs.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp index f6a9ec1..57a3494 100644 --- a/src/m

[Mesa-dev] [PATCH 27/57] i965/vec4: Drop backend_reg::in_range() in favor of regions_overlap().

This makes sure that overlap checks are done correctly throughout the back-end when the '*this' register starts before the register/size pair provided as argument, and is actually less annoying to use than in_range() at this point since regions_overlap() takes its size arguments in bytes. --- src/

[Mesa-dev] [PATCH 37/57] i965/fs: Simplify copy propagation LOAD_PAYLOAD ACP setup.

By keeping track of 'offset' in byte units. --- src/mesa/drivers/dri/i965/brw_fs_copy_propagation.cpp | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_fs_copy_propagation.cpp b/src/mesa/drivers/dri/i965/brw_fs_copy_propagation.cpp index bd534b

[Mesa-dev] [PATCH 45/57] i965/ir: Don't print ARF subnr values twice.

--- src/mesa/drivers/dri/i965/brw_fs.cpp | 4 src/mesa/drivers/dri/i965/brw_vec4.cpp | 4 2 files changed, 8 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp index a90aba0..6d4303c 100644 --- a/src/mesa/drivers/dri/i965/brw_fs.cpp

[Mesa-dev] [PATCH 40/57] i965/fs: Use region_contained_in() in compute-to-mrf coalescing pass.

--- src/mesa/drivers/dri/i965/brw_fs.cpp | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp index 1668ac0..df66dc7 100644 --- a/src/mesa/drivers/dri/i965/brw_fs.cpp +++ b/src/mesa/drivers/dri/i965/br

[Mesa-dev] [PATCH 09/57] i965/ir: Drop backend_instruction::regs_written field.

--- src/mesa/drivers/dri/i965/brw_shader.h | 1 - 1 file changed, 1 deletion(-) diff --git a/src/mesa/drivers/dri/i965/brw_shader.h b/src/mesa/drivers/dri/i965/brw_shader.h index 2173f32..0de0808 100644 --- a/src/mesa/drivers/dri/i965/brw_shader.h +++ b/src/mesa/drivers/dri/i965/brw_shader.h @@

[Mesa-dev] [PATCH 11/57] i965/vec4: Replace vec4_instruction::regs_read with ::size_read using byte units.

The previous regs_read value can be recovered by rewriting each reference of regs_read() like 'x = i.regs_read(j)' to 'x = DIV_ROUND_UP(i.size_read(j), reg_unit)'. For the same reason as in the previous patches, this doesn't attempt to be particularly clever about simplifying the result in the int

[Mesa-dev] [PATCH 05/57] i965/fs: Add wrapper functions for fs_inst::regs_read and ::regs_written.

This is in preparation for dropping fs_inst::regs_read and ::regs_written in favor of more accurate alternatives expressed in byte units. The main reason these wrappers are useful is that a number of optimization passes implement dataflow analysis with register granularity, so these helpers will c

[Mesa-dev] [PATCH 50/57] i965/vec4: Compare full register offsets in opt_register_coalesce nop move check.

In preparation for adding support for sub-GRF offsets to the VEC4 IR. --- src/mesa/drivers/dri/i965/brw_vec4.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mesa/drivers/dri/i965/brw_vec4.cpp b/src/mesa/drivers/dri/i965/brw_vec4.cpp index f97de18..d9dbc4c 100644 --- a/

[Mesa-dev] [PATCH 17/57] i965/fs: Take into account misalignment in regs_written() and regs_read().

There was a workaround for this in fs_inst::size_read() for the SHADER_OPCODE_MOV_INDIRECT instruction and FIXED_GRF register file *only*. We should take this possibility into account for the sources and destinations of all instructions on all optimization passes that need to quantize dataflow in

[Mesa-dev] [PATCH 47/57] i965/vec4: Simplify src/dst_reg to brw_reg conversion by using byte_offset().

This should also have the side effect of fixing convert_to_hw_regs() to handle sub-GRF register offsets. --- src/mesa/drivers/dri/i965/brw_vec4.cpp | 15 --- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_vec4.cpp b/src/mesa/drivers/dri/i96

[Mesa-dev] [PATCH 34/57] i965/fs: Simplify and fix buggy stride/offset calculations using subscript().

These were bashing the 'offset' and 'stride' values of several registers without taking the previous value into account, which probably didn't matter in practice for optimize_frontfacing_ternary() because the 'tmp' register already had a known region, but it would have given the wrong region as res

[Mesa-dev] [PATCH 03/57] i965/ir: Remove backend_reg::reg_offset.

--- src/mesa/drivers/dri/i965/brw_shader.cpp | 2 -- src/mesa/drivers/dri/i965/brw_shader.h | 15 ++- 2 files changed, 2 insertions(+), 15 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_shader.cpp b/src/mesa/drivers/dri/i965/brw_shader.cpp index 29435f6..e599235 100644 --

[Mesa-dev] [PATCH 10/57] i965/fs: Replace fs_inst::regs_read with ::size_read using byte units.

The previous regs_read value can be recovered by rewriting each reference of regs_read() like 'x = i.regs_read(j)' to 'x = DIV_ROUND_UP(i.size_read(j), reg_unit)'. For the same reason as in the previous patches, this doesn't attempt to be particularly clever about simplifying the result in the int

[Mesa-dev] [PATCH 43/57] i965/fs: Print fs_reg::offset field consistently for all register files.

The offset printing code in fs_visitor::dump_instruction() was doing things differently for sources and destinations and for each register file -- In some cases it would be added to the base register number fs_reg::nr, in other cases it would follow the base register separated with a plus sign, in

[Mesa-dev] [PATCH 13/57] i965/fs: Return more accurate read size for LINTERP from fs_inst::size_read.

The LINTERP virtual instruction only reads three scalar components from the first 16B of the second source, we can now teach size_read() about it since its return value is represented with byte granularity. --- src/mesa/drivers/dri/i965/brw_fs.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion

[Mesa-dev] [PATCH 22/57] i965/fs: Fix can_propagate_from() source/destination overlap check.

The previous overlap condition only made sure that the VGRF numbers or GRF-aligned offsets were different without taking the amount of data written and read by the instruction into consideration. Use the regions_overlap() helper instead. --- src/mesa/drivers/dri/i965/brw_fs_copy_propagation.cpp |

[Mesa-dev] [PATCH 16/57] i965/fs: Take into account trailing padding in regs_written() and regs_read().

This fixes regs_written() and regs_read() to return a more accurate value when the padding left between components due to a stride value greater than one causes the region bounds given by size_written or size_read to overflow into the next register. This could become a problem in optimization pass

[Mesa-dev] [PATCH 38/57] i965/fs: Change region_contained_in() to use byte units.

This makes the function less annoying to use and more accurate -- We shouldn't propagate a copy into a register region that wasn't fully contained in the destination of the copy (IOW, a source region that wasn't fully defined by the copy) just because the number of registers written and read by eac

[Mesa-dev] [PATCH 02/57] i965/vec4: Replace dst/src_reg::reg_offset with dst/src_reg::offset expressed in bytes.

The dst/src_reg::offset field in byte units introduced in the previous patch is a more straightforward alternative to an offset representation split between ::reg_offset and ::subreg_offset fields. The split representation makes it too easy to forget about one of the offsets while dealing with the

[Mesa-dev] [PATCH 01/57] i965/fs: Replace fs_reg::reg_offset with fs_reg::offset expressed in bytes.

The fs_reg::offset field in byte units introduced in this patch is a more straightforward alternative to the current register offset representation split between fs_reg::reg_offset and ::subreg_offset. The split representation makes it too easy to forget about one of the offsets while dealing with

[Mesa-dev] [PATCH 00/57] i965/ir: Switch representation of register offsets and sizes to byte units.

This series reworks the representation of register region offsets in the i965 IR to be universally byte-based instead of the rather awkward split between reg_offset and subreg_offset we have in the FS back-end right now, or the reg_offset field currently used in the VEC4 IR which doesn't allow bett

[Mesa-dev] [PATCH 04/57] i965/fs: Replace fs_reg::subreg_offset with fs_reg::offset expressed in bytes.

The fs_reg::subreg_offset and ::offset fields are now redundant, the sub-GRF offset can just be added to the single ::offset field expressed in byte units. The current subreg_offset value can be recovered by applying the following rule: Replace each rvalue reference of subreg_offset like 'x = r.su

Re: [Mesa-dev] [PATCH] gallium: remove PIPE_BIND_TRANSFER_READ/WRITE

Marek Olšák writes: > From: Marek Olšák > > not used in any useful way > diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c > b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c > index 0627f3d..77b38b5 100644 > --- a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c > +++ b/src/gallium/dri

Re: [Mesa-dev] [PATCH 07/12] anv/image: Memset hiz surfaces to 0 when binding memory

On Thu, Sep 01, 2016 at 04:12:23PM -0700, Jason Ekstrand wrote: > On Wed, Aug 31, 2016 at 8:29 PM, Nanley Chery wrote: > > > From: Jason Ekstrand > > > > Nanley Chery (amend): > > - Change memset value from 0xff to 0 (a defined value for HiZ). > > > > Signed-off-by: Nanley Chery > > --- > > s

[Mesa-dev] [PATCH] r300g: Set R300_VAP_CNTL on RSxxx to avoid triangle flickering

On the RSxxx chip series, HW TCL is missing and r300_emit_vs_state() is never called. However, if R300_VAP_CNTL is never set, the hardware (at least the RS690 I tested this on) comes up with rendering artifacts, and parts that are uploaded before this "fix" remain broken in VRAM. This causes artif

Re: [Mesa-dev] [PATCH 04/12] anv: Add func anv_image_has_hiz()

On Wed 07 Sep 2016, Nanley Chery wrote: > On Fri, Sep 02, 2016 at 11:42:24AM -0700, Chad Versace wrote: > > On Thu 01 Sep 2016, Jason Ekstrand wrote: > > > On Wed, Aug 31, 2016 at 8:29 PM, Nanley Chery > > > wrote: > > > > > > From: Chad Versace > > > > > > Nanley Chery (amend): > > >

Re: [Mesa-dev] [v3 3/6] i965: Track non-compressible sampling of renderbuffers

On Sep 7, 2016 10:24 AM, "Topi Pohjolainen" wrote: > > v3: >- Actually set the flags when needed instead of falsely > overwriting them (Jason). >- Use more generic name for flag (dropped RENDERBUFFER) >- Consult also shader images > > Signed-off-by: Topi Pohjolainen > --- > src/

Re: [Mesa-dev] [4.1/6] i965: Add sanity check for non-compressible texture views

On Sep 7, 2016 10:24 AM, "Topi Pohjolainen" wrote: > > Signed-off-by: Topi Pohjolainen > --- > src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 34 > 1 file changed, 34 insertions(+) > > diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/d

Re: [Mesa-dev] [v3 4/6] i965/rbc: Consult rb settings for texture surface setup

On Sep 7, 2016 10:24 AM, "Topi Pohjolainen" wrote: > > Once mcs buffer gets allocated without delay for lossless > compression (same as we do for msaa), one gets regression in: > > GL45-CTS.texture_barrier_ARB.same-texel-rw > > Setting the auxiliary surface for both sampling engine and data > port

Re: [Mesa-dev] [PATCH] EGL: Combine the GL and GLES current contexts (v2)

On Wed, 2016-09-07 at 22:07 +0100, Emil Velikov wrote: > Was going to mention this but it slipped through. Can we get a proper > spec quote in the code ? I guess the logic through eglCreateContext (the only place where the API difference matters) is a little contorted, certainly took me more than

[Mesa-dev] [PATCH] egl: Document why EGL_OPENGL{, _ES}_API are mostly identical

Signed-off-by: Adam Jackson --- src/egl/main/eglcontext.c | 10 ++ 1 file changed, 10 insertions(+) diff --git a/src/egl/main/eglcontext.c b/src/egl/main/eglcontext.c index ebc004d..057b60f 100644 --- a/src/egl/main/eglcontext.c +++ b/src/egl/main/eglcontext.c @@ -457,6 +457,16 @@ _eglPa

Re: [Mesa-dev] [PATCH] EGL: Combine the GL and GLES current contexts (v2)

On 7 September 2016 at 16:57, Adam Jackson wrote: > On Wed, 2016-09-07 at 11:15 -0400, Adam Jackson wrote: >> From: Kyle Brenneman >> >> Only keep track of a single current context, instead of separate >> contexts for GL and GLES. > > In addition to fixing 1.4+ compliance, this fixes the "eglterm

Re: [Mesa-dev] [PATCH 14/33] intel/blorp: Add an entrypoint for doing bit-for-bit copies

On Sep 7, 2016 10:45 AM, "Nanley Chery" wrote: > > On Wed, Sep 07, 2016 at 10:26:25AM -0700, Jason Ekstrand wrote: > > On Wed, Sep 7, 2016 at 9:50 AM, Jason Ekstrand wrote: > > > > > On Wed, Sep 7, 2016 at 9:36 AM, Nanley Chery > > > wrote: > > > > > >> On Tue, Sep 06, 2016 at 05:02:55PM -0700,

Re: [Mesa-dev] [PATCH 6/6] intel/isl: Add a detailed comment about multisampling with HiZ

On Sep 7, 2016 12:23 PM, "Chad Versace" wrote: > > On Fri 02 Sep 2016, Jason Ekstrand wrote: > > --- > > src/intel/isl/isl.c | 60 +++-- > > 1 file changed, 58 insertions(+), 2 deletions(-) > > > > diff --git a/src/intel/isl/isl.c b/src/intel/isl/is

Re: [Mesa-dev] [PATCH 0/6] intel/isl: A few cleanups for multisampled HiZ

On Sep 7, 2016 12:27 PM, "Nanley Chery" wrote: > > On Fri, Sep 02, 2016 at 03:50:41PM -0700, Jason Ekstrand wrote: > > This series does a few cleanups to ISL so that it can actually handle > > multisampled HiZ correctly. When Chad and I first discussed HiZ, we > > thought it would all work out ea

[Mesa-dev] [PATCH] gallium: remove PIPE_BIND_TRANSFER_READ/WRITE

From: Marek Olšák not used in any useful way --- src/gallium/auxiliary/util/u_debug.c| 2 -- src/gallium/docs/source/screen.rst | 2 -- src/gallium/drivers/freedreno/a2xx/fd2_screen.c | 5 - src/gallium/drivers/freedreno/a3xx/fd3_screen.c | 5 - s

Re: [Mesa-dev] [PATCH] EGL: Combine the GL and GLES current contexts (v2)

On Wed 07 Sep 2016, Adam Jackson wrote: > On Wed, 2016-09-07 at 11:15 -0400, Adam Jackson wrote: > > From: Kyle Brenneman > > > > Only keep track of a single current context, instead of separate > > contexts for GL and GLES. > > In addition to fixing 1.4+ compliance, this fixes the "eglterminate

Re: [Mesa-dev] [PATCH 0/6] intel/isl: A few cleanups for multisampled HiZ

On Fri, Sep 02, 2016 at 03:50:41PM -0700, Jason Ekstrand wrote: > This series does a few cleanups to ISL so that it can actually handle > multisampled HiZ correctly. When Chad and I first discussed HiZ, we > thought it would all work out easy as ISL already had all the required > code. We were co

Re: [Mesa-dev] [PATCH 6/6] intel/isl: Add a detailed comment about multisampling with HiZ

On Fri 02 Sep 2016, Jason Ekstrand wrote: > --- > src/intel/isl/isl.c | 60 > +++-- > 1 file changed, 58 insertions(+), 2 deletions(-) > > diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c > index 33e83b1..cb9eb23 100644 > --- a/src/intel/isl/

Re: [Mesa-dev] [PATCH 5/6] intel/isl: Remove tiling checks from choose_msaa_layout

On Fri 02 Sep 2016, Jason Ekstrand wrote: > We already do those checks in filter_tiling. There's no good reason to > repeat them in choose_msaa_layout. If anything they should have been > asserts and not "return false" checks. Also, this check was causing us to > outright reject multisampled HiZ

Re: [Mesa-dev] [PATCH 4/6] intel/isl: Handle HiZ and CCS tiling more directly

On Fri 02 Sep 2016, Jason Ekstrand wrote: > The HiZ and CCS tiling formats are always used for HiZ and CCS surfaces > respectively. There's no reason why we should go through filter_tiling and > it's much easier to always get HiZ and CCS right if we just handle them > directly. > --- > src/intel/

Re: [Mesa-dev] [PATCH 3/6] intel/isl: Allow multisampling with ISL_FORMAT_HiZ

On Fri 02 Sep 2016, Jason Ekstrand wrote: > HiZ buffers can be multisampled and, on BDW+, simply using interleaved > multisampling with a compression block size of 8x4 samples yields the > correct HiZ surface size calculations. Unfortunately, choose_msaa_layout > was rejecting multisampled HiZ buf

Re: [Mesa-dev] EGL_EXT_*_drm - primary vs render node (Was Re: [Piglit] [PATCH 1/2] egl: Add sanity test for EGL_EXT_device_query (v3))

On 09/07/2016 04:18 AM, Emil Velikov wrote: Hi Mathias, On 6 September 2016 at 18:32, Mathias Fröhlich wrote: ** EGL_EXT_output_drm Correction - the above should read: EGL_EXT_{device,output}_drm *** Using/exposing the card or render node - Extension is designed with EGL streams in mind

Re: [Mesa-dev] Proposal: move the Mesa documentation to readthedocs.org

On 09/07/2016 07:58 PM, Nicholas Bishop wrote: > Bump, any interest in this? > In my experience rST is much nicer to write than pure HTML, and I like how the output looks. Definitive yes on the rST instead of HTML, no strong opinion on readthedocs.org vs self-hosted. Regards, Vedran -- Vedran

Re: [Mesa-dev] [PATCH 04/12] anv: Add func anv_image_has_hiz()

On Fri, Sep 02, 2016 at 11:42:24AM -0700, Chad Versace wrote: > On Thu 01 Sep 2016, Jason Ekstrand wrote: > > On Wed, Aug 31, 2016 at 8:29 PM, Nanley Chery wrote: > > > > From: Chad Versace > > > > Nanley Chery (amend): > >  - Remove wip! tag > > > > Signed-off-by: Nanley Chery

Re: [Mesa-dev] [PATCH] spirv/nir: Add support for OpAtomicLoad/Store

Hi Mark, Thanks for the report. The assumption is that coord will be set on the image by a preceding SpvOpImageTexelPointer opcode (see top of the vtn_handle_image function). I don't think there are tests in the CTS exercising this at the moment :( - Lionel On Wed, 2016-09-07 at 10:14 -0700, Ma

[Mesa-dev] [Bug 97542] mesa-12.0.1 with llvm-3.9.0_rc3 - src/gallium/state_trackers/clover/llvm/invocation.cpp:212:75: error: no matching function for call to clang::CompilerInvocation::setLangDefault

https://bugs.freedesktop.org/show_bug.cgi?id=97542 --- Comment #10 from Vedran Miletić --- (In reply to Dennis Schridde from comment #1) > Created attachment 126118 [details] [review] > mesa-12.0.1-llvm-3.9.0_rc3-compatibility.patch > > Attached patch fixes the issue. Using LLVM release_39 bran

Re: [Mesa-dev] Proposal: move the Mesa documentation to readthedocs.org

Bump, any interest in this? On Sat, Aug 27, 2016 at 1:09 AM, Nicholas Bishop wrote: > Hi, > > I'd like to propose a conversion of Mesa's documentation to > reStructuredText (RST) and hosting the result on readthedocs.org. The > intent is to make Mesa's documentation more accessible, searchable,

[Mesa-dev] [PATCH] vl/dri3: handle the case of different GPU

use a linear buffer in case of back buffer Signed-off-by: Nayan Deshmukh --- src/gallium/auxiliary/vl/vl_winsys_dri3.c | 11 --- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/src/gallium/auxiliary/vl/vl_winsys_dri3.c b/src/gallium/auxiliary/vl/vl_winsys_dri3.c index 3d59

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