On Wed, 2016-08-17 at 15:15 -0700, Francisco Jerez wrote:
> Iago Toral writes:
>
> >
> > On Tue, 2016-08-02 at 18:27 -0700, Francisco Jerez wrote:
> > >
> > > Iago Toral Quiroga writes:
> > >
> > > >
> > > >
> > > > ---
> > > > src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 18
> > > > ++
https://bugs.freedesktop.org/show_bug.cgi?id=92877
Timo Aaltonen changed:
What|Removed |Added
CC||tjaal...@ubuntu.com
--
You are receivin
Hi,
On Wednesday, 17 August 2016 11:00:48 CEST Tim Rowley wrote:
> Increases the performance of legacy geometry-heavy apps
> still using display lists.
That is my observation too.
+1 from my side.
If you need that from me this gets:
Reviewed-by: Mathias Fröhlich
Mathias
> ---
> src/mesa/vbo/v
On 18/08/16 05:39 AM, Itai wrote:
> (Posted initially in mesa-users, but got no reply - the list seems dead.
> Couldn't find any bug report, and sadly not well versed enough in mesa
> to file one myself).
FWIW, there's no need to be versed in Mesa to file a bug report. :)
> Following an investig
Hi Dave and all,
(Since Dave implemented this extension EGL_MESA_image_dma_buf_export,
so I also send this email to you.)
Could you please review this patch and push it if it looks good to you?
Thanks!
Thanks,
Chuanbo Weng
-Original Message-
From: mesa-dev [mailto:mesa-d
(Posted initially in mesa-users, but got no reply - the list seems dead.
Couldn't find any bug report, and sadly not well versed enough in mesa to
file one myself).
Following an investigation of a memory leak with JavaFX on some Linux
configuration, it looks like there is a possible memory leak wh
Hi Nicolai
Patch is
Tested-by: Edmondo Tommasina
Thanks
edmondo
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev
OpenMW tries to upload a new surface (mouse pointer) which fails in the now
guarded update_framebuffer_size() as the surface is NULL.
This is not inteded as a real "fix", as it would just hide the immediate crash.
So if somebody could take a look at this...
Reported-by:
Signed-off-by: Tobias Kl
On Wed, Aug 17, 2016 at 3:30 PM, Francisco Jerez wrote:
> Matt Turner writes:
>
>> ... instead of assert failing. Can only happen when the program has an
>> unconditional infinite loop.
>
> I'm curious how the framebuffer write gets eliminated, I don't think DCE
> is smart enough currently to fin
Francisco Jerez writes:
> Matt Turner writes:
>
>> ... instead of assert failing. Can only happen when the program has an
>> unconditional infinite loop.
>
> I'm curious how the framebuffer write gets eliminated, I don't think DCE
> is smart enough currently to find out that the FB write is unre
Matt Turner writes:
> ... instead of assert failing. Can only happen when the program has an
> unconditional infinite loop.
I'm curious how the framebuffer write gets eliminated, I don't think DCE
is smart enough currently to find out that the FB write is unreachable?
> ---
> Sigh.
>
> src/mes
Kenneth Graunke writes:
> Previously, the scalar TCS backend was generating:
>
> mov(8) g17<1>UD 0xUD{ align1 WE_all 1Q compacted };
> and(8) g17.2<1>UD g0.2<0,1,0>UD 0x0001e000UD { align1 WE_all 1Q };
> shl(8) g17.2<1>UD g17.2<8,8,1>UD 0x000bUD { align1 WE_all
Iago Toral writes:
> On Tue, 2016-08-02 at 18:27 -0700, Francisco Jerez wrote:
>> Iago Toral Quiroga writes:
>>
>> >
>> > ---
>> > src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 18 ++
>> > 1 file changed, 18 insertions(+)
>> >
>> > diff --git a/src/mesa/drivers/dri/i965/brw_ve
Previously, the scalar TCS backend was generating:
mov(8) g17<1>UD 0xUD{ align1 WE_all 1Q compacted };
and(8) g17.2<1>UD g0.2<0,1,0>UD 0x0001e000UD { align1 WE_all 1Q };
shl(8) g17.2<1>UD g17.2<8,8,1>UD 0x000bUD { align1 WE_all 1Q };
or(8)g17.2<1>UD g17.2<8
I don't want src_is_bool() and src_is_type(x, nir_type_bool) to behave
differently. Having the logic spread out over three functions makes it
harder to decide where to put new logic, as well.
So, combine them all. It's a bit simpler because there's now only one
recursive function rather than a p
According to Connor, it's safe to assume that the first operand of
bcsel, as well as the operand of b2f and b2i, must be well formed
booleans.
https://lists.freedesktop.org/archives/mesa-dev/2016-August/125658.html
With the previous improvements to a@bool handling, this now has no
change in shade
load_front_face and load_helper_invocation produce booleans.
On Broadwell:
total instructions in shared programs: 11638956 -> 11638011 (-0.01%)
instructions in affected programs: 115093 -> 114148 (-0.82%)
helped: 628
HURT: 14
Signed-off-by: Kenneth Graunke
---
src/compiler/nir/nir_search.c | 7
Currently, 'a@type' can only match if 'a' is produced by an ALU
instruction. This is rather limited - there are other cases we
can easily detect which we should handle.
Extending the code in-place would be fairly messy, so we introduce
a new src_is_type() helper.
Signed-off-by: Kenneth Graunke
Iago Toral writes:
> On Tue, 2016-08-02 at 18:40 -0700, Francisco Jerez wrote:
>> Iago Toral Quiroga writes:
>>
>> >
>> > ---
>> > src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 8 +---
>> > 1 file changed, 5 insertions(+), 3 deletions(-)
>> >
>> > diff --git a/src/mesa/drivers/dri/i965/br
The max basevertex is already computed and added into max_index by the
caller, _tnl_draw_prims.
Signed-off-by: Ilia Mirkin
---
src/mesa/vbo/vbo_split.c | 8
1 file changed, 8 deletions(-)
diff --git a/src/mesa/vbo/vbo_split.c b/src/mesa/vbo/vbo_split.c
index 2f95746..79d7dd4 100644
---
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=97351
Signed-off-by: Ilia Mirkin
Cc: mesa-sta...@lists.freedesktop.org
---
src/mesa/vbo/vbo_split_copy.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mesa/vbo/vbo_split_copy.c b/src/mesa/vbo/vbo_split_copy.c
index d
... instead of assert failing. Can only happen when the program has an
unconditional infinite loop.
---
Sigh.
src/mesa/drivers/dri/i965/brw_fs.cpp | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
b/src/mesa/drivers/dri/i965/brw_fs.cpp
Kenneth Graunke writes:
> Previously, the scalar TCS backend was generating:
>
> mov(8) g17<1>UD 0xUD{ align1 WE_all 1Q compacted };
> and(8) g17.2<1>UD g0.2<0,1,0>UD 0x0001e000UD { align1 WE_all 1Q };
> shl(8) g17.2<1>UD g17.2<8,8,1>UD 0x000bUD { align1 WE_all
Jason Ekstrand writes:
> On Tue, Aug 16, 2016 at 1:54 PM, Francisco Jerez
> wrote:
>
>> This adds a bit of metadata to schedule_node that will be used to
>> compare available nodes in the scheduling heuristic code based on
>> which of them unblocks the earliest successor exit node. Note that
>>
Reviewed-by: Alejandro Piñeiro
On 17/08/16 16:15, Kenneth Graunke wrote:
> The "Barrier Count" field goes in 14:9 of m0.2. The vec4 backend
> correctly shifts by 9, but the scalar backend only shifted by 8.
>
> It's not like this changed - I think I just made a typo when writing
> the original
Reviewed-by: Alejandro Piñeiro
On 17/08/16 16:15, Kenneth Graunke wrote:
> Previously, the scalar TCS backend was generating:
>
> mov(8) g17<1>UD 0xUD{ align1 WE_all 1Q compacted };
> and(8) g17.2<1>UD g0.2<0,1,0>UD 0x0001e000UD { align1 WE_all 1Q };
> shl(8) g17.2<1>U
Reviewed-by: Alejandro Piñeiro
On 17/08/16 16:15, Kenneth Graunke wrote:
> The first simply picks the bany_inequal[234] opcodes based on the SSA
> def's number of components. The latter implicitly compares with zero
> to achieve the same semantics of GLSL's any().
>
> Cc: mesa-sta...@lists.free
Jason Ekstrand writes:
> On Tue, Aug 16, 2016 at 1:54 PM, Francisco Jerez
> wrote:
>
>> This may have been the reason people ran into problems with
>> non-uniform HALT instructions and ended up using the inefficient
>> ANY16H/ANY8H predicates instead of ANY4H or NORMAL in order to prevent
>> non
On Wed, Aug 17, 2016 at 10:24 AM, Marek Olšák wrote:
> From: Marek Olšák
>
> the text string was not zero-terminated.
Oh, that's aggravating that glCreateShaderProgramv() doesn't take a
length like glShaderSource does.
Reviewed-by: Matt Turner
___
me
The basic block following a control flow structure like an infinite loop
will be unreachable. Ignore any non-control-flow instructions in it
since they can have no effect on the program.
Avoids a segmentation fault in cfg_t::intersect(a, b) when called on an
unreachable block. By avoiding ever put
---
src/mesa/drivers/dri/i965/brw_cfg.cpp | 10 ++
1 file changed, 2 insertions(+), 8 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_cfg.cpp
b/src/mesa/drivers/dri/i965/brw_cfg.cpp
index 5d46615..53b32be 100644
--- a/src/mesa/drivers/dri/i965/brw_cfg.cpp
+++ b/src/mesa/drivers/d
https://bugs.freedesktop.org/show_bug.cgi?id=97386
Bug ID: 97386
Summary: [softpipe] piglit
ext_framebuffer_multisample-fast-clear
GL_ARB_texture_rg-float single-sample regression
Product: Mesa
Version: git
On 08/17/2016 12:08 PM, Matt Turner wrote:
On Wed, Aug 17, 2016 at 10:59 AM, Brian Paul wrote:
The lrint() and lrintf() functions are pretty slow and make some
texture transfers very inefficient. This patch makes a better effort
at using those intrisics for 32-bit gcc and MSVC.
Note, this pat
On Wed, Aug 17, 2016 at 10:59 AM, Brian Paul wrote:
> The lrint() and lrintf() functions are pretty slow and make some
> texture transfers very inefficient. This patch makes a better effort
> at using those intrisics for 32-bit gcc and MSVC.
>
> Note, this patch doesn't address the use of SSE4.1
The lrint() and lrintf() functions are pretty slow and make some
texture transfers very inefficient. This patch makes a better effort
at using those intrisics for 32-bit gcc and MSVC.
Note, this patch doesn't address the use of SSE4.1 with MSVC.
Reviewed-by: José Fonseca
---
src/util/rounding.
On Wed, Aug 17, 2016 at 06:51:24PM +0100, Chris Wilson wrote:
> However, X will always send a fake front if the real front is requested,
> and the real front buffer is requested if either the read or write
> buffer is GL_FRONT. So the fake front copy should suffice to trigger the
> flush.
Except f
On Wed, Aug 17, 2016 at 01:34:48PM -0400, Adam Jackson wrote:
> On Wed, 2016-08-17 at 17:50 +0100, Chris Wilson wrote:
> > On Wed, Aug 17, 2016 at 12:13:23PM -0400, Adam Jackson wrote:
> > >
> > > On Wed, 2016-08-17 at 08:17 -0700, Eric Anholt wrote:
> > >
> > > >
> > > > All I'm saying is that
Looks good to me.
Reviewed-by: Neha Bhende
Regards,
Neha
From: Brian Paul
Sent: Wednesday, August 17, 2016 7:40:13 AM
To: mesa-dev@lists.freedesktop.org
Cc: Charmaine Lee; Neha Bhende
Subject: [PATCH 2/2] svga: fix src/dst typo in can_blit_via_copy_region_vg
On Wed, 2016-08-17 at 17:50 +0100, Chris Wilson wrote:
> On Wed, Aug 17, 2016 at 12:13:23PM -0400, Adam Jackson wrote:
> >
> > On Wed, 2016-08-17 at 08:17 -0700, Eric Anholt wrote:
> >
> > >
> > > All I'm saying is that it's the thing that was intentionally used for
> > > this purpose in DRI1 a
From: Marek Olšák
the text string was not zero-terminated.
---
run.c | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/run.c b/run.c
index de815f8..63f933f 100644
--- a/run.c
+++ b/run.c
@@ -634,21 +634,29 @@ main(int argc, char **argv)
ctx_is_core = type
https://bugs.freedesktop.org/show_bug.cgi?id=92877
--- Comment #5 from Kyle Brenneman ---
I've got a draft of a vendor library interface for EGL posted:
https://github.com/NVIDIA/libglvnd/pull/92
I still need to run it through some testing, but assuming it works, I'll have
the patches ready shor
On Wed, Aug 17, 2016 at 12:13:23PM -0400, Adam Jackson wrote:
> On Wed, 2016-08-17 at 08:17 -0700, Eric Anholt wrote:
>
> > All I'm saying is that it's the thing that was intentionally used for
> > this purpose in DRI1 and early DRI2, and maybe if it works we shouldn't
> > just accidentally drop
Series looks good to me.
Reviewed-by: Charmaine Lee
From: Brian Paul
Sent: Wednesday, August 17, 2016 7:40:13 AM
To: mesa-dev@lists.freedesktop.org
Cc: Charmaine Lee; Neha Bhende
Subject: [PATCH 2/2] svga: fix src/dst typo in can_blit_via_copy_region_vg
On Wed, 2016-08-17 at 08:17 -0700, Eric Anholt wrote:
> All I'm saying is that it's the thing that was intentionally used for
> this purpose in DRI1 and early DRI2, and maybe if it works we shouldn't
> just accidentally drop it in a refactor.
I don't see how the patch in this thread does that. I
Increases the performance of legacy geometry-heavy apps
still using display lists.
---
src/mesa/vbo/vbo_save.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mesa/vbo/vbo_save.h b/src/mesa/vbo/vbo_save.h
index 2843b3c..d1d7fb0 100644
--- a/src/mesa/vbo/vbo_save.h
+++ b/src
Adam Jackson writes:
> On Tue, 2016-08-16 at 15:55 +0100, Chris Wilson wrote:
>> On Mon, Aug 17, 2015 at 03:17:30PM -0700, Eric Anholt wrote:
>> >
>> > I think XSync makes more sense. It's cheaper, and it does exactly what
>> > you're supposed to do at this point -- make sure that all your X
>>
---
src/gallium/drivers/svga/svga_pipe_query.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/gallium/drivers/svga/svga_pipe_query.c
b/src/gallium/drivers/svga/svga_pipe_query.c
index bf074b6..33822e6 100644
--- a/src/gallium/drivers/svga/svga_pipe_query.c
+++ b/src/galli
The function was always returning false because of this typo.
Retested with piglit. There's some sRGB-related blit failures, but
that seems unrelated.
---
src/gallium/drivers/svga/svga_pipe_blit.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/gallium/drivers/svga/svga_p
We need an extra set of braces for an array inside a struct.
---
src/compiler/glsl/ast_to_hir.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/compiler/glsl/ast_to_hir.cpp b/src/compiler/glsl/ast_to_hir.cpp
index e03a6e3..abab932 100644
--- a/src/compiler/glsl/ast_to_hir
To silence unused var warning with MSVC, MinGW.
---
src/gallium/auxiliary/hud/hud_context.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/gallium/auxiliary/hud/hud_context.c
b/src/gallium/auxiliary/hud/hud_context.c
index 7870da5..3f3f64f 100644
--- a/src/gallium/auxilia
Since the type is an array inside a union. Silences MinGW warning.
---
src/mesa/state_tracker/st_glsl_to_nir.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mesa/state_tracker/st_glsl_to_nir.cpp
b/src/mesa/state_tracker/st_glsl_to_nir.cpp
index 73a692a..6470fae 100644
On 08/17/2016 03:55 AM, Nicolai Hähnle wrote:
From: Nicolai Hähnle
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=97285
Hi Nicolai,
The commit message seems a bit sparse. It would be nice if one didn't
have to wade through the bug report to know what's being done.
-Brian
---
Previously, the scalar TCS backend was generating:
mov(8) g17<1>UD 0xUD{ align1 WE_all 1Q compacted };
and(8) g17.2<1>UD g0.2<0,1,0>UD 0x0001e000UD { align1 WE_all 1Q };
shl(8) g17.2<1>UD g17.2<8,8,1>UD 0x000bUD { align1 WE_all 1Q };
or(8)g17.2<1>UD g17.2<8
The first simply picks the bany_inequal[234] opcodes based on the SSA
def's number of components. The latter implicitly compares with zero
to achieve the same semantics of GLSL's any().
Cc: mesa-sta...@lists.freedesktop.org
Signed-off-by: Kenneth Graunke
---
src/compiler/nir/nir_builder.h | 19
Fixes several GL44-CTS.tessellation_shader (and GL45 and ES31) subcases:
- vertex_spacing
- tessellation_shader_point_mode.points_verification
- tessellation_shader_quads_tessellation.inner_tessellation_level_rounding
Cc: mesa-sta...@lists.freedesktop.org
Signed-off-by: Kenneth Graunke
---
src/m
The "Barrier Count" field goes in 14:9 of m0.2. The vec4 backend
correctly shifts by 9, but the scalar backend only shifted by 8.
It's not like this changed - I think I just made a typo when writing
the original scalar TCS backend code.
Cc: mesa-sta...@lists.freedesktop.org
Signed-off-by: Kennet
On Thu, Aug 11, 2016 at 02:15:17PM -0700, Jason Ekstrand wrote:
> This mimics what we do on gen8.
> ---
> src/mesa/drivers/dri/i965/gen6_blorp.c | 4 ++--
> src/mesa/drivers/dri/i965/gen7_blorp.c | 17 -
> 2 files changed, 10 insertions(+), 11 deletions(-)
>
> diff --git a/src/me
Pushed, thanks.
Marek
On Tue, Aug 16, 2016 at 2:38 PM, Francesco Ansanelli
wrote:
> v2: long has 32bit on Windows (Marek)
> Signed-off-by: Francesco Ansanelli
> ---
> src/mesa/state_tracker/st_atom_array.c |2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/src/mesa/st
You should re-order the list in priority_to_string (in si_debug.c). I
guess it's not strictly needed, but seems like a good idea.
Nicolai
On 11.08.2016 22:25, Marek Olšák wrote:
From: Marek Olšák
just FYI, the kernel receives priority/4
---
src/gallium/drivers/radeon/radeon_winsys.h | 6 +++
On Wed, 2016-08-03 at 13:28 -0700, Francisco Jerez wrote:
> Iago Toral Quiroga writes:
>
> >
> > Gen7 hardware does not support double immediates so these need
> > to be moved in 32-bit chunks to a regular vgrf instead. Instead
> > of doing this every time we need to create a DF immediate,
> > c
The duplicate `const` was simply being ignored, but const'ing the pointer can be
a weak but useful protection, so let's do that instead.
Signed-off-by: Eric Engestrom
---
src/gallium/drivers/ilo/core/ilo_state_raster.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/galli
On Tue, 2016-08-02 at 18:40 -0700, Francisco Jerez wrote:
> Iago Toral Quiroga writes:
>
> >
> > ---
> > src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 8 +---
> > 1 file changed, 5 insertions(+), 3 deletions(-)
> >
> > diff --git a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
> > b/src/mesa/d
On Wed, Aug 17, 2016 at 12:09 PM, Nicolai Hähnle wrote:
> On 17.08.2016 12:04, Marek Olšák wrote:
>>
>> On Wed, Aug 17, 2016 at 11:41 AM, Nicolai Hähnle
>> wrote:
>>>
>>> On 11.08.2016 18:16, Marek Olšák wrote:
From: Marek Olšák
This is just a workaround. The problem is
On 17.08.2016 12:04, Marek Olšák wrote:
On Wed, Aug 17, 2016 at 11:41 AM, Nicolai Hähnle wrote:
On 11.08.2016 18:16, Marek Olšák wrote:
From: Marek Olšák
This is just a workaround. The problem is described in the code.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=96541
---
src/g
On Wed, Aug 17, 2016 at 11:41 AM, Nicolai Hähnle wrote:
> On 11.08.2016 18:16, Marek Olšák wrote:
>>
>> From: Marek Olšák
>>
>> This is just a workaround. The problem is described in the code.
>>
>> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=96541
>> ---
>> src/gallium/drivers/radeon
For the series:
Reviewed-by: Nicolai Hähnle
On 11.08.2016 22:25, Marek Olšák wrote:
From: Marek Olšák
---
src/gallium/drivers/radeon/r600_streamout.c | 4 ++--
src/gallium/drivers/radeonsi/si_descriptors.c | 6 --
2 files changed, 6 insertions(+), 4 deletions(-)
diff --git a/src/gall
From: Nicolai Hähnle
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=97285
---
src/mesa/state_tracker/st_cb_blit.c | 34 ++
1 file changed, 18 insertions(+), 16 deletions(-)
diff --git a/src/mesa/state_tracker/st_cb_blit.c
b/src/mesa/state_tracker/st_cb_b
On 11.08.2016 18:16, Marek Olšák wrote:
From: Marek Olšák
This is just a workaround. The problem is described in the code.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=96541
---
src/gallium/drivers/radeon/r600_pipe_common.h | 2 +-
src/gallium/drivers/radeon/r600_texture.c | 35
Patches 1-4:
Reviewed-by: Nicolai Hähnle
On 11.08.2016 18:16, Marek Olšák wrote:
From: Marek Olšák
we can now rely on CB_COLORn_INFO to disable empty slots.
---
src/gallium/drivers/radeonsi/si_state.c | 21 +++--
1 file changed, 7 insertions(+), 14 deletions(-)
diff --git a
Christian König wrote:
Top and Bottom field are separated in this representation.
So you got a maximum of 3 planes multiplied by two fields.
Ahh, thanks.
Regards,
Christian.
Am 17.08.2016 um 11:11 schrieb Andy Furniss:
Nayan Deshmukh wrote:
Sorry for the misleading language. What I mean
Patch 1 & 2, where I only looked at the st/mesa and radeon parts:
Acked-by: Nicolai Hähnle
Patch 3:
Reviewed-by: Nicolai Hähnle
On 12.08.2016 18:46, Marek Olšák wrote:
From: Marek Olšák
st/mesa does this too, so we're safe.
---
src/gallium/drivers/radeonsi/si_state.c | 2 +-
1 file chang
On Tue, 2016-08-02 at 18:27 -0700, Francisco Jerez wrote:
> Iago Toral Quiroga writes:
>
> >
> > ---
> > src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 18 ++
> > 1 file changed, 18 insertions(+)
> >
> > diff --git a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
> > b/src/mesa/drive
Top and Bottom field are separated in this representation.
So you got a maximum of 3 planes multiplied by two fields.
Regards,
Christian.
Am 17.08.2016 um 11:11 schrieb Andy Furniss:
Nayan Deshmukh wrote:
Sorry for the misleading language. What I meant was that the filter
should only
be app
Nayan Deshmukh wrote:
Sorry for the misleading language. What I meant was that the filter should only
be applied to first resource i.e. use only first sampler_view and
surface. As you
replaced i by 0 the filter gets applied multiple times. I tried doing
that and I am
experiencing same problems i
On Thu, Jul 28, 2016 at 12:21 AM, Pohjolainen, Topi <
topi.pohjolai...@intel.com> wrote:
> On Thu, Jul 28, 2016 at 10:10:29AM +0300, Pohjolainen, Topi wrote:
> > On Tue, Jul 26, 2016 at 03:02:10PM -0700, Jason Ekstrand wrote:
> > > The helper does a full transformation on the surface to turn it in
On Wed, Aug 17, 2016 at 01:11:18AM -0700, Jason Ekstrand wrote:
>On Wed, Aug 17, 2016 at 12:17 AM, Pohjolainen, Topi
><[1]topi.pohjolai...@intel.com> wrote:
>
> On Tue, Jul 26, 2016 at 03:11:10PM -0700, Jason Ekstrand wrote:
> > The previous HiZ support was bogus because all of g
In case we have empty log (""), we should return 0. This fixes
Khronos WebGL conformance test 'program-infolog'.
From OpenGL ES 3.1 (and OpenGL 4.5 Core) spec:
"If pname is INFO_LOG_LENGTH , the length of the info log, including
a null terminator, is returned. If there is no info log, zero
On Wed, Aug 17, 2016 at 12:17 AM, Pohjolainen, Topi <
topi.pohjolai...@intel.com> wrote:
> On Tue, Jul 26, 2016 at 03:11:10PM -0700, Jason Ekstrand wrote:
> > The previous HiZ support was bogus because all of get_aux_isl_surf looked
> > at mt->mcs_mt directly. For HiZ buffers, you need to look at
On Fri, Jul 29, 2016 at 07:04:40AM -0700, Jason Ekstrand wrote:
>On Jul 29, 2016 2:18 AM, "Pohjolainen, Topi"
><[1]topi.pohjolai...@intel.com> wrote:
>>
>> On Fri, Jul 29, 2016 at 09:58:36AM +0300, Pohjolainen, Topi wrote:
>> > On Tue, Jul 26, 2016 at 03:11:13PM -0700, Jason Eks
On Tue, Jul 26, 2016 at 03:11:10PM -0700, Jason Ekstrand wrote:
> The previous HiZ support was bogus because all of get_aux_isl_surf looked
> at mt->mcs_mt directly. For HiZ buffers, you need to look at either
> mt->hiz_buf or mt->hiz_buf->mt.
Makes a lot more sense:
Reviewed-by: Topi Pohjolaine
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