Re: [Mesa-dev] Building Mesa and LLVM cross compiling Linux to Windows issue

On 17/03/16 18:42, Roland Scheidegger wrote: I suspect you simply ran into an issue with old mesa and new llvm. Unfortunately some usage of the c++ abi of llvm is unavoidable, and the abi is unstable, thus breaking quite often. And we do not generally backport such fixes to older mesa releases (i

[Mesa-dev] [PATCH 07/12] i965/peephole_ffma: Don't fuse exact adds

--- src/mesa/drivers/dri/i965/brw_nir_opt_peephole_ffma.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/mesa/drivers/dri/i965/brw_nir_opt_peephole_ffma.c b/src/mesa/drivers/dri/i965/brw_nir_opt_peephole_ffma.c index 5ff2cba..3c1e27f 100644 --- a/src/mesa/drivers/dri/i

[Mesa-dev] [PATCH 3/4] mesa: simplify and inline _mesa_lookup_parameter_index()

The function has only one user and strings are always null terminated. --- src/mesa/program/ir_to_mesa.cpp | 2 +- src/mesa/program/prog_parameter.c | 38 -- src/mesa/program/prog_parameter.h | 19 +-- 3 files changed, 18 insertions(+), 41 del

[Mesa-dev] [PATCH 03/11] st/mesa: use correct TGSI texture target in drawpix fragment shader

--- src/mesa/state_tracker/st_cb_drawpixels.h| 2 +- src/mesa/state_tracker/st_cb_drawpixels_shader.c | 11 +-- src/mesa/state_tracker/st_program.c | 2 +- 3 files changed, 11 insertions(+), 4 deletions(-) diff --git a/src/mesa/state_tracker/st_cb_drawpixels.h b/sr

Re: [Mesa-dev] [PATCH 06.5/20] radeonsi: update shader image descriptor for invalidated buffer

On 15.03.2016 22:04, Nicolai Hähnle wrote: From: Nicolai Hähnle --- src/gallium/drivers/radeonsi/si_descriptors.c | 22 +- 1 file changed, 21 insertions(+), 1 deletion(-) diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c b/src/gallium/drivers/radeonsi/si_descri

Re: [Mesa-dev] [PATCH 0/7] nv50: rework compute/3d validation path

This serie is: Reviewed-by: Pierre Moreau Tested-by: Pierre Moreau Pierre On 08:54 PM - Mar 15 2016, Samuel Pitoiset wrote: > From: Samuel Pitoiset > > Hi, > > This is loosely based on what I did for nvc0 few weeks ago. I have not tested > this series because I don't have access to a Tesla c

[Mesa-dev] [PATCH] st/mesa: report correct precision information for low/medium/high ints

When we have native integers, these have full precision. Whether they're low/medium/high isn't piped through the TGSI yet, but eventually those might have differing precisions. For now they're just 32-bit ints. Fixes the following dEQP tests: dEQP-GLES3.functional.state_query.shader.precision_v

Re: [Mesa-dev] [PATCH] st/mesa: only minify depth for 3d targets

On 20 March 2016 at 11:28, Ilia Mirkin wrote: > We make sure that that image depth matches the level's depth before > copying it into place. However we should only be minifying the first > level's depth for 3d textures - array textures have the same depth for > all levels. > > This fixes tests suc

Re: [Mesa-dev] [PATCH 06/20] radeonsi: implement set_shader_images

On 17.03.2016 18:13, Marek Olšák wrote: On Tue, Mar 15, 2016 at 7:28 PM, Nicolai Hähnle wrote: From: Nicolai Hähnle Whether DCC is disabled depends on the access flags with which the image is bound: image_load supports DCC, but store and atomic don't. --- src/gallium/drivers/radeonsi/si_des

Re: [Mesa-dev] [PATCH 3/4] st/mesa: emit sampler view decls in PBO upload shader

On 16.03.2016 19:43, Brian Paul wrote: The return type is float, which is what was implicitly used before, AFAICT. Isn't this technically incorrect when the uploaded texture is integer? To be honest, it's not really clear to me what the return type is supposed to mean. I don't think any of th

Re: [Mesa-dev] [PATCH 1/4] gallium/radeon: remove old CS tracing

Series is: Reviewed-by: Nicolai Hähnle On 17.03.2016 10:15, Marek Olšák wrote: Ping On Fri, Mar 11, 2016 at 4:01 PM, Marek Olšák wrote: From: Marek Olšák Cons: - it was only integrated in r600g - it doesn't work with GPUVM - it records buffer contents at the end of IBs instead of at the b

[Mesa-dev] [PATCH 2/9] nir/algebraic: Add two more fsat optimizations

No shader-db changes on Broadwell, but it prevents a regression in one rocketbirds shader that would otherwise be introduced by the next commit --- src/compiler/nir/nir_opt_algebraic.py | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/compiler/nir/nir_opt_algebraic.py b/src/compiler/nir/

[Mesa-dev] [PATCH] nv50/ir: print SUBFM subops

Only 3d subop is currently emitted. Signed-off-by: Samuel Pitoiset --- src/gallium/drivers/nouveau/codegen/nv50_ir_print.cpp | 9 + 1 file changed, 9 insertions(+) diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_print.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_print.cpp

Re: [Mesa-dev] [PATCH 5/5] meta: Don't use integer handles for shaders or programs.

On Wednesday, March 16, 2016 5:36:25 PM PDT Pohjolainen, Topi wrote: > On Wed, Mar 16, 2016 at 12:13:02AM -0700, Kenneth Graunke wrote: [snip] > > @@ -265,22 +270,21 @@ setup_coord_coeff(GLuint prog, GLuint multiplier, GLuint offset, > > * destination rectangle is adjusted for possible msaa and

Re: [Mesa-dev] [PATCH 2/5] i965/cfg: Track prev_block and prev_inst explicitly in the whole function

Ian Romanick writes: > From: Ian Romanick > > This provides a trivial simplification now, and it makes some future > changes more straight forward. > > Signed-off-by: Ian Romanick > --- > src/mesa/drivers/dri/i965/brw_dead_control_flow.cpp | 12 +++- > 1 file changed, 7 insertions(+),

Re: [Mesa-dev] [PATCH mesa 1/6] tgsi_build: Fix return of uninitialized memory in tgsi_*_instruction_memory

On 16.03.2016 04:23, Hans de Goede wrote: tgsi_default_instruction_memory / tgsi_build_instruction_memory were returning uninitialized memory for tgsi_instruction_memory.Texture and tgsi_instruction_memory.Format. Note 0 means not set, and thus is a correct default initializer for these. Fixes:

[Mesa-dev] [PATCH] st/mesa: only minify depth for 3d targets

We make sure that that image depth matches the level's depth before copying it into place. However we should only be minifying the first level's depth for 3d textures - array textures have the same depth for all levels. This fixes tests such as dEQP-GLES3.functional.texture.specification.texsubima

[Mesa-dev] [PATCH 7/9] i965/vec4: Don't allow type conversion in opt_vector_float

--- src/mesa/drivers/dri/i965/brw_vec4.cpp | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mesa/drivers/dri/i965/brw_vec4.cpp b/src/mesa/drivers/dri/i965/brw_vec4.cpp index baf72a2..155a550 100644 --- a/src/mesa/drivers/dri/i965/brw_vec4.cpp +++ b/src/mesa/drivers/dri/i965/brw_vec4.cpp @@

[Mesa-dev] [Bug 94452] dEQP-GLES3.functional.negative_api.texture.generatemipmap fails

https://bugs.freedesktop.org/show_bug.cgi?id=94452 Kenneth Graunke changed: What|Removed |Added Status|NEW |ASSIGNED Assignee|mesa-dev@l

Re: [Mesa-dev] [PATCH 1/9] i965/fs: Remove the RCP+RSQ peephole

On Thu, Mar 17, 2016 at 5:40 PM, Jason Ekstrand wrote: > On Thu, Mar 17, 2016 at 10:45 AM, Matt Turner wrote: >> On Thu, Mar 17, 2016 at 10:21 AM, Jason Ekstrand >> wrote: >> > NIR already has this optimization and it can do much better than the >> > little >> > peephole in the backend. >> > >>

[Mesa-dev] [PATCH 5/9] i965/fs: Don't constant-fold RCP

No shader-db changes on Broadwell --- src/mesa/drivers/dri/i965/brw_fs_copy_propagation.cpp | 15 --- 1 file changed, 15 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_fs_copy_propagation.cpp b/src/mesa/drivers/dri/i965/brw_fs_copy_propagation.cpp index 2616e65..ffab0a8 1006

[Mesa-dev] [PATCH mesa v2 1/3] nouveau: codegen: Disable more old resource handling code

Commit c3083c7082 ("nv50/ir: add support for BUFFER accesses") disabled / commented out some of the old resource handling code, but not all of it. Effectively all of it is dead already, if we ever enter the old code paths in handeLOAD / handleSTORE / handleATOM we will get an exception due to tryi

[Mesa-dev] [PATCH V4] glsl: disable varying packing when its not safe

In GL 4.4+ there is no guarantee that interpolation qualifiers will match between stages so we cannot safely pack varyings using the current packing pass in Mesa. We also disable packing on outerward facing interfaces for SSO because in ES we need to retain the unpacked varying information for dra

Re: [Mesa-dev] [PATCH 13/14] nir: propagate bitsize information in nir_search

On Wed, 2016-03-16 at 10:54 -0700, Jason Ekstrand wrote: > > > On Wed, Mar 16, 2016 at 2:01 AM, Iago Toral wrote: > On Wed, 2016-03-16 at 09:48 +0100, Samuel Iglesias Gonsálvez > wrote: > > > > On 15/03/16 08:41, Iago Toral wrote: > > > On Mon, 2016-03-14

[Mesa-dev] Building Mesa and LLVM cross compiling Linux to Windows issue

Hi all, I have been trying to compile LLVM 3.8 and Mesa 11.0.7, and I have the final last hurdle I think to get past scons: Building targets ... Linking build/windows-x86_64/gallium/targets/libgl-gdi/opengl32.dll ... /home/janderssen/mesa_win64/llvm-3.8.build/lib/libLLVMCodeGen.a(Passes.o):

Re: [Mesa-dev] [PATCH] configure.ac: enable_asm=yes when x-compiling across same X86 arch

Matt, I uploaded v2 patch with corrected commit message. Other than commit message, everything is still same. Can you please re-review it and merge it if there's no issue? Thanks On Tue, Feb 16, 2016 at 10:05:24AM -0800, Dongwon Kim wrote: > Currently, configure script is forcing 'enable_asm'

Re: [Mesa-dev] [PATCH] nvc0/lowering: Handle conversions to U64/S64 manually

On 06:41 PM - Mar 19 2016, Ilia Mirkin wrote: > On Sat, Mar 19, 2016 at 6:36 PM, Pierre Moreau wrote: > > On 06:26 PM - Mar 19 2016, Ilia Mirkin wrote: > >> On Sat, Mar 19, 2016 at 6:26 PM, Pierre Moreau > >> wrote: > >> > However, you could have some `long bar; char foo = > >> > convert_char_s

Re: [Mesa-dev] [PATCH 2/5] nv50/ir: make use of auxCBSlot instead of magic numbers

Hello, On 10:38 AM - Mar 16 2016, Hans de Goede wrote: > Hi, > > On 15-03-16 21:55, Samuel Pitoiset wrote: > >This avoids using magic numbers for the driver constbuf slot which > >is always 15 except for compute shaders on gk104+ where the slot 0 > >is used. > > > >For gk104+, some special comput

Re: [Mesa-dev] [PATCH 06/20] radeonsi: implement set_shader_images

On Tue, Mar 15, 2016 at 7:28 PM, Nicolai Hähnle wrote: > From: Nicolai Hähnle > > Whether DCC is disabled depends on the access flags with which the image > is bound: image_load supports DCC, but store and atomic don't. > --- > src/gallium/drivers/radeonsi/si_descriptors.c | 206 > +

[Mesa-dev] [PATCH] i965: Decode non-normalized coordinates bit in SAMPLER_STATE.

We weren't printing this for some reason. Signed-off-by: Kenneth Graunke --- src/mesa/drivers/dri/i965/brw_state_dump.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_state_dump.c b/src/mesa/drivers/dri/i965/brw_state_dump.c index 4666788.

Re: [Mesa-dev] [PATCH 4/5] nvc0: avoid using magic numbers for the uniform_bo offsets

On 03/17/2016 01:02 AM, Pierre Moreau wrote: Hello, On 09:55 PM - Mar 15 2016, Samuel Pitoiset wrote: Instead make use of constants to improve readability. Signed-off-by: Samuel Pitoiset --- src/gallium/drivers/nouveau/nvc0/nvc0_compute.c| 13 +- src/gallium/drivers/nouveau/n

Re: [Mesa-dev] [PATCH 22/20] radeonsi: disable early Z if the fragment shader writes to memory

I made comments on patches 17 & 18. With those addressed, patches 13-22 including 15 v2 are: Reviewed-by: Marek Olšák Marek On Wed, Mar 16, 2016 at 4:09 AM, Nicolai Hähnle wrote: > From: Nicolai Hähnle > > Empirically, both the EXEC_ON_* flags and LATE_Z are necessary. > --- > src/gallium/d

Re: [Mesa-dev] [PATCH 05/10] radeonsi: ignore PIPE_BIND_LINEAR in si_is_format_supported

Looks good. Reviewed-by: Marek Olšák Marek On Thu, Mar 17, 2016 at 2:47 PM, Christian König wrote: > Am 09.03.2016 um 15:53 schrieb Marek Olšák: >> >> On Wed, Mar 9, 2016 at 4:54 AM, Michel Dänzer wrote: >>> >>> On 08.03.2016 21:21, Christian König wrote: From: Christian König

Re: [Mesa-dev] [PATCH 4/9] i965/fs: Get rid of all remaining algebraic optimizations for floats

Jason Ekstrand writes: > --- > src/mesa/drivers/dri/i965/brw_fs.cpp | 74 > +--- > 1 file changed, 18 insertions(+), 56 deletions(-) > > diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp > b/src/mesa/drivers/dri/i965/brw_fs.cpp > index 365231e..9f303d5 100644 >

[Mesa-dev] [PATCH 4/4] mesa: inline _mesa_add_unnamed_constant()

--- src/mesa/program/prog_parameter.c | 22 -- src/mesa/program/prog_parameter.h | 8 ++-- 2 files changed, 6 insertions(+), 24 deletions(-) diff --git a/src/mesa/program/prog_parameter.c b/src/mesa/program/prog_parameter.c index 25d3835..470c98e 100644 --- a/src/mesa/pr

[Mesa-dev] [PATCH 1/2] glsl: Don't require matching centroid qualifiers for newer GLSL

The OpenGLES GLSL 3.1 and OpenGL GLSL 4.3 specifications both remove the requirement for the output and input centroid qualifiers to match. The OpenGL 4.2 spec says: "the last active shader stage output variables and fragment shader input variables of the same name must match in type and qualifica

Re: [Mesa-dev] [PATCH] nvc0/lowering: Handle conversions to U64/S64 manually

On Sat, Mar 19, 2016 at 6:36 PM, Pierre Moreau wrote: > On 06:26 PM - Mar 19 2016, Ilia Mirkin wrote: >> On Sat, Mar 19, 2016 at 6:26 PM, Pierre Moreau wrote: >> > However, you could have some `long bar; char foo = convert_char_sat(bar);` >> > in >> > the OpenCL kernel. >> >> Sure, but the SPIR-

[Mesa-dev] [PATCH 1/1] vc4: Remove unused include from vc4_nir_lower_txf_ms.c

Found with grep and inspection. Test compiled on RPi hw. Assists any future effort to remove TGSI as an intermediate stage. Signed-off-by: Rhys Kidd --- src/gallium/drivers/vc4/vc4_nir_lower_txf_ms.c | 1 - 1 file changed, 1 deletion(-) diff --git a/src/gallium/drivers/vc4/vc4_nir_lower_txf_ms.

Re: [Mesa-dev] [PATCH] nv50/ir: Split 64-bit MAD and MUL operations

On 06:24 PM - Mar 19 2016, Ilia Mirkin wrote: > On Sat, Mar 19, 2016 at 6:15 PM, Pierre Moreau wrote: > > On 06:05 PM - Mar 19 2016, Ilia Mirkin wrote: > >> Not 100% sure, but pretty sure this is wrong. Can you provide the > >> generated sequence of instructions in response to a 64-bit mul and > >

Re: [Mesa-dev] [PATCH 18/20] radeonsi: force the DCC enable bit off in image descriptors for writing

On Tue, Mar 15, 2016 at 7:29 PM, Nicolai Hähnle wrote: > From: Nicolai Hähnle > > This avoids a lockup at least on Tonga. > --- > src/gallium/drivers/radeonsi/si_shader.c | 53 > +++- > 1 file changed, 45 insertions(+), 8 deletions(-) > > diff --git a/src/gallium/dri

Re: [Mesa-dev] [PATCH] nvc0/lowering: Handle conversions to U64/S64 manually

On 06:26 PM - Mar 19 2016, Ilia Mirkin wrote: > On Sat, Mar 19, 2016 at 6:26 PM, Pierre Moreau wrote: > > However, you could have some `long bar; char foo = convert_char_sat(bar);` > > in > > the OpenCL kernel. > > Sure, but the SPIR-V -> nv50/ir converter could be smarter about when > it genera

Re: [Mesa-dev] [PATCH] nv50/ra: `isinf()` is in namespace `std` since C++11

On 19/03/16 22:30, Jose Fonseca wrote: On 19/03/16 22:25, Ilia Mirkin wrote: On Sat, Mar 19, 2016 at 6:23 PM, Jose Fonseca wrote: On 18/03/16 04:00, Ilia Mirkin wrote: On Mar 17, 2016 8:27 PM, "Matt Turner" mailto:matts...@gmail.com>> wrote: > > On Thu, Mar 17, 2016 at 5:17 PM, Pierre M

Re: [Mesa-dev] [PATCH] nvc0/lowering: Handle conversions to U64/S64 manually

On Sat, Mar 19, 2016 at 6:26 PM, Pierre Moreau wrote: > However, you could have some `long bar; char foo = convert_char_sat(bar);` in > the OpenCL kernel. Sure, but the SPIR-V -> nv50/ir converter could be smarter about when it generates the converts, no? -ilia

Re: [Mesa-dev] [PATCH] nv50/ra: `isinf()` is in namespace `std` since C++11

On Sat, Mar 19, 2016 at 6:23 PM, Jose Fonseca wrote: > On 18/03/16 04:00, Ilia Mirkin wrote: >> >> >> On Mar 17, 2016 8:27 PM, "Matt Turner" > > wrote: >> > >> > On Thu, Mar 17, 2016 at 5:17 PM, Pierre Moreau > > wrote: >> > > This fixes

Re: [Mesa-dev] [PATCH 17/20] radeonsi: implement MemoryBarrier

On Tue, Mar 15, 2016 at 7:29 PM, Nicolai Hähnle wrote: > From: Nicolai Hähnle > > --- > src/gallium/drivers/radeonsi/si_state.c | 36 > + > 1 file changed, 36 insertions(+) > > diff --git a/src/gallium/drivers/radeonsi/si_state.c > b/src/gallium/drivers/radeonsi

Re: [Mesa-dev] [PATCH] nvc0/lowering: Handle conversions to U64/S64 manually

On 06:06 PM - Mar 19 2016, Ilia Mirkin wrote: > Where are these coming from? Could you perhaps not generate them in > the first place? Those are coming from the generated SPIR-V, of the following kernel for example: __kernel void global_id(__global int * out) { unsigned id = get_glo

Re: [Mesa-dev] [PATCH] nv50/ra: `isinf()` is in namespace `std` since C++11

On 19/03/16 22:25, Ilia Mirkin wrote: On Sat, Mar 19, 2016 at 6:23 PM, Jose Fonseca wrote: On 18/03/16 04:00, Ilia Mirkin wrote: On Mar 17, 2016 8:27 PM, "Matt Turner" mailto:matts...@gmail.com>> wrote: > > On Thu, Mar 17, 2016 at 5:17 PM, Pierre Moreau mailto:pierre.mor...@free.fr>> wro

Re: [Mesa-dev] [PATCH 5/5] meta: Don't use integer handles for shaders or programs.

On Wed, Mar 16, 2016 at 12:13:02AM -0700, Kenneth Graunke wrote: > Previously, we gave our internal clear/blit shaders actual GL handles > and stored them in the shader/program hash table. We used ordinary > GL API entrypoints to work with them. > > We thought this shouldn't be a problem because

Re: [Mesa-dev] [PATCH 2/5] nv50/ir: make use of auxCBSlot instead of magic numbers

On 03/16/2016 10:38 AM, Hans de Goede wrote: Hi, On 15-03-16 21:55, Samuel Pitoiset wrote: This avoids using magic numbers for the driver constbuf slot which is always 15 except for compute shaders on gk104+ where the slot 0 is used. For gk104+, some special compute-related values like the t

Re: [Mesa-dev] [PATCH] nv50/ir: Split 64-bit MAD and MUL operations

On Sat, Mar 19, 2016 at 6:15 PM, Pierre Moreau wrote: > On 06:05 PM - Mar 19 2016, Ilia Mirkin wrote: >> Not 100% sure, but pretty sure this is wrong. Can you provide the >> generated sequence of instructions in response to a 64-bit mul and >> mad? > > For the given mul: > > mul u64 %r55d %r42d

Re: [Mesa-dev] [PATCH] nv50/ra: `isinf()` is in namespace `std` since C++11

On 18/03/16 04:00, Ilia Mirkin wrote: On Mar 17, 2016 8:27 PM, "Matt Turner" mailto:matts...@gmail.com>> wrote: > > On Thu, Mar 17, 2016 at 5:17 PM, Pierre Moreau mailto:pierre.mor...@free.fr>> wrote: > > This fixes a compile error while building Nouveau with C++11 enabled (and > > glibc >=

Re: [Mesa-dev] [PATCH] nv50/ir: Split 64-bit MAD and MUL operations

On 06:05 PM - Mar 19 2016, Ilia Mirkin wrote: > Not 100% sure, but pretty sure this is wrong. Can you provide the > generated sequence of instructions in response to a 64-bit mul and > mad? For the given mul: mov u64 %r42d 0x0004 mov u64 %r52d 0x0002 mul u64 %r55d %r

Re: [Mesa-dev] [PATCH] nvc0/lowering: Handle conversions to U64/S64 manually

Where are these coming from? Could you perhaps not generate them in the first place? On Sat, Mar 19, 2016 at 5:56 PM, Pierre Moreau wrote: > Generating a `cvt u32 $r0 u64 $r1d` or a `cvt u64 $r0d u32 $r2` makes the GPU > unhappy. Instead, manually handle the conversion between 64-bit and 32-bit >

Re: [Mesa-dev] [PATCH] nv50/ir: Split 64-bit MAD and MUL operations

Not 100% sure, but pretty sure this is wrong. Can you provide the generated sequence of instructions in response to a 64-bit mul and mad? On Sat, Mar 19, 2016 at 5:56 PM, Pierre Moreau wrote: > Two 32-bit MAD or MUL operations are generated in place of the original 64-bit > operation. All operand

[Mesa-dev] [PATCH] nvc0/lowering: Handle conversions to U64/S64 manually

Generating a `cvt u32 $r0 u64 $r1d` or a `cvt u64 $r0d u32 $r2` makes the GPU unhappy. Instead, manually handle the conversion between 64-bit and 32-bit values, and use `cvt` to convert between the original target (resp. source) and 32-bit value. This happens to be the behaviour of NVIDIA's driver.

[Mesa-dev] [PATCH] nv50/ir: Split 64-bit MAD and MUL operations

Two 32-bit MAD or MUL operations are generated in place of the original 64-bit operation. All operands can either be signed or unsigned, but they have to be integers. Signed-off-by: Pierre Moreau --- src/gallium/drivers/nouveau/codegen/nv50_ir_build_util.cpp | 11 ++- 1 file changed, 10

[Mesa-dev] [PATCH 05/12] nir/algebraic: Flag inexact optimizations

Many of our optimizations, while great for cutting shaders down to size, aren't really precision-safe. This commit tries to flag all of the inexact floating-point optimizations so they don't get run on values that are flagged "exact". It's a bit conservative and maybe flags some safe optimization

[Mesa-dev] [PATCH 3/4] st/mesa: simplify drawpixels shader code with tgsi transform helper functions

--- src/mesa/state_tracker/st_cb_drawpixels_shader.c | 82 ++-- 1 file changed, 18 insertions(+), 64 deletions(-) diff --git a/src/mesa/state_tracker/st_cb_drawpixels_shader.c b/src/mesa/state_tracker/st_cb_drawpixels_shader.c index 749b46c..2cf75f8 100644 --- a/src/mesa/stat

Re: [Mesa-dev] [PATCH 12/20] radeonsi: Lower TGSI_OPCODE_STORE down to LLVM op

Patches 1-12, including 06.5 and 11 v2: Reviewed-by: Marek Olšák Marek On Tue, Mar 15, 2016 at 7:28 PM, Nicolai Hähnle wrote: > From: Nicolai Hähnle > > --- > src/gallium/drivers/radeonsi/si_shader.c | 83 > ++-- > 1 file changed, 80 insertions(+), 3 deletions(-)

Re: [Mesa-dev] [PATCH 02/12] nir/builder: Add a flag for setting exact

On Thu, Mar 17, 2016 at 6:13 PM, Jason Ekstrand wrote: > How about 'Whether new ALU instructions will be marked "exact"' Sounds good. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH] nv50/ir: print SUBFM subops

Reviewed-by: Ilia Mirkin On Mar 17, 2016 6:25 PM, "Samuel Pitoiset" wrote: > Only 3d subop is currently emitted. > > Signed-off-by: Samuel Pitoiset > --- > src/gallium/drivers/nouveau/codegen/nv50_ir_print.cpp | 9 + > 1 file changed, 9 insertions(+) > > diff --git a/src/gallium/driver

Re: [Mesa-dev] [PATCH mesa 6/6] nouveau: codegen: Disable more old resource handling code

On 03/16/2016 11:49 AM, Hans de Goede wrote: Hi, On 16-03-16 11:45, Samuel Pitoiset wrote: On 03/16/2016 10:23 AM, Hans de Goede wrote: Commit c3083c7082 ("nv50/ir: add support for BUFFER accesses") disabled / commented out some of the old resource handling code, but not all of it. Effect

[Mesa-dev] [Bug 94522] llvmpipe crash in rendering on Atom

https://bugs.freedesktop.org/show_bug.cgi?id=94522 --- Comment #13 from Jose Fonseca --- (In reply to comicfans44 from comment #12) > but still crash at lp_rast.c:457 > > 0xb7fc26f3 in ?? () [...] > > info locals: > state = 0xac500900 > variant = 0xb4c18380 > scene = > color = {0xa8ec01b0 ,

[Mesa-dev] [PATCH 04/12] nir/algebraic: Allow for flagging operations as being inexact

--- src/compiler/nir/nir_algebraic.py | 9 - src/compiler/nir/nir_opt_algebraic.py | 9 - src/compiler/nir/nir_search.c | 4 src/compiler/nir/nir_search.h | 6 ++ 4 files changed, 26 insertions(+), 2 deletions(-) diff --git a/src/compiler/nir/nir_algeb

Re: [Mesa-dev] [PATCH 3/4] st/mesa: emit sampler view decls in PBO upload shader

On 03/17/2016 10:47 AM, Nicolai Hähnle wrote: On 16.03.2016 19:43, Brian Paul wrote: The return type is float, which is what was implicitly used before, AFAICT. Isn't this technically incorrect when the uploaded texture is integer? That was my suspicion, regardless of my patch. I'm not too

[Mesa-dev] [Bug 94627] Game Risen on wine black grass

https://bugs.freedesktop.org/show_bug.cgi?id=94627 Ilia Mirkin changed: What|Removed |Added Component|Other |Drivers/DRI/nouveau Assignee|mes

Re: [Mesa-dev] [PATCH 7/9] i965/vec4: Don't allow type conversion in opt_vector_float

On Thu, Mar 17, 2016 at 10:21 AM, Jason Ekstrand wrote: > --- > src/mesa/drivers/dri/i965/brw_vec4.cpp | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/src/mesa/drivers/dri/i965/brw_vec4.cpp > b/src/mesa/drivers/dri/i965/brw_vec4.cpp > index baf72a2..155a550 100644 > --- a/src/mesa/drive

[Mesa-dev] [PATCH mesa v2 2/3] nouveau: codegen: Do not silently fail in handeLOAD / handleSTORE / handleATOM

handeLOAD / handleSTORE / handleATOM can only handle TGSI_FILE_BUFFER and TGSI_FILE_MEMORY. Make things fail explictly when another register-file is used in these functions. Signed-off-by: Hans de Goede --- Changes in v2: -Split out of "nouveau: codegen: Disable more old resource handling code" -

Re: [Mesa-dev] [PATCH 11/12] glsl/rebalance_tree: Don't handle invariant or precise trees

Jason Ekstrand writes: > --- > src/compiler/glsl/opt_rebalance_tree.cpp | 16 > 1 file changed, 16 insertions(+) > > diff --git a/src/compiler/glsl/opt_rebalance_tree.cpp > b/src/compiler/glsl/opt_rebalance_tree.cpp > index 095f2d7..8045d51 100644 > --- a/src/compiler/glsl/opt_

Re: [Mesa-dev] [PATCH mesa 4/6] nouveau: codegen: s/FILE_MEMORY_GLOBAL/FILE_MEMORY_BUFFER/

On Wed, Mar 16, 2016 at 2:14 PM, Hans de Goede wrote: > Hi, > > On 16-03-16 15:55, Ilia Mirkin wrote: >> >> This approach leads to the emitters needing to know about both global and >> buffer, even though at that point, they are identical. I was thinking that >> in the lowering logic, buffer would

Re: [Mesa-dev] [PATCH V4] glsl: disable varying packing when its not safe

Reviewed-by: Samuel Iglesias Gonsálvez On 16/03/16 12:30, Timothy Arceri wrote: > In GL 4.4+ there is no guarantee that interpolation qualifiers will > match between stages so we cannot safely pack varyings using the > current packing pass in Mesa. > > We also disable packing on outerward facing

[Mesa-dev] [PATCH 11/12] glsl/rebalance_tree: Don't handle invariant or precise trees

--- src/compiler/glsl/opt_rebalance_tree.cpp | 16 1 file changed, 16 insertions(+) diff --git a/src/compiler/glsl/opt_rebalance_tree.cpp b/src/compiler/glsl/opt_rebalance_tree.cpp index 095f2d7..8045d51 100644 --- a/src/compiler/glsl/opt_rebalance_tree.cpp +++ b/src/compiler/gl

[Mesa-dev] [PATCH 3/9] i965/fs: Get rid of the sel.sat peephole

Shader-db results on Broadwell: total instructions in shared programs: 7517815 -> 7517816 (0.00%) instructions in affected programs: 46 -> 47 (2.17%) HURT: 1 The one hurt shader is a shader from "The Swapper" that writes to gl_FrontColor and, as such, gets an

Re: [Mesa-dev] [PATCH 09/12] glsl: Add a pass to propagate the "invariant" and "precise" qualifiers

Jason Ekstrand writes: > --- > src/compiler/Makefile.sources | 1 + > src/compiler/glsl/glsl_parser_extras.cpp | 1 + > src/compiler/glsl/ir_optimization.h| 1 + > src/compiler/glsl/propagate_invariance.cpp | 125 > + > 4 files changed, 1

[Mesa-dev] [PATCH 02/12] nir/builder: Add a flag for setting exact

--- src/compiler/nir/nir_builder.h | 9 + 1 file changed, 9 insertions(+) diff --git a/src/compiler/nir/nir_builder.h b/src/compiler/nir/nir_builder.h index d546e41..1d61ff9 100644 --- a/src/compiler/nir/nir_builder.h +++ b/src/compiler/nir/nir_builder.h @@ -31,6 +31,9 @@ struct exec_list

Re: [Mesa-dev] [PATCH 2/2] mesa: Do proper format error checks for GenerateMipmap in ES 3.x.

Reviewed-by: Jordan Justen On 2016-03-16 20:32:19, Kenneth Graunke wrote: > According to the OpenGL ES 3.2 spec's description of GenerateMipmap: > > "An INVALID_OPERATION error is generated if the levelbase array was not > specified with an unsized internal format from table 8.3 or a sized > i

Re: [Mesa-dev] [PATCH] nv50/ra: `isinf()` is in namespace `std` since C++11

On 03/18/2016 01:22 AM, Matt Turner wrote: On Thu, Mar 17, 2016 at 5:17 PM, Pierre Moreau wrote: This fixes a compile error while building Nouveau with C++11 enabled (and glibc >= 2.23). This happens if SWR is enabled, as it forces C++11. That seems bad, right? Enabling OpenSWR should affe

Re: [Mesa-dev] [PATCH 4/9] i965/fs: Get rid of all remaining algebraic optimizations for floats

On Thu, Mar 17, 2016 at 10:21 AM, Jason Ekstrand wrote: > --- > src/mesa/drivers/dri/i965/brw_fs.cpp | 74 > +--- > 1 file changed, 18 insertions(+), 56 deletions(-) > > diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp > b/src/mesa/drivers/dri/i965/brw_fs.cpp >

[Mesa-dev] [Bug 94627] Game Risen on wine black grass

https://bugs.freedesktop.org/show_bug.cgi?id=94627 --- Comment #1 from Heiko Ernst --- I have test it with geforce GTX 670. This is the Link to the trace file https://drive.google.com/file/d/0B3ZWj0J3q6uRcHpJYkNPeTk1dVE/view?usp=sharing -- You are receiving this mail because: You are the QA Con

Re: [Mesa-dev] [PATCH] gallium/swr: Cleaned up some context-resource management

Reviewed-by: Bruce Cherniak On 3/14/16, 5:40 PM, "mesa-dev on behalf of George Kyriazis" wrote: >Removed bound_to_context. We now pick up the context from the screen >instead of the resource itself. The resource could be out-of-date >and point to a pipe that is already freed. > >Fixes m

Re: [Mesa-dev] [PATCH 06/10] st/vdpau: use linear layout for output surfaces

Patch 6-10 are: Reviewed-by: Leo Liu On 03/08/2016 07:21 AM, Christian König wrote: From: Christian König Works around a bug in radeonsi and tiling is actually not very beneficial in this use case. Signed-off-by: Christian König --- src/gallium/state_trackers/vdpau/output.c | 3 ++- 1 fi

Re: [Mesa-dev] [PATCH 12/17] gallium/util: Ensure util_framebuffer_get_num_samples() is valid

Normally samples == 0 is perfecly valid and means "not multisampling". Why is it invalid here? On Sat, Mar 19, 2016 at 2:41 AM, Edward O'Callaghan wrote: > Upon context creation, internal driver structures are malloc()'ed > and memset() to zero them. This results in a invalid number of > samples

[Mesa-dev] [PATCH v2] nvc0/ir: Use double constant in `handleSQRT()`

v2: Use "Fixes: sha1 (subject)" format for the fixes section, as pointed out by Ilia Mirin Fixes: a100d89d0998 ("nv50,nvc0: Fix invalid constant.") Signed-off-by: Pierre Moreau --- src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletio

[Mesa-dev] [Bug 94627] Game Risen on wine black grass

https://bugs.freedesktop.org/show_bug.cgi?id=94627 Bug ID: 94627 Summary: Game Risen on wine black grass Product: Mesa Version: 11.1 Hardware: All OS: Linux (All) Status: NEW Severity: normal Pri

Re: [Mesa-dev] [PATCH v2] nvc0/ir: Use double constant in `handleSQRT()`

Reviewed-by: Ilia Mirkin Thanks for noticing this! On Sat, Mar 19, 2016 at 12:56 PM, Pierre Moreau wrote: > v2: Use "Fixes: sha1 (subject)" format for the fixes section, as pointed out > by Ilia Mirin > > Fixes: a100d89d0998 ("nv50,nvc0: Fix invalid constant.") > Signed-off-by: Pierre Morea

Re: [Mesa-dev] [PATCH] nvc0/ir: Use double constant in `handleSQRT()`

Please use the same format for fixes as in the other commit, i.e. Fixes: sha1 (subject) That way it's easier to have tools that automatically track this stuff. On Sat, Mar 19, 2016 at 12:40 PM, Pierre Moreau wrote: > Fixes: > > commit a100d89d09981d2ebb42a7e4643a48e78db8dfe3 > Author: V

[Mesa-dev] [PATCH v2] i965: Fix stencil texturing in ES 3.1.

Stencil texturing is required by ES 3.1. Apparently we never actually turned it on, and we missed some necessary code. Fixes nine dEQP-GLES31.functional tests: stencil_texturing.format.stencil_index8_2d texture.border_clamp.formats.stencil_index8.nearest_size_pot texture.border_clamp.formats.ste

[Mesa-dev] [PATCH] nvc0/ir: Use double constant in `handleSQRT()`

Fixes: commit a100d89d09981d2ebb42a7e4643a48e78db8dfe3 Author: Vinson Lee Date: Fri Mar 18 18:28:28 2016 -0700 nv50,nvc0: Fix invalid constant. Signed-off-by: Pierre Moreau --- src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp | 2 +- 1 file changed, 1 insert

Re: [Mesa-dev] [PATCH 1/3] nv50: reset TFB bufctx when we no longer hold a reference to the buffers

Patches 1-2 are: Reviewed-by: Samuel Pitoiset For patch 3, I don't enough know this part to have a look. On 03/19/2016 05:04 PM, Ilia Mirkin wrote: This fix is analogous to commit ff085d014. This fixes some use-after-free situations in dEQP when an xfb state is removed, and then a clear is t

Re: [Mesa-dev] [PATCH 13/14] nir: propagate bitsize information in nir_search

On Thu, Mar 17, 2016 at 5:15 AM, Iago Toral wrote: > On Wed, 2016-03-16 at 10:54 -0700, Jason Ekstrand wrote: > > > > > > On Wed, Mar 16, 2016 at 2:01 AM, Iago Toral wrote: > > On Wed, 2016-03-16 at 09:48 +0100, Samuel Iglesias Gonsálvez > > wrote: > > > > > > On

Re: [Mesa-dev] [RFC mesa] nouveau: Add support for OpenCL global memory buffers

Hi, On 14-03-16 21:50, Samuel Pitoiset wrote: Btw, do you need someone with commit access to push your previous series (the tgsi thing)? I can do this for you. Thanks for the offer. IIRC Ilia wanted some minor fixes there, so I'll do a v2 tomorrow. Talking about commit rights, I guess it wo

[Mesa-dev] [PATCH 15/20] radeonsi: implement coherent memory access (v2)

From: Nicolai Hähnle v2: set glc=1 for volatile also on buffers --- volatile should behave like coherent in this regard, which it already did for images in v1. --- src/gallium/drivers/radeonsi/si_shader.c | 17 + 1 file changed, 13 insertions(+), 4 deletions(-) diff --git a/src/

Re: [Mesa-dev] [PATCH] r300g: add missing layer argument to rws->buffer_get_handle() call

Ups, yeah that's a rebase problem. Sorry for not compiling R300 once more. Patch is Reviewed-by: Christian König Regards, Christian. Am 17.03.2016 um 16:49 schrieb Brian Paul: Fixes compilation error since 5aea0d691. --- src/gallium/drivers/r300/r300_texture.c | 2 +- 1 file changed, 1 ins

[Mesa-dev] [Bug 94549] [swrast] piglit glsl-arb-fragment-coord-conventions regression

https://bugs.freedesktop.org/show_bug.cgi?id=94549 --- Comment #3 from Vinson Lee --- (In reply to Plamena Manolova from comment #2) > Hi Vinson, > Could you please give the proposed patch a go? The patch fixes the glsl-arb-fragment-coord-convention regression on swrast. Tested-by: Vinson Lee

Re: [Mesa-dev] [PATCH 01/17] gallium: Add PIPE_CAP_MSAA_MODES

On Sat, Mar 19, 2016 at 12:02 PM, Bas Nieuwenhuizen wrote: > On Sat, Mar 19, 2016 at 4:25 PM, Ilia Mirkin wrote: >> On Sat, Mar 19, 2016 at 11:14 AM, Bas Nieuwenhuizen >> wrote: >>> That would limit us to supporting sample counts for which we have >>> texture formats. >>> >>> As far as I underst

[Mesa-dev] [PATCH 1/3] nv50: reset TFB bufctx when we no longer hold a reference to the buffers

This fix is analogous to commit ff085d014. This fixes some use-after-free situations in dEQP when an xfb state is removed, and then a clear is triggered, which only does a partial validation. It would attempt to read the no-longer-valid buffers, resulting in crashes. Signed-off-by: Ilia Mirkin C

[Mesa-dev] [PATCH 3/3] nv50/ir: normalize cube coordinates after derivatives have been computed

In "manual" derivative mode (always used on nv50 and sometimes on nvc0 but always for cube), the idea is that using the quadop instruction, we set up the "other" quads to have values such that the derivatives work out, and then run the texture instruction as if nothing were strange. It pulls values

[Mesa-dev] [PATCH 2/3] nv50/ir: force-enable derivatives on TXD ops

This matters especially in vertex shaders, where derivatives are disabled by default. This fixes textureGrad in vertex shaders on nv50. Signed-off-by: Ilia Mirkin Cc: "11.1 11.2" --- src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nv50.cpp | 4 +++- src/gallium/drivers/nouveau/codegen/nv50

Re: [Mesa-dev] [PATCH 01/17] gallium: Add PIPE_CAP_MSAA_MODES

On Sat, Mar 19, 2016 at 4:25 PM, Ilia Mirkin wrote: > On Sat, Mar 19, 2016 at 11:14 AM, Bas Nieuwenhuizen > wrote: >> That would limit us to supporting sample counts for which we have >> texture formats. >> >> As far as I understand with radeonsi we can support 16 samples without >> any attachmen

Re: [Mesa-dev] [PATCH] nv50/ir: fix compilation warning in handleSharedATOM()

Reviewed-by: Ilia Mirkin On Sat, Mar 19, 2016 at 11:56 AM, Samuel Pitoiset wrote: > In release build mode only, op may be used uninitialized because > the assertion has been removed. > > Signed-off-by: Samuel Pitoiset > --- > src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp | 1 +

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