On Tue, Mar 15, 2016 at 7:29 PM, Nicolai Hähnle <nhaeh...@gmail.com> wrote:
> From: Nicolai Hähnle <nicolai.haeh...@amd.com>
>
> ---
> src/gallium/drivers/radeonsi/si_state.c | 36
> +++++++++++++++++++++++++++++++++
> 1 file changed, 36 insertions(+)
>
> diff --git a/src/gallium/drivers/radeonsi/si_state.c
> b/src/gallium/drivers/radeonsi/si_state.c
> index 0c3fbdc..6dcd532 100644
> --- a/src/gallium/drivers/radeonsi/si_state.c
> +++ b/src/gallium/drivers/radeonsi/si_state.c
> @@ -3521,6 +3521,41 @@ static void si_texture_barrier(struct pipe_context
> *ctx)
> SI_CONTEXT_FLUSH_AND_INV_CB;
> }
>
> +static void si_memory_barrier(struct pipe_context *ctx, unsigned flags)
> +{
> + struct si_context *sctx = (struct si_context *)ctx;
> +
> + /* Subsequent commands must wait for all shader invocations to
> + * complete. */
> + sctx->b.flags |= SI_CONTEXT_PS_PARTIAL_FLUSH;
> +
> + if (flags & PIPE_BARRIER_CONSTANT_BUFFER)
> + sctx->b.flags |= SI_CONTEXT_INV_SMEM_L1;
> +
> + if (flags & (PIPE_BARRIER_VERTEX_BUFFER |
> + PIPE_BARRIER_SHADER_BUFFER |
> + PIPE_BARRIER_TEXTURE |
> + PIPE_BARRIER_IMAGE)) {
> + /* As far as I can tell, L1 contents are written back to L2
> + * automatically at end of shader, but the contents of other
> + * L1 caches might still be stale. */
> + sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1;
The constant buffer can also be read with VMEM if the address comes from a VGPR.
Marek
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