On 09/17/2015 11:09 PM, Kenneth Graunke wrote:
With this patch, if a .shader_test file contains
[require]
...
GL_ARB_separate_shader_objects
then the shader will be compiled using glCreateShaderProgramv, and thus
be a proper separate shader object. Drivers may choose to lay ou
On Thu, Sep 17, 2015 at 8:57 PM, Ilia Mirkin wrote:
> On Thu, Sep 17, 2015 at 8:48 PM, Rob Clark wrote:
>> On Thu, Sep 17, 2015 at 8:35 PM, Dieter Nützel wrote:
>>> Am 18.09.2015 02:27, schrieb Rob Clark:
On Thu, Sep 17, 2015 at 8:03 PM, Timothy Arceri
wrote:
>
> On Thu,
On Thu, Sep 17, 2015 at 8:48 PM, Rob Clark wrote:
> On Thu, Sep 17, 2015 at 8:35 PM, Dieter Nützel wrote:
>> Am 18.09.2015 02:27, schrieb Rob Clark:
>>>
>>> On Thu, Sep 17, 2015 at 8:03 PM, Timothy Arceri
>>> wrote:
On Thu, 2015-09-17 at 18:20 -0400, Rob Clark wrote:
> - /** list
On Thu, Sep 17, 2015 at 8:35 PM, Dieter Nützel wrote:
> Am 18.09.2015 02:27, schrieb Rob Clark:
>>
>> On Thu, Sep 17, 2015 at 8:03 PM, Timothy Arceri
>> wrote:
>>>
>>> On Thu, 2015-09-17 at 18:20 -0400, Rob Clark wrote:
From: Rob Clark
Signed-off-by: Rob Clark
---
Am 18.09.2015 02:27, schrieb Rob Clark:
On Thu, Sep 17, 2015 at 8:03 PM, Timothy Arceri
wrote:
On Thu, 2015-09-17 at 18:20 -0400, Rob Clark wrote:
From: Rob Clark
Signed-off-by: Rob Clark
---
src/glsl/nir/nir.h | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/
On Thu, Sep 17, 2015 at 8:03 PM, Timothy Arceri wrote:
> On Thu, 2015-09-17 at 18:20 -0400, Rob Clark wrote:
>> From: Rob Clark
>>
>> Signed-off-by: Rob Clark
>> ---
>> src/glsl/nir/nir.h | 10 +-
>> 1 file changed, 5 insertions(+), 5 deletions(-)
>>
>> diff --git a/src/glsl/nir/nir.h b
On Thu, 2015-09-17 at 18:20 -0400, Rob Clark wrote:
> From: Rob Clark
>
> Signed-off-by: Rob Clark
> ---
> src/glsl/nir/nir.h | 10 +-
> 1 file changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/src/glsl/nir/nir.h b/src/glsl/nir/nir.h
> index 297858a..9d8c3f4 100644
> --- a/src/
On Thu, 2015-09-17 at 16:25 +0100, Emil Velikov wrote:
> With the only C++ function having it's own wrapper we can 'demote'
> this
> file to a normal C one. This allows us to get rid of extern C {
> support C99 designated initializers in CPP code.
>
> This may cause build issue due to the missing
From: Rob Clark
Signed-off-by: Rob Clark
---
src/glsl/nir/nir_print.c | 30 ++
1 file changed, 30 insertions(+)
diff --git a/src/glsl/nir/nir_print.c b/src/glsl/nir/nir_print.c
index ca8059f..6e86140 100644
--- a/src/glsl/nir/nir_print.c
+++ b/src/glsl/nir/nir_print
From: Rob Clark
Signed-off-by: Rob Clark
---
src/glsl/nir/nir.h | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/src/glsl/nir/nir.h b/src/glsl/nir/nir.h
index 297858a..9d8c3f4 100644
--- a/src/glsl/nir/nir.h
+++ b/src/glsl/nir/nir.h
@@ -1451,13 +1451,13 @@ typedef
Ok, here's v2 of the change, with the suggested edits.
From 5f393faa058f453408dfc640eecae3fe6335dfed Mon Sep 17 00:00:00 2001
From: Arlie Davis
Date: Tue, 15 Sep 2015 09:58:34 -0700
Subject: [PATCH] This patch significantly reduces the size of the libGL.so
binary. It does not change the (extern
I need to build the mangled osmesa for Windows with shared glapi enabled,
otherwise functions like glCreateShader will not work(yes, this is a bug.) But
I can not find any setting to do that with scons. There is a experimental
option gles=yes which will force the shared glapi. But I get build er
remplace clCreateImage2D and clCreateImage3D implementation with call to
clCreateImage
---
src/gallium/state_trackers/clover/api/memory.cpp | 92 +---
1 file changed, 32 insertions(+), 60 deletions(-)
diff --git a/src/gallium/state_trackers/clover/api/memory.cpp
b/src/gallium
---
src/gallium/state_trackers/clover/api/memory.cpp | 117 +--
1 file changed, 107 insertions(+), 10 deletions(-)
diff --git a/src/gallium/state_trackers/clover/api/memory.cpp
b/src/gallium/state_trackers/clover/api/memory.cpp
index 1efb95b..6e95931 100644
--- a/src/gallium/
With this patch, if a .shader_test file contains
[require]
...
GL_ARB_separate_shader_objects
then the shader will be compiled using glCreateShaderProgramv, and thus
be a proper separate shader object. Drivers may choose to lay out the
inputs/outputs of SSO programs slightly differen
On Wed, Sep 16, 2015 at 9:42 AM, Arlie Davis wrote:
> The null check is safe to remove, for two reasons. First, we're allocating
> with calloc, so we know for sure that the entire structure is zero-filled.
> Second, we're assigning every byte of the table, so we don't even need to
> rely on zero-
Patches 1-3
Tested-by: Gottfried Haider
Thanks!
On Thu, Sep 17, 2015 at 5:25 PM, Emil Velikov wrote:
> With the only C++ function having it's own wrapper we can 'demote' this
> file to a normal C one. This allows us to get rid of extern C {
> support C99 designated initializers in CPP code.
>
>
From: Rob Clark
With this, we completely switch over to nir lowering passes instead of
tgsi_lowering. So one step closer to supporting direct glsl or spirv to
nir support for freedreno a3xx/a4xx.
Signed-off-by: Rob Clark
---
.../drivers/freedreno/ir3/ir3_compiler_nir.c | 24 +++-
From: Rob Clark
Signed-off-by: Rob Clark
---
src/glsl/Makefile.sources| 1 +
src/glsl/nir/nir.h | 2 +
src/glsl/nir/nir_lower_two_sided_color.c | 209 +++
3 files changed, 212 insertions(+)
create mode 100644 src/glsl/nir/ni
On Thu, Sep 17, 2015 at 3:15 PM, Eric Anholt wrote:
> Rob Clark writes:
>
>> From: Rob Clark
>>
>> Update of the patchset sent yesterday:
>> 1) rename to nir_lower_tex since it is no longer just lowering
>>projector
>> 2) split configuration options out into nir_lower_tex_options
>> 3) add R
Rob Clark writes:
> From: Rob Clark
>
> Update of the patchset sent yesterday:
> 1) rename to nir_lower_tex since it is no longer just lowering
>projector
> 2) split configuration options out into nir_lower_tex_options
> 3) add RECT lowering (also needed to get coord clamp working
>prope
Boyan Ding writes:
> 2015-08-30 15:07 GMT+08:00 Boyan Ding :
>> Instructions with difference in PM field can actually be paired up if
>> the one without PM doesn't do packing/unpacking and non-NOP
>> packing/unpacking operations from PM instruction aren't added to the
>> other without PM.
>>
>> t
SEL and MOV instructions, as long as they don't have source modifiers, are
just copying bits around. So those kind of instruction could be propagated
even if there are type mismatches. This is needed because NIR generates
integer SEL and MOV instructions whenever it doesn't know what else to
gener
SEL and MOV instructions, as long as they don't have source modifiers, are
just copying bits around. So those kind of instruction could be propagated
even if there are type mismatches. This is needed because NIR generates
integer SEL and MOV instructions whenever it doesn't know what else to
gener
On Thu, Sep 17, 2015 at 3:28 AM, Tapani Pälli
wrote:
> OpenGL ES 3.0 spec 3.7.2 "Transfer of Pixel Rectangles" specifies
> DEPTH_COMPONENT, UNSIGNED_INT as a valid couple, validation for
> internal format is checked by is_float_depth().
>
> Fix regression caused by 81d2fd91a90e5b2fd9fd74792a7a7c3
When updating texture buffers, we might end up replacing the whole
buffer. Check that the tic address matches the resource address, and if
not, update the tic and reupload it.
This fixes:
arb_direct_state_access-texture-buffer
arb_texture_buffer_object-data-sync
Signed-off-by: Ilia Mirkin
Cc
On Wed, Sep 16, 2015 at 8:22 AM, Julien Isorce wrote:
> I added below version4 updates. It works for all codecs expect h264.
> Video is visible but lot of blockiness.
> Can someone with a Radeon confirm that "LIBVA_DRIVER_NAME=gallium mpv
> --hwdec=vaapi"
> is working on h264 videos ?
> I want to
In order to support 16x MSAA, skl+ has a wider version of lcd2dms that
takes two parameters for the MCS data. The MCS data in the response
still fits in a single register so we just need to ensure we copy both
values rather than just the lower one.
---
src/mesa/drivers/dri/i965/brw_vec4.cpp
When 16 samples are used the MCS buffer needs 64 bits per pixel.
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 0cb0632..9faafb4 100644
---
src/mesa/drivers/dri/i965/brw_context.c | 6 ++
src/mesa/drivers/dri/i965/intel_screen.c | 5 -
2 files changed, 10 insertions(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/brw_context.c
b/src/mesa/drivers/dri/i965/brw_context.c
index 7c1c133..c05fb74 100644
--- a/src/mes
The gen7_surface_msaa_bits function already returns the right values
for 16 samples but it just needs its assert to be relaxed.
---
src/mesa/drivers/dri/i965/gen7_wm_surface_state.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.
In order to accomodate 16x MSAA, the starting sample pair index is now
3 bits rather than 2 on SKL+.
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
b/src/mesa/drivers/dri/i965/brw_fs.cpp
ind
When 16x MSAA is used for sampling with texelFetch the compiler needs
to use a different instruction which passes more arguments for the MCS
data. Previously on skl+ it was unconditionally using this new
instruction. However since 16x MSAA is probably going to be pretty
rare, it is probably worthwh
The destination rectangle is now drawn at 4x4 the size and the shader
code to calculate the sample number is adjusted accordingly.
---
src/mesa/drivers/dri/i965/brw_meta_stencil_blit.c | 22 +-
1 file changed, 17 insertions(+), 5 deletions(-)
diff --git a/src/mesa/drivers/dri/
I'm not too sure about the expression used to index into sample_map in
the shader. It looks like if fract(coord.x) and fract(coord.y) are
close to 1.0 then it would index outside of the array. However the
code for 4 and 8 has the same problem and the results seems to look
reasonable. It might make
In order to support 16x MSAA, skl+ has a wider version of lcd2dms that
takes two parameters for the MCS data. This patch makes it allocate a
register that is twice as big for the MCS data and then always use
the wider version.
---
src/mesa/drivers/dri/i965/brw_defines.h| 4
src/mesa/
The maximum message length for a send message is 11. Some of the
sampler message types have more than 5 arguments which means when they
are doubled to accomodate the SIMD16 register size then the message is
too long. This is important for the ld2dms_w message which will be
used in a later patch bec
This is the standard pattern used by the other 3D graphics API.
BDW has slots for these values, but they aren't actually used until
SKL. Even though the documentation for BDW says they must be zero, it
doesn't seem to cause any harm to program them anyway.
The comment above for the 8x sample posi
From: Kenneth Graunke
Signed-off-by: Kenneth Graunke
Reviewed-by: Neil Roberts
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
b/src/mesa/drivers/dri/i965/intel_mipmap_t
I ran the series through Piglit but there are some issues.
The texelFetch test appears to be broken for sample counts > 10 and
needs this patch to work:
http://patchwork.freedesktop.org/patch/59485/
The accuracy tests are failing but I think the problem is just that it
is too strict. I've writte
On Thu, Sep 17, 2015 at 8:48 AM, Rob Clark wrote:
> From: Rob Clark
>
> Signed-off-by: Rob Clark
> ---
> src/glsl/nir/nir.h | 7 +
> src/glsl/nir/nir_lower_tex.c | 66
> ++--
> 2 files changed, 70 insertions(+), 3 deletions(-)
>
> diff --g
On Thu, Sep 10, 2015 at 4:18 PM, Emil Velikov wrote:
> On 4 September 2015 at 19:57, Sedat Dilek wrote:
>> Hi,
>>
>> I compiled a toolchain based on LLVM/Clang v3.7.0 today and tested it
>> with an updated version of my Linux Graphics driver stack (see
>> attached logs).
>>
>> Here on Ubuntu/prec
It allows to call nouveau_vp3_bsp_next multiple times
between one begin/end.
It is required to support st/va.
https://bugs.freedesktop.org/show_bug.cgi?id=89969
Signed-off-by: Julien Isorce
---
src/gallium/drivers/nouveau/nouveau_vp3_video.h| 16 +++-
.../drivers/nouveau/nouveau_vp3_video_
> Or maybe this is enough?
Yes, that seems to make the trick for me.
Thanks!
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/mesa-dev
- split nvc0_decoder_bsp in begin/next/end
- preserve content buffer when calling nvc0_decoder_bsp_next
- implement pipe_video_codec::begin_frame/end_frame
https://bugs.freedesktop.org/show_bug.cgi?id=89969
Signed-off-by: Julien Isorce
---
src/gallium/drivers/nouveau/nouveau_vp3_video.h|
Hi,
I tried to build Mesa 11.0.0 llvmpipe on Windows using LLVM 3.7.
I had to patch the "scons/llvm.py" file and add 'LLVMInstrumentation' to
the libraries to be linked.
Can someone please add that to llvm.py? Appart from this change, it
seems to work fine.
best regards,
Florian
--
--
It fixes asserts like assert(templ->max_references <= 2);
in nvc0_video.c::nvc0_create_decoder
Signed-off-by: Julien Isorce
---
src/gallium/state_trackers/va/context.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/src/gallium/state_trackers/va/context.c
b/src/gallium
vainfo fails in vaDriverInit because "dd_create_screen"
does not reach strcmp(driver_name, "nouveau") code.
Indeed when compiling the va target.c, the macro GALLIUM_NOUVEAU
is not defined.
This patch define the macro the same it is done for dri and
vdpau targets.
Tested with:
./autogen.sh --enable
https://bugs.freedesktop.org/show_bug.cgi?id=89969
Signed-off-by: Julien Isorce
---
src/gallium/drivers/nouveau/nouveau_vp3_video.h | 3 +++
src/gallium/drivers/nouveau/nouveau_vp3_video_bsp.c | 17 +++--
2 files changed, 18 insertions(+), 2 deletions(-)
diff --git a/src/galliu
I added below version4 updates. It works for all codecs expect h264.
Video is visible but lot of blockiness.
Can someone with a Radeon confirm that "LIBVA_DRIVER_NAME=gallium mpv
--hwdec=vaapi"
is working on h264 videos ?
I want to make sure it is not a bug in st/va.
v4:
Update caps after number
*** BLURB HERE ***
Julien Isorce (6):
nouveau: split nouveau_vp3_bsp in begin/next/end
nvc0: add support for st/va
nouveau: fix chunk decoding by updating number of slices
st/va: properly set max number of ref frames
build: enable st/va with nouveau driver
WIP: implement vaapi export /
On 17 September 2015 at 14:34, Rob Clark wrote:
> On Thu, Sep 17, 2015 at 9:27 AM, Emil Velikov
> wrote:
>> Hi Gottfried,
>>
>> On 17 September 2015 at 13:42, Gottfried Haider
>> wrote:
>>> I am getting this error on 7e286506 - comping mesa used to work fine
>>> on this system a couple of weeks
Cc: Gottfried Haider
Signed-off-by: Emil Velikov
---
src/glsl/nir/nir_types.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/glsl/nir/nir_types.h b/src/glsl/nir/nir_types.h
index a8ff8f2..bf2faf4 100644
--- a/src/glsl/nir/nir_types.h
+++ b/src/glsl/nir/nir_types.h
@@
This will allow us to convert nir_lower_sampler.cpp to C.
Cc: Gottfried Haider
Signed-off-by: Emil Velikov
---
src/glsl/nir/nir_types.cpp | 7 +++
src/glsl/nir/nir_types.h | 2 ++
2 files changed, 9 insertions(+)
diff --git a/src/glsl/nir/nir_types.cpp b/src/glsl/nir/nir_types.cpp
index
With the only C++ function having it's own wrapper we can 'demote' this
file to a normal C one. This allows us to get rid of extern C {
support C99 designated initializers in CPP code.
This may cause build issue due to the missing dependency. If doing
incremental build run the following:
sed -i -
On Thu, Sep 17, 2015 at 1:09 AM, Eduardo Lima Mitev wrote:
> On 09/15/2015 10:44 PM, Jason Ekstrand wrote:
>> The idea here is not that it gives register coalescing a little bit of a
>> helping hand. It doesn't actually fix the coalescing problems, but it
>> seems to help a good bit.
>>
>> Shader
Rob Clark writes:
> From: Rob Clark
>
> Some hardware, such as adreno a3xx, supports txp on some but not all
> sampler types. In this case we want more fine grained control over
> which texture projectors get lowered.
In the subject, s/add //
signature.asc
Description: PGP signature
On Thu, Sep 17, 2015 at 3:27 PM, Emil Velikov wrote:
> Hi Gottfried,
>
> On 17 September 2015 at 13:42, Gottfried Haider
> wrote:
>> I am getting this error on 7e286506 - comping mesa used to work fine
>> on this system a couple of weeks ago
>>
>> CXXnir/nir_lower_samplers.lo
>> CC ni
On Thu, Sep 17, 2015 at 9:27 AM, Emil Velikov wrote:
> Hi Gottfried,
>
> On 17 September 2015 at 13:42, Gottfried Haider
> wrote:
>> I am getting this error on 7e286506 - comping mesa used to work fine
>> on this system a couple of weeks ago
>>
>> CXXnir/nir_lower_samplers.lo
>> CC ni
Hi Gottfried,
On 17 September 2015 at 13:42, Gottfried Haider
wrote:
> I am getting this error on 7e286506 - comping mesa used to work fine
> on this system a couple of weeks ago
>
> CXXnir/nir_lower_samplers.lo
> CC nir/nir_lower_system_values.lo
> In file included from nir/nir_lower
From: Rob Clark
Some hardware needs to clamp texture coordinates to [0.0, 1.0] in the
shader to emulate GL_CLAMP. This is added to lower_tex_proj since, in
the case of projected coords, the clamping needs to happen *after*
projection.
Signed-off-by: Rob Clark
---
src/glsl/nir/nir.h
From: Rob Clark
Split this out to reduce noise in later patches.
Signed-off-by: Rob Clark
---
src/glsl/nir/nir_lower_tex.c | 146 +++
1 file changed, 77 insertions(+), 69 deletions(-)
diff --git a/src/glsl/nir/nir_lower_tex.c b/src/glsl/nir/nir_lower_te
From: Rob Clark
Since the following patches will add additional tex-lowering related
functionality, which doesn't make sense to split out into a separate
pass (as they would require duplication of the projector lowering
logic), let's give this pass a more generic name.
Signed-off-by: Rob Clark
From: Rob Clark
Some hardware, such as adreno a3xx, supports txp on some but not all
sampler types. In this case we want more fine grained control over
which texture projectors get lowered.
v2: split out nir_lower_tex_options struct to make it easier to
add the additional parameters coming in t
From: Rob Clark
Signed-off-by: Rob Clark
---
src/glsl/nir/nir.h | 7 +
src/glsl/nir/nir_lower_tex.c | 66 ++--
2 files changed, 70 insertions(+), 3 deletions(-)
diff --git a/src/glsl/nir/nir.h b/src/glsl/nir/nir.h
index 04dfc97..a40dbae 10
From: Rob Clark
Update of the patchset sent yesterday:
1) rename to nir_lower_tex since it is no longer just lowering
projector
2) split configuration options out into nir_lower_tex_options
3) add RECT lowering (also needed to get coord clamp working
properly for RECT textures
Rob Clark (6
From: Rob Clark
Signed-off-by: Rob Clark
---
src/gallium/drivers/freedreno/a3xx/fd3_texture.c | 8 +++-
src/gallium/drivers/freedreno/a4xx/fd4_texture.c | 8 +++-
.../drivers/freedreno/ir3/ir3_compiler_nir.c | 56 --
3 files changed, 44 insertions(+), 28 deletion
I am getting this error on 7e286506 - comping mesa used to work fine
on this system a couple of weeks ago
CXXnir/nir_lower_samplers.lo
CC nir/nir_lower_system_values.lo
In file included from nir/nir_lower_samplers.cpp:27:0:
nir/nir_builder.h: In function 'nir_ssa_def*
nir_imm_float(nir
Check for PIPE_FORMAT_R8_UNORM when setting up the copy shader.
Also re-enable the dest alpha blending with A8 destination that
actually turned out to be correct.
Verified using rendercheck that the composite operators
overreverse, in, out, atop, atopreverse and xor seem to work fine
with a8 desti
On 09/17/2015 02:10 PM, Iago Toral wrote:
Hi Tapani, Kevin,
awesome work! I was curious about how to fix this, at least when I was
looking at the specs for this stuff it was not obvious that the Math
involved for this was so different, I only recall seeing the reference
that texure coordinates
Check for PIPE_FORMAT_R8_UNORM when setting up the copy shader.
Also re-enable the dest alpha blending with A8 destination that
actually turned out to be correct.
Verified using rendercheck that the composite operators
overreverse, in, out, atop, atopreverse and xor seem to work fine
with a8 desti
On 17/09/15 10:58, Thomas Hellstrom wrote:
On 09/17/2015 11:53 AM, Thomas Hellstrom wrote:
On 09/17/2015 11:34 AM, Jose Fonseca wrote:
On 16/09/15 14:04, Thomas Hellstrom wrote:
XA has been using L8_UNORM for a8 and yuv component surfaces.
This commit instead makes XA prefer R8_UNORM since it'
On 16 September 2015 at 21:14, Oded Gabbay wrote:
> On Tue, Sep 15, 2015 at 4:23 PM, Ulrich Weigand wrote:
>>
>> Various pieces of code to create compressed textures will first
>> generate an uncompressed RGBA texture into a temporary buffer,
>> and then read from that buffer while creating the f
On Wed, 2015-09-16 at 12:32 -0700, Kenneth Graunke wrote:
> On Wednesday, September 16, 2015 11:17:53 AM Iago Toral Quiroga wrote:
> > It seems that we have some bugs where we fail to compile shaders in gen6
> > because we do not having enough MRF registers available (see bugs 86469 and
> > 90631 f
Hi Tapani, Kevin,
awesome work! I was curious about how to fix this, at least when I was
looking at the specs for this stuff it was not obvious that the Math
involved for this was so different, I only recall seeing the reference
that texure coordinates had to be normalized to a [-1, 1] space after
OpenGL ES 3.0 spec 3.7.2 "Transfer of Pixel Rectangles" specifies
DEPTH_COMPONENT, UNSIGNED_INT as a valid couple, validation for
internal format is checked by is_float_depth().
Fix regression caused by 81d2fd91a90e5b2fd9fd74792a7a7c329f0e4d29 in:
ES3-CTS.gtf.GL3Tests.packed_pixels.packed_pixel
Reviewed-by: Marta Lofstedt
> -Original Message-
> From: mesa-dev [mailto:mesa-dev-boun...@lists.freedesktop.org] On
> Behalf Of Timothy Arceri
> Sent: Thursday, September 17, 2015 9:03 AM
> To: mesa-dev@lists.freedesktop.org
> Subject: [Mesa-dev] [PATCH 22/24] glsl: Allow arrays of arra
https://bugs.freedesktop.org/show_bug.cgi?id=92022
Frederic Romagne changed:
What|Removed |Added
CC||frederic.roma...@gmail.com
--
You ar
On 09/17/2015 11:53 AM, Thomas Hellstrom wrote:
> On 09/17/2015 11:34 AM, Jose Fonseca wrote:
>> On 16/09/15 14:04, Thomas Hellstrom wrote:
>>> XA has been using L8_UNORM for a8 and yuv component surfaces.
>>> This commit instead makes XA prefer R8_UNORM since it's assumed to
>>> have a
>>> higher
On 09/17/2015 11:34 AM, Jose Fonseca wrote:
> On 16/09/15 14:04, Thomas Hellstrom wrote:
>> XA has been using L8_UNORM for a8 and yuv component surfaces.
>> This commit instead makes XA prefer R8_UNORM since it's assumed to
>> have a
>> higher availability.
>>
>> Also neither of these formats are s
On 16/09/15 14:04, Thomas Hellstrom wrote:
XA has been using L8_UNORM for a8 and yuv component surfaces.
This commit instead makes XA prefer R8_UNORM since it's assumed to have a
higher availability.
Also neither of these formats are suitable as destination formats using
destination alpha blendi
On Thu, Sep 17, 2015 at 11:15 AM, Erik Faye-Lund wrote:
> On Wed, Sep 16, 2015 at 11:00 PM, Dave Airlie wrote:
>> This reverts commit 48961fa3ba37999a6f8fd812458b735e39604a95.
>
>> I also don't have a copy of this patch in my mail archive, which
>> seems wierd, did it get posted to mesa-dev?
>
>
On Wed, Sep 16, 2015 at 11:00 PM, Dave Airlie wrote:
> This reverts commit 48961fa3ba37999a6f8fd812458b735e39604a95.
> I also don't have a copy of this patch in my mail archive, which
> seems wierd, did it get posted to mesa-dev?
The same applies to 8200793 ("mesa/teximage: restrict GL_ETC1_RGB8
On 09/15/2015 10:44 PM, Jason Ekstrand wrote:
> The provided indices have the very nice property that if A dominates B then
> A->index <= B->index. We should document that somewhere.
>
> Reviewed-by: Kenneth Graunke
> ---
> src/glsl/nir/nir.c | 8
> 1 file changed, 8 insertions(+)
>
>
On 09/15/2015 10:44 PM, Jason Ekstrand wrote:
> The idea here is not that it gives register coalescing a little bit of a
> helping hand. It doesn't actually fix the coalescing problems, but it
> seems to help a good bit.
>
> Shader-db results for vec4 programs on Haswell:
>
>total instructio
https://bugs.freedesktop.org/show_bug.cgi?id=79783
--- Comment #6 from gregory.hain...@gmail.com ---
Hum, it could be related to item4 (assign_varying_locations).
/* Operate in a total of four passes.
*
* 1. Sort inputs / outputs into a canonical order. This is necessary so
*
https://bugs.freedesktop.org/show_bug.cgi?id=79783
gregory.hain...@gmail.com changed:
What|Removed |Added
CC||gregory.hain...@gmail.com
---
---
src/mesa/drivers/dri/i965/intel_extensions.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/mesa/drivers/dri/i965/intel_extensions.c
b/src/mesa/drivers/dri/i965/intel_extensions.c
index e6d39e0..9f9c6ed 100644
--- a/src/mesa/drivers/dri/i965/intel_extensions.c
+++ b/src/mesa/drivers/
Reviewed-by: Ian Romanick
---
docs/GL3.txt | 4 ++--
docs/relnotes/11.1.0.html | 1 +
2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/docs/GL3.txt b/docs/GL3.txt
index bd44d12..1cb7958 100644
--- a/docs/GL3.txt
+++ b/docs/GL3.txt
@@ -149,7 +149,7 @@ GL 4.2, GLSL 4.20:
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 4 ++--
src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 3 ++-
2 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
b/src/mesa/drivers/dri/i965/brw_fs.cpp
index b4d0567..b21c576 100644
--- a/src/mesa/drivers/
---
src/glsl/ast_function.cpp | 43 ++-
src/glsl/lower_subroutine.cpp | 2 +-
2 files changed, 39 insertions(+), 6 deletions(-)
diff --git a/src/glsl/ast_function.cpp b/src/glsl/ast_function.cpp
index d003655..42affad 100644
--- a/src/glsl/ast_function
V3: use a check_*_allowed style function for requirements checking
rather than has_* which doesn't encapsulate the error message
V2: add missing 's' to the extension name in error messages
and add decimal place in version string
---
src/glsl/ast_to_hir.cpp | 7 +--
src/glsl/glsl_parse
---
src/glsl/link_uniforms.cpp | 77 +-
1 file changed, 49 insertions(+), 28 deletions(-)
diff --git a/src/glsl/link_uniforms.cpp b/src/glsl/link_uniforms.cpp
index bdc28cc..94161e7 100644
--- a/src/glsl/link_uniforms.cpp
+++ b/src/glsl/link_uniforms.cp
---
src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 45
1 file changed, 29 insertions(+), 16 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
index f8133a5..6ef0703 100644
--- a/src/mesa/drivers/dri/i965/brw
---
src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 22 +-
1 file changed, 17 insertions(+), 5 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
index 0465770..733d5ad 100644
--- a/src/mesa/drivers/dri/i
Since commit c0cd5b var->data.binding was being used as a replacement
for atomic buffer index, but they don't have to be the same value they
just happen to end up the same when binding is 0.
Now that we store the atomic uniform location in var->data.location
we can use this to lookup the atomic bu
This allows the correct offset to be calculated for use in indirect
indexing of samplers.
---
src/glsl/glsl_types.cpp | 16 +++-
1 file changed, 15 insertions(+), 1 deletion(-)
diff --git a/src/glsl/glsl_types.cpp b/src/glsl/glsl_types.cpp
index 97c79fa..86f0ea5 100644
--- a/src/glsl/
Desktop GL supports interface block AoA however AMD and Nvidia
dont support it in their drivers curently so we can get away
with disabling it for now.
V2: make error message more clear that this is a fault in Mesa and
not with the application
---
src/glsl/ast_to_hir.cpp | 10 ++
1 file ch
Also add TODO comment about adding proper support
Signed-off-by: Timothy Arceri
---
src/glsl/ir_set_program_inouts.cpp | 6 ++
1 file changed, 6 insertions(+)
diff --git a/src/glsl/ir_set_program_inouts.cpp
b/src/glsl/ir_set_program_inouts.cpp
index b7a0f6e..d7c29b0 100644
--- a/src/glsl/i
Reviewed-by: Tapani Pälli
Reviewed-by: Ian Romanick
---
src/glsl/nir/nir_types.cpp | 6 ++
src/glsl/nir/nir_types.h | 2 ++
2 files changed, 8 insertions(+)
diff --git a/src/glsl/nir/nir_types.cpp b/src/glsl/nir/nir_types.cpp
index 940c676..da7015b 100644
--- a/src/glsl/nir/nir_types.cpp
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