From: Rob Clark <robcl...@freedesktop.org>

Signed-off-by: Rob Clark <robcl...@freedesktop.org>
---
 src/gallium/drivers/freedreno/a3xx/fd3_texture.c   |  8 +++-
 src/gallium/drivers/freedreno/a4xx/fd4_texture.c   |  8 +++-
 .../drivers/freedreno/ir3/ir3_compiler_nir.c       | 56 ++++++++++++----------
 3 files changed, 44 insertions(+), 28 deletions(-)

diff --git a/src/gallium/drivers/freedreno/a3xx/fd3_texture.c 
b/src/gallium/drivers/freedreno/a3xx/fd3_texture.c
index 2d6ecb2..c9951dc 100644
--- a/src/gallium/drivers/freedreno/a3xx/fd3_texture.c
+++ b/src/gallium/drivers/freedreno/a3xx/fd3_texture.c
@@ -87,6 +87,7 @@ fd3_sampler_state_create(struct pipe_context *pctx,
 {
        struct fd3_sampler_stateobj *so = CALLOC_STRUCT(fd3_sampler_stateobj);
        unsigned aniso = util_last_bit(MIN2(cso->max_anisotropy >> 1, 8));
+       bool normalized_coords = cso->normalized_coords;
        bool miplinear = false;
        bool clamp_to_edge;
 
@@ -111,10 +112,15 @@ fd3_sampler_state_create(struct pipe_context *pctx,
                so->saturate_s = (cso->wrap_s == PIPE_TEX_WRAP_CLAMP);
                so->saturate_t = (cso->wrap_t == PIPE_TEX_WRAP_CLAMP);
                so->saturate_r = (cso->wrap_r == PIPE_TEX_WRAP_CLAMP);
+               /* if any component is clamped in tex-lowering pass, it
+                * is automatically converted from RECT->2D:
+                */
+               if (so->saturate_s || so->saturate_t || so->saturate_r)
+                       normalized_coords = true;
        }
 
        so->texsamp0 =
-                       COND(!cso->normalized_coords, 
A3XX_TEX_SAMP_0_UNNORM_COORDS) |
+                       COND(!normalized_coords, A3XX_TEX_SAMP_0_UNNORM_COORDS) 
|
                        COND(!cso->seamless_cube_map, 
A3XX_TEX_SAMP_0_CUBEMAPSEAMLESSFILTOFF) |
                        COND(miplinear, A3XX_TEX_SAMP_0_MIPFILTER_LINEAR) |
                        A3XX_TEX_SAMP_0_XY_MAG(tex_filter(cso->mag_img_filter, 
aniso)) |
diff --git a/src/gallium/drivers/freedreno/a4xx/fd4_texture.c 
b/src/gallium/drivers/freedreno/a4xx/fd4_texture.c
index dbff5a7..1ebb413 100644
--- a/src/gallium/drivers/freedreno/a4xx/fd4_texture.c
+++ b/src/gallium/drivers/freedreno/a4xx/fd4_texture.c
@@ -87,6 +87,7 @@ fd4_sampler_state_create(struct pipe_context *pctx,
 {
        struct fd4_sampler_stateobj *so = CALLOC_STRUCT(fd4_sampler_stateobj);
        unsigned aniso = util_last_bit(MIN2(cso->max_anisotropy >> 1, 8));
+       bool normalized_coords = cso->normalized_coords;
        bool miplinear = false;
        bool clamp_to_edge;
 
@@ -111,6 +112,11 @@ fd4_sampler_state_create(struct pipe_context *pctx,
                so->saturate_s = (cso->wrap_s == PIPE_TEX_WRAP_CLAMP);
                so->saturate_t = (cso->wrap_t == PIPE_TEX_WRAP_CLAMP);
                so->saturate_r = (cso->wrap_r == PIPE_TEX_WRAP_CLAMP);
+               /* if any component is clamped in tex-lowering pass, it
+                * is automatically converted from RECT->2D:
+                */
+               if (so->saturate_s || so->saturate_t || so->saturate_r)
+                       normalized_coords = true;
        }
 
        so->texsamp0 =
@@ -124,7 +130,7 @@ fd4_sampler_state_create(struct pipe_context *pctx,
 
        so->texsamp1 =
 //             COND(miplinear, A4XX_TEX_SAMP_1_MIPFILTER_LINEAR_FAR) |
-               COND(!cso->normalized_coords, A4XX_TEX_SAMP_1_UNNORM_COORDS);
+               COND(!normalized_coords, A4XX_TEX_SAMP_1_UNNORM_COORDS);
 
        if (cso->min_mip_filter != PIPE_TEX_MIPFILTER_NONE) {
                so->texsamp1 |=
diff --git a/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c 
b/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
index d72464f..c609d3c 100644
--- a/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
+++ b/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
@@ -127,10 +127,10 @@ struct ir3_compile {
 static struct ir3_instruction * create_immed(struct ir3_block *block, uint32_t 
val);
 static struct ir3_block * get_block(struct ir3_compile *ctx, nir_block 
*nblock);
 
-static struct nir_shader *to_nir(const struct tgsi_token *tokens,
-               struct ir3_shader_variant *so)
+static struct nir_shader *to_nir(struct ir3_compile *ctx,
+               const struct tgsi_token *tokens, struct ir3_shader_variant *so)
 {
-       struct nir_shader_compiler_options options = {
+       static const nir_shader_compiler_options options = {
                        .lower_fpow = true,
                        .lower_fsat = true,
                        .lower_scmp = true,
@@ -138,8 +138,33 @@ static struct nir_shader *to_nir(const struct tgsi_token 
*tokens,
                        .lower_ffract = true,
                        .native_integers = true,
        };
+       struct nir_lower_tex_options tex_options = {
+                       .lower_rect = 0,
+       };
        bool progress;
 
+       switch (so->type) {
+       case SHADER_FRAGMENT:
+       case SHADER_COMPUTE:
+               tex_options.saturate_s = so->key.fsaturate_s;
+               tex_options.saturate_t = so->key.fsaturate_t;
+               tex_options.saturate_r = so->key.fsaturate_r;
+               break;
+       case SHADER_VERTEX:
+               tex_options.saturate_s = so->key.vsaturate_s;
+               tex_options.saturate_t = so->key.vsaturate_t;
+               tex_options.saturate_r = so->key.vsaturate_r;
+               break;
+       }
+
+       if (ctx->compiler->gpu_id >= 400) {
+               /* a4xx seems to have *no* sam.p */
+               tex_options.lower_txp = ~0;  /* lower all txp */
+       } else {
+               /* a3xx just needs to avoid sam.p for 3d tex */
+               tex_options.lower_txp = (1 << GLSL_SAMPLER_DIM_3D);
+       }
+
        struct nir_shader *s = tgsi_to_nir(tokens, &options);
 
        if (fd_mesa_debug & FD_DBG_OPTMSGS) {
@@ -155,6 +180,7 @@ static struct nir_shader *to_nir(const struct tgsi_token 
*tokens,
        } else if (s->stage == MESA_SHADER_FRAGMENT) {
                nir_lower_clip_fs(s, so->key.ucp_enables);
        }
+       nir_lower_tex(s, &tex_options);
        nir_lower_idiv(s);
        nir_lower_load_const_to_scalar(s);
 
@@ -196,28 +222,6 @@ lower_tgsi(struct ir3_compile *ctx, const struct 
tgsi_token *tokens,
                        .color_two_side = so->key.color_two_side,
        };
 
-       switch (so->type) {
-       case SHADER_FRAGMENT:
-       case SHADER_COMPUTE:
-               lconfig.saturate_s = so->key.fsaturate_s;
-               lconfig.saturate_t = so->key.fsaturate_t;
-               lconfig.saturate_r = so->key.fsaturate_r;
-               break;
-       case SHADER_VERTEX:
-               lconfig.saturate_s = so->key.vsaturate_s;
-               lconfig.saturate_t = so->key.vsaturate_t;
-               lconfig.saturate_r = so->key.vsaturate_r;
-               break;
-       }
-
-       if (ctx->compiler->gpu_id >= 400) {
-               /* a4xx seems to have *no* sam.p */
-               lconfig.lower_TXP = ~0;  /* lower all txp */
-       } else {
-               /* a3xx just needs to avoid sam.p for 3d tex */
-               lconfig.lower_TXP = (1 << TGSI_TEXTURE_3D);
-       }
-
        return tgsi_transform_lowering(&lconfig, tokens, &info);
 }
 
@@ -257,7 +261,7 @@ compile_init(struct ir3_compiler *compiler,
        lowered_tokens = lower_tgsi(ctx, tokens, so);
        if (!lowered_tokens)
                lowered_tokens = tokens;
-       ctx->s = to_nir(lowered_tokens, so);
+       ctx->s = to_nir(ctx, lowered_tokens, so);
 
        if (lowered_tokens != tokens)
                free((void *)lowered_tokens);
-- 
2.4.3

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