On 01.09.2014 19:08, Marek Olšák wrote:
On Wed, Aug 27, 2014 at 10:57 AM, Michel Dänzer wrote:
From: Michel Dänzer
It's never used under normal circumstances.
Signed-off-by: Michel Dänzer
---
src/gallium/drivers/radeonsi/si_pipe.c | 7 ---
src/gallium/drivers/radeonsi/si_state.c |
Yep, it should be allocating just the pointers.
Reviewed-by: Tapani Pälli
On 09/02/2014 02:22 AM, Dave Airlie wrote:
> From: Dave Airlie
>
> Coverity reported this, and I think this is the right solution,
> since cache->items is struct cache_item ** not struct cache_item *,
> we also realloc it
On lun, 2014-09-01 at 11:17 -0700, Kenneth Graunke wrote:
> On Thursday, August 14, 2014 01:11:39 PM Iago Toral Quiroga wrote:
> > This implements the FF_SYNC message required in gen6 geometry shaders to
> > get the initial URB handle.
> > ---
> > src/mesa/drivers/dri/i965/brw_defines.h
Reviewed-by: Tapani Pälli
On 09/02/2014 02:55 AM, Dave Airlie wrote:
> From: Dave Airlie
>
> If we fails in reserve_explicit_locations, we leak uniform_map.
>
> Reported-by: coverity scanner.
>
> Signed-off-by: Dave Airlie
> ---
> src/glsl/linker.cpp | 4 +++-
> 1 file changed, 3 insertions(+)
https://bugs.freedesktop.org/show_bug.cgi?id=82327
Vinson Lee changed:
What|Removed |Added
Status|NEW |RESOLVED
Resolution|---
https://bugs.freedesktop.org/show_bug.cgi?id=83382
Priority: medium
Bug ID: 83382
Assignee: mesa-dev@lists.freedesktop.org
Summary: /usr/include/string.h:82:1: error: unknown type name
'__extern_always_inline'
Severity: norma
https://bugs.freedesktop.org/show_bug.cgi?id=83381
Priority: medium
Bug ID: 83381
Assignee: mesa-dev@lists.freedesktop.org
Summary: dri_screen.c:72:10: error: expected '}'
Severity: normal
Classification: Unclassified
OS: Lin
Oops.
Reviewed-by: Chris Forbes
On Tue, Sep 2, 2014 at 12:14 PM, Dave Airlie wrote:
> From: Dave Airlie
>
> coverity reported this, Matt said it look like missing parens,
> not bad identing, so lets try that.
>
> Signed-off-by: Dave Airlie
> ---
> src/mesa/drivers/dri/i965/brw_vec4_visitor.c
From: Dave Airlie
coverity reported this, Matt said it look like missing parens,
not bad identing, so lets try that.
Signed-off-by: Dave Airlie
---
src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/brw
From: Dave Airlie
If we fails in reserve_explicit_locations, we leak uniform_map.
Reported-by: coverity scanner.
Signed-off-by: Dave Airlie
---
src/glsl/linker.cpp | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/src/glsl/linker.cpp b/src/glsl/linker.cpp
index d5473ad..5
coverity gives out that we initialize a bunch of fields in the
ir_variable constructor,
but we don't initialize a bunch more of them,
precise, assigned etc.
Someone should probably take a look who knows C++ better than me :-)
Dave.
___
mesa-dev mailing
From: Dave Airlie
Coverity reported this, looks wrong to me.
Signed-off-by: Dave Airlie
---
src/gallium/state_trackers/omx/vid_dec_h264.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/gallium/state_trackers/omx/vid_dec_h264.c
b/src/gallium/state_trackers/omx/vid_dec_
On Sat, 2014-08-16 at 13:13 +0300, Francisco Jerez wrote:
> Jan Vesely writes:
>
> > On Thu, 2014-08-07 at 16:02 +0300, Francisco Jerez wrote:
> >> Jan Vesely writes:
> >>
> >> > This respin includes Francisco's approach of providing implicit
> >> > in the arg vector passed from clover, and Tom
From: Dave Airlie
Coverity reported this, and I think this is the right solution,
since cache->items is struct cache_item ** not struct cache_item *,
we also realloc it using struct cache_item * at some point.
Signed-off-by: Dave Airlie
---
src/mesa/program/prog_cache.c | 2 +-
1 file changed,
From: Dave Airlie
Did this code mean to do something else, you tell me!
Signed-off-by: Dave Airlie
---
src/gallium/drivers/r300/r300_render.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/src/gallium/drivers/r300/r300_render.c
b/src/gallium/drivers/r300/r300_render.c
index 6e5b381..4c9
On Mon, Sep 1, 2014 at 7:08 PM, Dave Airlie wrote:
> From: Dave Airlie
>
> This one path doesn't goto fail, so it seems to leak dec.
>
> Signed-off-by: Dave Airlie
Reviewed-by: Ilia Mirkin
> ---
> src/gallium/drivers/nouveau/nouveau_video.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletio
From: Dave Airlie
Coverity reported this, I'm not sure this patch is correct, but I'm sure
someone who knows can fix this or push my fix.
Signed-off-by: Dave Airlie
---
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mesa/dri
From: Dave Airlie
This one path doesn't goto fail, so it seems to leak dec.
Signed-off-by: Dave Airlie
---
src/gallium/drivers/nouveau/nouveau_video.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/gallium/drivers/nouveau/nouveau_video.c
b/src/gallium/drivers/nouveau/
From: Dave Airlie
Coverity pointed out we never dropped the lock here, so fix
it by using a common exit path.
Signed-off-by: Dave Airlie
---
src/gallium/state_trackers/vdpau/mixer.c | 38 ++--
1 file changed, 26 insertions(+), 12 deletions(-)
diff --git a/src/galli
Ken,
I think you were concerned about:
[PATCH v2 06/14] i965/gen8: Enable hiz for all depth levels
but, you weren't able to reproduce any issues with it.
Should we try this series on master now that 10.3 has branched?
-Jordan
On Mon, Jul 21, 2014 at 11:00 PM, Jordan Justen
wrote:
> 1. No longe
Hi Emil,
The first attachment is the patch for 10.2. The other two patches fix
build with latest LLVM for 10.2.
Marek
On Tue, Aug 26, 2014 at 10:09 PM, Emil Velikov wrote:
> On 06/08/14 17:16, Alex Deucher wrote:
>> On Mon, Aug 4, 2014 at 6:48 AM, Andreas Boll
>> wrote:
>>> The initial firmwa
Requires evergreen/cayman
Signed-off-by: Glenn Kennard
---
This patch depends on r600g: Implement GL_ARB_sample_shading
Implementation note: interpolateAtSample/Offset is doing affine
rather than perspective correct reverse projection, I think for
the small intra-pixel offsets used this should t
Pushed, thanks.
Marek
On Mon, Aug 25, 2014 at 11:05 AM, Glenn Kennard wrote:
> Requires Evergreen or later hardware.
>
> Signed-off-by: Glenn Kennard
> ---
> docs/GL3.txt | 2 +-
> src/gallium/drivers/r600/evergreen_state.c | 4 ++--
> src/gallium/drivers/r600/r
https://bugs.freedesktop.org/show_bug.cgi?id=66184
Marek Olšák changed:
What|Removed |Added
Status|NEW |RESOLVED
Resolution|---
The set of variable defs does not need to be ordered in any way, and
removing/adding elements is a fairly common operation in various
optimization passes.
This shortens runtime of piglit test fp-long-alu to ~11s from ~22s
No piglit regressions observed on nvc0!
Signed-off-by: Tobias Klausmann
-
On Thursday, August 14, 2014 01:11:39 PM Iago Toral Quiroga wrote:
> This implements the FF_SYNC message required in gen6 geometry shaders to
> get the initial URB handle.
> ---
> src/mesa/drivers/dri/i965/brw_defines.h | 14 +
> src/mesa/drivers/dri/i965/brw_shader.cpp |
From: Marek Olšák
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=82538
Cc: mesa-sta...@lists.freedesktop.org
---
src/mesa/main/attrib.c | 4
1 file changed, 4 insertions(+)
diff --git a/src/mesa/main/attrib.c b/src/mesa/main/attrib.c
index c656845..2e289b6 100644
--- a/src/mesa/ma
Am 01.09.2014 18:53, schrieb Ilia Mirkin:
> On Mon, Sep 1, 2014 at 12:47 PM, Roland Scheidegger
> wrote:
>> Am 01.09.2014 18:19, schrieb Ilia Mirkin:
>>> On Mon, Sep 1, 2014 at 12:00 PM, Roland Scheidegger
>>> wrote:
Am 29.08.2014 22:44, schrieb Ilia Mirkin:
> Hello,
>
> I've b
On Thursday, August 14, 2014 01:11:45 PM Iago Toral Quiroga wrote:
> We have GS_OPCODE_SET_DWORD_2_IMMED but this requires its source argument to
> be
> an immediate. In gen6 we need to set dword 2 of the URB write message header
> from values stored in separate register, so we need something more
On Monday, September 01, 2014 07:45:26 PM Dave Airlie wrote:
> Possible resource leak reported by coverity.
>
> Reported-by: Coverity scanner.
> Signed-off-by: Dave Airlie
> ---
> src/loader/loader.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/src/loader/loader.c b/
On Monday, September 01, 2014 01:36:16 AM Jason Ekstrand wrote:
> ---
> src/mesa/drivers/dri/i965/brw_fs.cpp | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
> b/src/mesa/drivers/dri/i965/brw_fs.cpp
> index 43aee66..8b76c3e 100644
The current code... makes no sense. Use nouveau_bo_ref to attach the bo
to the exposed resource so as to have the proper lifetime guarantees.
Tested-by: Emil Velikov
Signed-off-by: Ilia Mirkin
Cc: "10.2 10.3"
---
src/gallium/drivers/nouveau/nv50/nv84_video.c | 13 +
1 file changed,
The mt address is about to be used more, make sure it's set
appropriately.
Reported-by: Emil Velikov
Tested-by: Emil Velikov
Signed-off-by: Ilia Mirkin
Cc: "10.2 10.3"
---
src/gallium/drivers/nouveau/nv50/nv84_video.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/src/gallium/drivers/n
With VP2, nv50_miptree is faked because the underlying bo's have to be
laid out in a certain way. This is done by adjusting the address. Make
sure that blits (and everything else for consistency) use the mt address
rather than the bo address as a base.
This fixes retrieving chroma plane with VDPAU
On Mon, Sep 1, 2014 at 12:47 PM, Roland Scheidegger wrote:
> Am 01.09.2014 18:19, schrieb Ilia Mirkin:
>> On Mon, Sep 1, 2014 at 12:00 PM, Roland Scheidegger
>> wrote:
>>> Am 29.08.2014 22:44, schrieb Ilia Mirkin:
Hello,
I've been thinking a bit about how to properly implement TCS
Am 01.09.2014 18:19, schrieb Ilia Mirkin:
> On Mon, Sep 1, 2014 at 12:00 PM, Roland Scheidegger
> wrote:
>> Am 29.08.2014 22:44, schrieb Ilia Mirkin:
>>> Hello,
>>>
>>> I've been thinking a bit about how to properly implement TCS outputs
>>> in TGSI. As a quick reminder, there are per-vertex (i.e
This starts the process of generalizing the scalar code gen so it can
be used for other stages beyond FS.
These changes are enough to allow code for a basic compute shader to
be generated. (With some more CS patches added...)
No piglit regressions were seen on gen7.
git://people.freedesktop.org/
All fields were migrated from brw_wm_prog_data. In future updates, we can move
these FS specific fields back into brw_wm_prog_data.
The scalar_visitor and scalar_generator class mainly use these structures now.
Signed-off-by: Jordan Justen
---
src/mesa/drivers/dri/i965/Makefile.sources
Signed-off-by: Jordan Justen
---
src/mesa/drivers/dri/i965/brw_blorp_blit_eu.h | 2 +-
src/mesa/drivers/dri/i965/brw_fs.cpp | 2 +-
src/mesa/drivers/dri/i965/brw_fs.h | 699 -
.../drivers/dri/i965/brw_fs_copy_propagation.cpp | 2 +-
s
Signed-off-by: Jordan Justen
---
src/mesa/drivers/dri/i965/brw_fs_fp.cpp | 8 ++--
src/mesa/drivers/dri/i965/brw_scalar.h | 1 -
src/mesa/drivers/dri/i965/brw_scalar_visitor.cpp | 1 -
src/mesa/drivers/dri/i965/brw_wm_iz.cpp | 2 ++
4 files changed, 8 insertions(+)
Signed-off-by: Jordan Justen
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 2 +-
src/mesa/drivers/dri/i965/brw_scalar.h | 4 ++--
src/mesa/drivers/dri/i965/brw_scalar_generator.cpp | 10 +-
3 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/src/mesa/dr
Signed-off-by: Jordan Justen
---
src/mesa/drivers/dri/i965/brw_scalar.h | 17 +++--
1 file changed, 15 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_scalar.h
b/src/mesa/drivers/dri/i965/brw_scalar.h
index 7d3ebdb..be71101 100644
--- a/src/mesa/drivers/dri/
Reduce scalar_visitor's dependence on gl_fragment_program.
Signed-off-by: Jordan Justen
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 28
src/mesa/drivers/dri/i965/brw_scalar_visitor.cpp | 2 +-
2 files changed, 15 insertions(+), 15 deletions(-)
diff --git a/s
Signed-off-by: Jordan Justen
---
src/mesa/drivers/dri/i965/brw_context.h| 1 +
src/mesa/drivers/dri/i965/brw_scalar_generator.cpp | 4 ++--
src/mesa/drivers/dri/i965/brw_wm.c | 1 +
3 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i96
Signed-off-by: Jordan Justen
---
src/mesa/drivers/dri/i965/brw_scalar_visitor.cpp | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_scalar_visitor.cpp
b/src/mesa/drivers/dri/i965/brw_scalar_visitor.cpp
index e1b1fd7..f021dcb 100644
---
All fields were migrated from brw_wm_prog_key. In future updates, we can move
these FS specific fields back into brw_wm_prog_key.
The scalar_visitor and scalar_generator class mainly use these structures now.
Signed-off-by: Jordan Justen
---
src/mesa/drivers/dri/i965/brw_blorp_blit_eu.cpp|
Signed-off-by: Jordan Justen
---
src/mesa/drivers/dri/i965/brw_context.h| 1 +
src/mesa/drivers/dri/i965/brw_fs.cpp | 2 +-
src/mesa/drivers/dri/i965/brw_scalar_generator.cpp | 2 +-
src/mesa/drivers/dri/i965/brw_scalar_visitor.cpp | 12 ++--
src/mesa/driver
Reduce brw_fs_precompile's dependence on gl_fragment_program.
Signed-off-by: Jordan Justen
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 17 +
1 file changed, 9 insertions(+), 8 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
b/src/mesa/drivers/dri/i965/brw_fs.cpp
i
This common init routine can be used by constructors for multiple program
types.
Signed-off-by: Jordan Justen
---
src/mesa/drivers/dri/i965/brw_scalar.h | 1 +
src/mesa/drivers/dri/i965/brw_scalar_visitor.cpp | 6 ++
2 files changed, 7 insertions(+)
diff --git a/src/mesa/drivers/d
On Mon, Sep 1, 2014 at 12:00 PM, Roland Scheidegger wrote:
> Am 29.08.2014 22:44, schrieb Ilia Mirkin:
>> Hello,
>>
>> I've been thinking a bit about how to properly implement TCS outputs
>> in TGSI. As a quick reminder, there are per-vertex (i.e. invocation)
>> and per-patch outputs in TCS. And w
Am 01.09.2014 17:55, schrieb Emil Velikov:
> On 01/09/14 16:31, Roland Scheidegger wrote:
>> Am 30.08.2014 01:44, schrieb Emil Velikov:
>>> Hello list,
>>>
>>> Another boring yet important series, if we are to have properly working
>>> solution to package a mesa release tarball via 'make dist'.
>>>
As older versions of gnu ld did not support --dynamic-list check to see
if it is supported before using it. Non gnu linkers such the apple one
likely lack this option as well.
Fixes the build on OpenBSD which has binutils 2.15 and 2.17.
The --dynamic-list option seems to been have introduced some
On Mon, Sep 1, 2014 at 8:31 AM, Roland Scheidegger wrote:
> Am 30.08.2014 01:44, schrieb Emil Velikov:
>> Hello list,
>>
>> Another boring yet important series, if we are to have properly working
>> solution to package a mesa release tarball via 'make dist'.
>>
>> This series covers a few state-tr
Am 29.08.2014 22:44, schrieb Ilia Mirkin:
> Hello,
>
> I've been thinking a bit about how to properly implement TCS outputs
> in TGSI. As a quick reminder, there are per-vertex (i.e. invocation)
> and per-patch outputs in TCS. And while you can only write to the
> current invocation's per-vertex o
On 01/09/14 16:31, Roland Scheidegger wrote:
> Am 30.08.2014 01:44, schrieb Emil Velikov:
>> Hello list,
>>
>> Another boring yet important series, if we are to have properly working
>> solution to package a mesa release tarball via 'make dist'.
>>
>> This series covers a few state-tracker files mi
Am 30.08.2014 01:44, schrieb Emil Velikov:
> Hello list,
>
> Another boring yet important series, if we are to have properly working
> solution to package a mesa release tarball via 'make dist'.
>
> This series covers a few state-tracker files missed out previously,
> picks up all the gallium te
When constant folding a MAD operation, we first fold the multiply and
generate an ADD. However we do so without making sure that the immediate
can be handled in the saturate case. If it can't, load the immediate in
a separate instruction.
Reported-by: Tiziano Bacocco
Signed-off-by: Ilia Mirkin
C
https://bugs.freedesktop.org/show_bug.cgi?id=83355
--- Comment #3 from Emil Velikov ---
(In reply to comment #2)
> Thanks Emil, the patch fixes the build again. You can have my
> Tested-by: Kai Wasserbäch
>
Thanks.
> With regards to the parallel build: I always build in parallel and consider
https://bugs.freedesktop.org/show_bug.cgi?id=83355
--- Comment #2 from Kai ---
Thanks Emil, the patch fixes the build again. You can have my
Tested-by: Kai Wasserbäch
With regards to the parallel build: I always build in parallel and consider it
a valuable feature, since it speeds up build ti
https://bugs.freedesktop.org/show_bug.cgi?id=83355
--- Comment #1 from Emil Velikov ---
Parallel 'make install' was never tested to work (see the release
announcements).
With that aside a the following patch [1] will revert the commit and resolve
the original issue in another way. Feel free to gi
https://bugs.freedesktop.org/show_bug.cgi?id=83355
Priority: medium
Bug ID: 83355
Assignee: mesa-dev@lists.freedesktop.org
Summary: FTBFS: src/mesa/program/program_lexer.l:122:64: error:
unknown type name 'YYSTYPE'
Severity:
https://bugs.freedesktop.org/show_bug.cgi?id=79662
Eero Tamminen changed:
What|Removed |Added
CC||eero.t.tammi...@intel.com
--
You are re
https://bugs.freedesktop.org/show_bug.cgi?id=76188
--- Comment #11 from Pekka Paalanen ---
Sent to Mesa-stable:
http://lists.freedesktop.org/archives/mesa-stable/2014-September/001683.html
--
You are receiving this mail because:
You are the assignee for the bug.
This reverts commit 0fbb9a599df898d4e1166d6d6f00cb34a0524bea.
Rather than adding hacks around the issue drop the sources from the
final tarball, and re-add them back with 'make dist'. This fixes a
problem when running parallel 'make install' fails as it recreates
sources and triggers partial recom
On Thu, Aug 28, 2014 at 3:36 PM, Roland Scheidegger wrote:
> Oops there's a bug in there, I'll send out a new version (we only pass a
> one pixel sized array).
> FWIW the msaa case also has its issues (generates a warning in
> store_texsubimage, I guess that's pretty harmless though at the very
>
Perhaps Valley uses scattered writes, which the write-combining cache
doesn't like? u_upload_mgr mostly uses sequential writes, so I think
it could still benefit from VRAM placement. Just guessing.
Does the STREAM flag which causes problems come from Valley
(glBufferData) or from Mesa (u_upload_mg
Reviewed-by: Marek Olšák
Marek
On Thu, Aug 28, 2014 at 8:56 AM, Michel Dänzer wrote:
> From: Michel Dänzer
>
> This allows the kernel to prevent such BOs from ever being stored in the
> CPU inaccessible part of VRAM.
>
> Signed-off-by: Michel Dänzer
> ---
> src/gallium/drivers/radeon/r600_bu
Reviewed-by: Marek Olšák
Marek
On Thu, Aug 28, 2014 at 6:44 AM, Jordan Justen
wrote:
> i965 will have more than 32 bits when BRW_STATE_COMPUTE_PROGRAM is added.
>
> Signed-off-by: Jordan Justen
> ---
> Ken,
>
> How about this to replace "i965: Convert brw state dirty bits to
> 64-bits"?
>
> -J
PIPE_SHADER_MAX_CONST_BUFFER_SIZE replaced MAX_CONSTS. The former is
in bytes, while the latter was in vec4s (16 bytes).
Marek
On Wed, Aug 27, 2014 at 8:05 AM, Dave Airlie wrote:
> I think Tom cc'ed the wrong stable maybe, not sure,
>
> 10.2 doesn't have PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE, so
On Wed, Aug 27, 2014 at 10:57 AM, Michel Dänzer wrote:
> From: Michel Dänzer
>
> It's never used under normal circumstances.
>
> Signed-off-by: Michel Dänzer
> ---
> src/gallium/drivers/radeonsi/si_pipe.c | 7 ---
> src/gallium/drivers/radeonsi/si_state.c | 11 ++-
> 2 files chang
Possible resource leak reported by coverity.
Reported-by: Coverity scanner.
Signed-off-by: Dave Airlie
---
src/loader/loader.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/loader/loader.c b/src/loader/loader.c
index 47e1f58..bdd3906 100644
--- a/src/loader/loader.c
+++
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
b/src/mesa/drivers/dri/i965/brw_fs.cpp
index 43aee66..8b76c3e 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw
---
src/mesa/main/texstore.c | 4
1 file changed, 4 insertions(+)
diff --git a/src/mesa/main/texstore.c b/src/mesa/main/texstore.c
index f2eb0de..4b8158a 100644
--- a/src/mesa/main/texstore.c
+++ b/src/mesa/main/texstore.c
@@ -1634,6 +1634,8 @@ texstore_via_float(TEXSTORE_PARAMS)
}
---
src/mesa/drivers/dri/i965/brw_vec4.cpp | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_vec4.cpp
b/src/mesa/drivers/dri/i965/brw_vec4.cpp
index 5f8f399..ebe1216 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4.cpp
+++ b/src/mesa/drivers/dri/
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