Changes in directory llvm/lib/Target/ARM:
ARMInstrInfo.cpp updated: 1.39 -> 1.40
ARMInstrInfo.h updated: 1.16 -> 1.17
ARMInstrInfo.td updated: 1.114 -> 1.115
ARMInstrThumb.td updated: 1.32 -> 1.33
---
Log message:
Revert the earlier change that removed the M_REMATERIALIZABLE machine
instruction
On Jun 18, 2007, at 6:25 PM, Evan Cheng wrote:
> Log message:
>
> Replace TargetInstrInfo::CanBeDuplicated() with a M_NOT_DUPLICABLE
> bit.
>
Thanks Evan!
-Chris
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Changes in directory llvm/lib/Target/ARM:
ARMInstrInfo.cpp updated: 1.38 -> 1.39
ARMInstrInfo.h updated: 1.15 -> 1.16
ARMInstrInfo.td updated: 1.111 -> 1.112
ARMInstrThumb.td updated: 1.31 -> 1.32
---
Log message:
Replace M_REMATERIALIZIBLE and the newly-added isOtherReMaterializableLoad
with a
Changes in directory llvm/lib/Target/ARM:
ARMInstrInfo.cpp updated: 1.37 -> 1.38
ARMInstrInfo.h updated: 1.14 -> 1.15
ARMInstrInfo.td updated: 1.110 -> 1.111
ARMInstrThumb.td updated: 1.30 -> 1.31
---
Log message:
Replace TargetInstrInfo::CanBeDuplicated() with a M_NOT_DUPLICABLE bit.
---
Diff
Geeze. I was sure I would've been yelled at had I made it into a
targetinstrinfo bit. :-)
Really didn't want to go with either approach. But I don't see a
better alternative.
Evan
On Jun 15, 2007, at 2:37 PM, Chris Lattner wrote:
> On Jun 15, 2007, at 2:15 PM, Evan Cheng wrote:
>> Instructi
On Jun 15, 2007, at 2:15 PM, Evan Cheng wrote:
> Instructions with unique labels or embedded jumptables cannot be
> duplicated during ifcvt.
Please turn this into a targetinstrinfo bit. Virtual methods should
only be used for properties whose behavior is a property of the
*operands* of the
Changes in directory llvm/lib/Target/ARM:
ARMInstrInfo.cpp updated: 1.36 -> 1.37
ARMInstrInfo.h updated: 1.13 -> 1.14
---
Log message:
Instructions with unique labels or embedded jumptables cannot be duplicated
during ifcvt.
---
Diffs of the changes: (+31 -0)
ARMInstrInfo.cpp | 29 ++
Changes in directory llvm/lib/Target/ARM:
ARMInstrInfo.cpp updated: 1.35 -> 1.36
---
Log message:
Handle blocks with 2 unconditional branches in AnalyzeBranch.
---
Diffs of the changes: (+10 -0)
ARMInstrInfo.cpp | 10 ++
1 files changed, 10 insertions(+)
Index: llvm/lib/Target/
Changes in directory llvm/lib/Target/ARM:
ARMInstrInfo.cpp updated: 1.34 -> 1.35
---
Log message:
Add a utility routine to check for unpredicated terminator instruction.
---
Diffs of the changes: (+3 -3)
ARMInstrInfo.cpp |6 +++---
1 files changed, 3 insertions(+), 3 deletions(-)
Inde
Changes in directory llvm/lib/Target/ARM:
ARMInstrInfo.cpp updated: 1.33 -> 1.34
---
Log message:
Fix ARM condition code subsumission check.
---
Diffs of the changes: (+3 -3)
ARMInstrInfo.cpp |6 +++---
1 files changed, 3 insertions(+), 3 deletions(-)
Index: llvm/lib/Target/ARM/ARMIns
On Jun 6, 2007, at 6:38 PM, Evan Cheng wrote:
>
> Stupid cut-n-paste bug caused me s much grief. Why wasn't there
> a compilation warning? I blame it on the FE folks.
Geeze, if backend people wouldn't write code like this, the f.e.
people would have a much easier time ;-)
-Chris
> ---
Changes in directory llvm/lib/Target/ARM:
ARMInstrInfo.cpp updated: 1.32 -> 1.33
---
Log message:
Stupid cut-n-paste bug caused me s much grief. Why wasn't there a
compilation warning? I blame it on the FE folks.
---
Diffs of the changes: (+1 -1)
ARMInstrInfo.cpp |2 +-
1 files cha
Changes in directory llvm/lib/Target/ARM:
ARMInstrInfo.cpp updated: 1.31 -> 1.32
ARMInstrInfo.h updated: 1.12 -> 1.13
ARMLoadStoreOptimizer.cpp updated: 1.12 -> 1.13
ARMRegisterInfo.cpp updated: 1.96 -> 1.97
---
Log message:
Add missing const qualifiers.
---
Diffs of the changes: (+24 -19)
Changes in directory llvm/lib/Target/ARM:
ARMInstrInfo.cpp updated: 1.30 -> 1.31
ARMInstrInfo.h updated: 1.11 -> 1.12
---
Log message:
Hooks for predication support.
---
Diffs of the changes: (+39 -9)
ARMInstrInfo.cpp | 41 +
ARMInstrInfo.h |7
No. IsTerminatorInstr() simply checks opcode flag, it's not target
dependent.
Evan
On May 21, 2007, at 12:01 PM, Dale Johannesen wrote:
>
> On May 21, 2007, at 11:56 AM, Evan Cheng wrote:
>
>> - isTerminatorInstr((--I)->getOpcode()))
>> + !isPredicated(--I) && isTerminatorInstr(I->ge
Changes in directory llvm/lib/Target/ARM:
ARMInstrInfo.cpp updated: 1.29 -> 1.30
---
Log message:
Fix some -march=thumb regressions. tBR_JTr is not predicable.
---
Diffs of the changes: (+3 -1)
ARMInstrInfo.cpp |4 +++-
1 files changed, 3 insertions(+), 1 deletion(-)
Index: llvm/lib/T
On May 21, 2007, at 11:56 AM, Evan Cheng wrote:
> - isTerminatorInstr((--I)->getOpcode()))
> + !isPredicated(--I) && isTerminatorInstr(I->getOpcode()))
Wouldn't it be better to have isTerminatorInst return false on
predicated things?
___
l
Changes in directory llvm/lib/Target/ARM:
ARMInstrInfo.cpp updated: 1.28 -> 1.29
---
Log message:
BlockHasNoFallThrough() now returns true if block ends with a return
instruction; AnalyzeBranch() should ignore predicated instructionsd.
---
Diffs of the changes: (+13 -2)
ARMInstrInfo.cpp |
On May 16, 2007, at 1:50 PM, Chris Lattner wrote:
>>> Does that mean it can be predicated and the predicate is not set to
>>> always? What client do you expect for this?
>>
>> Right. The only potential client is the if-converter. If anything is
>> already predicated on a non-always predicate bef
>> Does that mean it can be predicated and the predicate is not set to
>> always? What client do you expect for this?
>
> Right. The only potential client is the if-converter. If anything is
> already predicated on a non-always predicate before if-conversion, it
> needs to know.
Random thought, p
On May 16, 2007, at 11:42 AM, Chris Lattner wrote:
>>> Yes, I think this should be the distinction between M_PREDICATED
>>> (the
>>> instr already has a predicate field, but may be set to 'always') vs
>>> M_PREDICABLE (the instr may or may not have a predicate field, but
>>> PredicateInstructio
>> Yes, I think this should be the distinction between M_PREDICATED (the
>> instr already has a predicate field, but may be set to 'always') vs
>> M_PREDICABLE (the instr may or may not have a predicate field, but
>> PredicateInstruction can change it into one that does).
>
> I dunno if that's the
On May 16, 2007, at 11:21 AM, Evan Cheng wrote:
>> I realized this morning what I really meant :). I think that
>> isPredicable should be a non-virtual function that checks TID-
>>> Flags&M_PREDICATED (Actually, it might make sense to introduce a
>> new M_PREDICABLE flag). Further, the default
On May 16, 2007, at 10:09 AM, Chris Lattner wrote:
> On May 16, 2007, at 1:18 AM, Evan Cheng wrote:
>>> But even then I am not sure if that eliminate the need to have a
>>> virtual function isPredicatable. Conditional branches probably would
>>> require special handling. Also, while it isn't poss
On May 16, 2007, at 10:06 AM, Chris Lattner wrote:
> On May 16, 2007, at 1:02 AM, Evan Cheng wrote:
>>> I don't think there is any reason for this to be virtual and target-
>>> specific. In particular, can you please model B/tB the same way PPC
>>> handles branches (where an uncond branch is jus
On May 16, 2007, at 1:18 AM, Evan Cheng wrote:
>> But even then I am not sure if that eliminate the need to have a
>> virtual function isPredicatable. Conditional branches probably would
>> require special handling. Also, while it isn't possible now, it's
>> conceivable some instruction predicate f
On May 16, 2007, at 1:02 AM, Evan Cheng wrote:
>> I don't think there is any reason for this to be virtual and target-
>> specific. In particular, can you please model B/tB the same way PPC
>> handles branches (where an uncond branch is just a conditional branch
>> where the condition is set to 'a
On May 16, 2007, at 1:02 AM, Evan Cheng wrote:
>
> On May 15, 2007, at 11:50 PM, Chris Lattner wrote:
>>
>> I don't think there is any reason for this to be virtual and target-
>> specific. In particular, can you please model B/tB the same way PPC
>> handles branches (where an uncond branch is j
On May 15, 2007, at 11:50 PM, Chris Lattner wrote:
>> Hooks for predication support.
>
> yay!
>
>> +bool ARMInstrInfo::isPredicatable(MachineInstr *MI) const {
>> + const TargetInstrDescriptor *TID = MI->getInstrDescriptor();
>> + if (TID->Flags & M_PREDICATED)
>> +return true;
>> +
>> + u
> Hooks for predication support.
yay!
> +bool ARMInstrInfo::isPredicatable(MachineInstr *MI) const {
> + const TargetInstrDescriptor *TID = MI->getInstrDescriptor();
> + if (TID->Flags & M_PREDICATED)
> +return true;
> +
> + unsigned Opc = MI->getOpcode();
> + return Opc == ARM::B || Opc
Changes in directory llvm/lib/Target/ARM:
ARMInstrInfo.cpp updated: 1.24 -> 1.25
ARMInstrInfo.h updated: 1.7 -> 1.8
ARMTargetMachine.cpp updated: 1.26 -> 1.27
ARMTargetMachine.h updated: 1.9 -> 1.10
---
Log message:
Hooks for predication support.
---
Diffs of the changes: (+39 -0)
ARMInstrI
Changes in directory llvm/lib/Target/ARM:
ARMInstrInfo.cpp updated: 1.22 -> 1.23
ARMConstantIslandPass.cpp updated: 1.38 -> 1.39
---
Log message:
Rewrite of Thumb constant islands handling (exact allowance for padding
around islands and jump tables).
---
Diffs of the changes: (+226 -87)
AR
Changes in directory llvm/lib/Target/ARM:
ARMInstrInfo.cpp updated: 1.21 -> 1.22
ARMLoadStoreOptimizer.cpp updated: 1.7 -> 1.8
---
Log message:
Rename findRegisterUseOperand to findRegisterUseOperandIdx to avoid confusion.
---
Diffs of the changes: (+2 -2)
ARMInstrInfo.cpp |2 +
Changes in directory llvm/lib/Target/ARM:
ARMInstrInfo.cpp updated: 1.20 -> 1.21
---
Log message:
Relex assertions to account for additional implicit def / use operands.
---
Diffs of the changes: (+1 -1)
ARMInstrInfo.cpp |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index: llv
Changes in directory llvm/lib/Target/ARM:
ARMInstrInfo.cpp updated: 1.19 -> 1.20
ARMRegisterInfo.cpp updated: 1.85 -> 1.86
---
Log message:
Removed tabs everywhere except autogenerated & external files. Add make
target for tabs checking.
---
Diffs of the changes: (+3 -3)
ARMInstrInfo.cpp
Changes in directory llvm/lib/Target/ARM:
ARMInstrInfo.cpp updated: 1.18 -> 1.19
---
Log message:
Inverted logic.
---
Diffs of the changes: (+1 -1)
ARMInstrInfo.cpp |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index: llvm/lib/Target/ARM/ARMInstrInfo.cpp
diff -u llvm/lib/Targe
Changes in directory llvm/lib/Target/ARM:
ARMInstrInfo.cpp updated: 1.17 -> 1.18
ARMLoadStoreOptimizer.cpp updated: 1.6 -> 1.7
---
Log message:
findRegisterUseOperand() changed.
---
Diffs of the changes: (+3 -3)
ARMInstrInfo.cpp |4 ++--
ARMLoadStoreOptimizer.cpp |2 +-
2 f
Changes in directory llvm/lib/Target/ARM:
ARMInstrInfo.cpp updated: 1.15 -> 1.16
ARMInstrThumb.td updated: 1.13 -> 1.14
ARMRegisterInfo.cpp updated: 1.58 -> 1.59
README-Thumb.txt updated: 1.5 -> 1.6
---
Log message:
Spill / restore should avoid modifying the condition register.
---
Diffs of th
Changes in directory llvm/lib/Target/ARM:
ARMInstrInfo.cpp updated: 1.14 -> 1.15
---
Log message:
Copy and paste bug.
---
Diffs of the changes: (+11 -1)
ARMInstrInfo.cpp | 12 +++-
1 files changed, 11 insertions(+), 1 deletion(-)
Index: llvm/lib/Target/ARM/ARMInstrInfo.cpp
diff
Changes in directory llvm/lib/Target/ARM:
ARMInstrInfo.cpp updated: 1.13 -> 1.14
---
Log message:
Misseed thumb jumptable branch.
---
Diffs of the changes: (+1 -0)
ARMInstrInfo.cpp |1 +
1 files changed, 1 insertion(+)
Index: llvm/lib/Target/ARM/ARMInstrInfo.cpp
diff -u llvm/lib/Targe
Changes in directory llvm/lib/Target/ARM:
ARMInstrInfo.cpp updated: 1.9 -> 1.10
ARMMul.cpp updated: 1.3 -> 1.4
ARMRegisterInfo.cpp updated: 1.26 -> 1.27
ARMRegisterInfo.h updated: 1.2 -> 1.3
---
Log message:
Change MachineInstr ctor's to take a TargetInstrDescriptor reference instead
of opcode
Changes in directory llvm/lib/Target/ARM:
ARMInstrInfo.cpp updated: 1.8 -> 1.9
---
Log message:
fix warning about missing newline at end of file
---
Diffs of the changes: (+1 -1)
ARMInstrInfo.cpp |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index: llvm/lib/Target/ARM/ARMInst
Changes in directory llvm/lib/Target/ARM:
ARMInstrInfo.cpp updated: 1.7 -> 1.8
ARMInstrInfo.h updated: 1.3 -> 1.4
ARMInstrInfo.td updated: 1.70 -> 1.71
---
Log message:
implement uncond branch insertion, mark branches with isBranch.
---
Diffs of the changes: (+13 -1)
ARMInstrInfo.cpp |
Changes in directory llvm/lib/Target/ARM:
ARMInstrInfo.cpp updated: 1.4 -> 1.5
ARMInstrInfo.h updated: 1.2 -> 1.3
ARMInstrInfo.td updated: 1.12 -> 1.13
ARMRegisterInfo.cpp updated: 1.10 -> 1.11
---
Log message:
change the addressing mode of the str instruction to reg+imm
---
Diffs of the chan
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