[llvm-commits] CVS: llvm/lib/Target/ARM/ARMInstrInfo.cpp ARMInstrInfo.h

[Evan Cheng]

Changes in directory llvm/lib/Target/ARM:

ARMInstrInfo.cpp updated: 1.30 -> 1.31
ARMInstrInfo.h updated: 1.11 -> 1.12
---
Log message:

Hooks for predication support.

---
Diffs of the changes:  (+39 -9)

 ARMInstrInfo.cpp |   41 +++++++++++++++++++++++++++++++++--------
 ARMInstrInfo.h   |    7 ++++++-
 2 files changed, 39 insertions(+), 9 deletions(-)


Index: llvm/lib/Target/ARM/ARMInstrInfo.cpp
diff -u llvm/lib/Target/ARM/ARMInstrInfo.cpp:1.30 
llvm/lib/Target/ARM/ARMInstrInfo.cpp:1.31
--- llvm/lib/Target/ARM/ARMInstrInfo.cpp:1.30   Mon May 21 18:17:32 2007
+++ llvm/lib/Target/ARM/ARMInstrInfo.cpp        Wed May 23 02:22:05 2007
@@ -298,11 +298,6 @@
   return NewMIs[0];
 }
 
-static bool isPredicated(MachineInstr *MI) {
-  MachineOperand *PMO = MI->findFirstPredOperand();
-  return PMO && PMO->getImmedValue() != ARMCC::AL;
-}
-
 // Branch analysis.
 bool ARMInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock 
*&TBB,
                                  MachineBasicBlock *&FBB,
@@ -436,23 +431,53 @@
   return false;
 }
 
+bool ARMInstrInfo::isPredicated(MachineInstr *MI) const {
+  MachineOperand *PMO = MI->findFirstPredOperand();
+  return PMO && PMO->getImmedValue() != ARMCC::AL;
+}
+
 bool ARMInstrInfo::PredicateInstruction(MachineInstr *MI,
-                                      std::vector<MachineOperand> &Cond) const 
{
+                                      std::vector<MachineOperand> &Pred) const 
{
   unsigned Opc = MI->getOpcode();
   if (Opc == ARM::B || Opc == ARM::tB) {
     MI->setInstrDescriptor(get(Opc == ARM::B ? ARM::Bcc : ARM::tBcc));
-    MI->addImmOperand(Cond[0].getImmedValue());
+    MI->addImmOperand(Pred[0].getImmedValue());
     return true;
   }
 
   MachineOperand *PMO = MI->findFirstPredOperand();
   if (PMO) {
-    PMO->setImm(Cond[0].getImmedValue());
+    PMO->setImm(Pred[0].getImmedValue());
     return true;
   }
   return false;
 }
 
+bool ARMInstrInfo::SubsumesPredicate(std::vector<MachineOperand> &Pred1,
+                                     std::vector<MachineOperand> &Pred2) const{
+  if (Pred1.size() > 1 || Pred2.size() > 1)
+    return false;
+
+  ARMCC::CondCodes CC1 = (ARMCC::CondCodes)Pred1[0].getImmedValue();
+  ARMCC::CondCodes CC2 = (ARMCC::CondCodes)Pred2[0].getImmedValue();
+  if (CC1 == CC2)
+    return true;
+
+  switch (CC1) {
+  default:
+    return false;
+  case ARMCC::AL:
+    return true;
+  case ARMCC::HS:
+    return CC2 == ARMCC::HI || CC2 == ARMCC::EQ;
+  case ARMCC::LS:
+    return CC2 == ARMCC::LO || CC2 == ARMCC::EQ;
+  case ARMCC::GE:
+    return CC2 == ARMCC::GT || CC2 == ARMCC::EQ;
+  case ARMCC::LE:  return "le";
+    return CC2 == ARMCC::LT || CC2 == ARMCC::EQ;
+  }
+}
 
 /// FIXME: Works around a gcc miscompilation with -fstrict-aliasing
 static unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT,


Index: llvm/lib/Target/ARM/ARMInstrInfo.h
diff -u llvm/lib/Target/ARM/ARMInstrInfo.h:1.11 
llvm/lib/Target/ARM/ARMInstrInfo.h:1.12
--- llvm/lib/Target/ARM/ARMInstrInfo.h:1.11     Thu May 17 19:18:17 2007
+++ llvm/lib/Target/ARM/ARMInstrInfo.h  Wed May 23 02:22:05 2007
@@ -104,8 +104,13 @@
   virtual bool ReverseBranchCondition(std::vector<MachineOperand> &Cond) const;
 
   // Predication support.
+  virtual bool isPredicated(MachineInstr *MI) const;
+
   virtual bool PredicateInstruction(MachineInstr *MI,
-                                    std::vector<MachineOperand> &Cond) const;
+                                    std::vector<MachineOperand> &Pred) const;
+
+  virtual bool SubsumesPredicate(std::vector<MachineOperand> &Pred1,
+                                 std::vector<MachineOperand> &Pred1) const;
 };
 
   // Utility routines



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