> Hooks for predication support. yay!
> +bool ARMInstrInfo::isPredicatable(MachineInstr *MI) const { > + const TargetInstrDescriptor *TID = MI->getInstrDescriptor(); > + if (TID->Flags & M_PREDICATED) > + return true; > + > + unsigned Opc = MI->getOpcode(); > + return Opc == ARM::B || Opc == ARM::tB; > +} > + > +void ARMInstrInfo::PredicateInstruction(MachineInstr *MI, > + std::vector<MachineOperand> > &Cond) const { > + unsigned Opc = MI->getOpcode(); > + if (Opc == ARM::B || Opc == ARM::tB) { > + MI->setInstrDescriptor(get(Opc == ARM::B ? ARM::Bcc : > ARM::tBcc)); > + MI->addImmOperand(Cond[0].getImmedValue()); > + return; > + } > + > + MachineOperand *PMO = MI->findFirstPredOperand(); > + PMO->setImm(Cond[0].getImmedValue()); > +} I don't think there is any reason for this to be virtual and target- specific. In particular, can you please model B/tB the same way PPC handles branches (where an uncond branch is just a conditional branch where the condition is set to 'always')? That way, you don't need a special case, isPredicatable doesn't need to be virtual, and each target doesn't need to implement PredicateInstruction. -Chris _______________________________________________ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits