re of. The PCIe entry falls under the
PLB which could also be a problem but again, I am not sure.
So basically, is there an easy way to change what I've got
to map 1.25 or 2GB of space?
Thanks
Ayman
PCIE0: pciex@0a000 {
device_type = "pci";
#interru
I never did get this to work, and now I am back to it again.
On Fri, Oct 14, 2011 at 09:39:51AM +0200, Benjamin Herrenschmidt wrote:
> On Wed, 2011-10-12 at 16:08 -0500, Ayman El-Khashab wrote:
> > I'm using the 460sx (440 core) so no snooping here. What
> > I've do
(PHYS_MEM_ADDR)>>PAGE_SHIFT,
len, vma->vm_page_prot);
Is this going to give me the best performance, or is there
something more I can do?
Failing that, what is the best way to do this (i need a very
large contiguous buffer). it runs in batch mode, so it
DMAs, stops, cpu rea
From: Ayman El-Khashab
Adds a register to the config space for the 460sx. Changes the vc0
detect to a pll detect. maps configuration space to test the link
status. changes the setup to enable gen2 devices to operate at gen2
speeds. fixes mapping that was not correct for the 460sx. added
bit
From: Ayman El-Khashab
Changes from v1->v2
Added definitions for the bits in the OMRxMSKL registers
Refactored the setting of the OMRxMSKL registers for the 460SX
Added bit defines for the PECFG_460SX_DLLSTA register
Changes from v2->v3
Fixed commit message to be more clear as to what wa
On Mon, Jul 18, 2011 at 02:01:15PM +1000, Tony Breeds wrote:
> On Fri, Jul 15, 2011 at 11:40:27AM -0500, Ayman Elkhashab wrote:
>
> > @@ -1582,8 +1628,8 @@ static int __init ppc4xx_setup_one_pciex_POM(struct
> > ppc4xx_pciex_port *port,
> > dcr_write(port-&
From: Ayman El-Khashab
Adds a register to the config space for the 460sx. Changes the vc0
detect to a pll detect. maps configuration space to test the link
status. changes the setup to enable gen2 devices to operate at gen2
speeds. fixes mapping that was not correct for the 460sx. added
bit
_OMR3MSKL, sa | 3);
> > + dcr_write(port->dcrs, DCRO_PEGPL_OMR3MSKL, sa);
> > break;
> > }
>
> I think you really want to check the definitions for OMRs 2 and 3 to verify
> that this is right.
Thanks, good catch. I'll change the first case block to
include a switch on the 460sx. The first case statement
needs to be | 0x5, while the others need to stay 0x3.
Ayman
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custom board
Signed-off-by: Ayman El-Khashab
---
arch/powerpc/sysdev/ppc4xx_pci.c | 83 +
arch/powerpc/sysdev/ppc4xx_pci.h |3 +
2 files changed, 68 insertions(+), 18 deletions(-)
diff --git a/arch/powerpc/sysdev/ppc4xx_pci.c b/arch/powerpc/sysdev
_link function to specialize the link detect for the 460sx.
Tested on an eiger and custom board. Note that is swaps the order of the link
check and dcr initialization since the config space needs the DCRs setup before
it can be mapped and used to check the link.
Ayman El-Khashab (1):
powerp
right thing to do
here is?
thanks
ayman
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On Tue, Jul 12, 2011 at 02:04:04PM -0400, Josh Boyer wrote:
> On Tue, Jul 12, 2011 at 12:40:07PM -0500, Ayman El-Khashab wrote:
> >On Fri, Jul 01, 2011 at 04:44:24PM +1000, Tony Breeds wrote:
> >> All current pcie controllers unconditionally use SDR to check the link and
&
So how does one supply a patch atop another
patch?
Best,
Ayman
> +static int __init ppc4xx_pciex_port_reset_sdr(struct ppc4xx_pciex_port *port)
> +{
> + printk(KERN_INFO "PCIE%d: Checking link...\n",
> +port->index);
Its not a functional problem, but this p
On Wed, Jun 29, 2011 at 11:42:03AM +1000, Benjamin Herrenschmidt wrote:
> On Mon, 2011-06-27 at 06:31 -0500, Ayman El-Khashab wrote:
> > On Mon, Jun 27, 2011 at 08:19:56PM +1000, Benjamin Herrenschmidt wrote:
> > > On Sat, 2011-06-25 at 18:52 -0500, Ayman El-Khashab wrote:
> &
On Wed, Jun 29, 2011 at 09:15:28AM +1000, Benjamin Herrenschmidt wrote:
> On Tue, 2011-06-28 at 17:31 -0500, Ayman El-Khashab wrote:
> > > > +static int ppc4xx_setup_pcieh_hw(struct platform_device *dev,
> > > > +struct resource res,
ct resource res, struct ppc4xx_msi *msi)
> > +{
> > +
> > +
> > + msi->msi_dev = of_find_node_by_name(NULL, "ppc4xx-msi");
> > + if (msi->msi_dev)
> > + return -ENODEV;
This do
On Mon, Jun 27, 2011 at 08:19:56PM +1000, Benjamin Herrenschmidt wrote:
> On Sat, 2011-06-25 at 18:52 -0500, Ayman El-Khashab wrote:
> > I noticed during a recent development with the 460SX that a
> > simple device that once worked stopped. I did a bisect to
> > find the of
ake a stab at making a new functor to handle
the "link check"? -- which IIRC was the thought from last
month about how best to handle the 460SX and whatever some
people were using internally.
Ayman
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on a 460SX (which
has the 36 bit pci space).
sil24 /drivers/ata/sata_sil24.c
Thanks
Ayman
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es at the time of submission
> > To test them.
>
> Can we fix that ?
>
I took care of that in my patch. Basically it let the
system go to gen-2 speeds and negotiate down.
Ayman
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r something.
Lastly, what was the reason for forcing the original code to
be GEN-1 speeds?
ayman
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On Tue, Apr 12, 2011 at 07:09:49PM -0700, Tirumala Marri wrote:
> You originally submitted the support for 460ex. Can you chime in (and
> review Ayman patch) please ?
>
> [Marri] Ben sure I will review it and send you my feedback in couple of
> days.
Is there any update on t
From: Ayman El-Khashab
This patch is to fix the PCIe on the 460SX CPU. As far as I can tell,
the 460SX must be using a different core than the previous 4xx SOCs.
The registers aren't the same and it appears DCRs that existed on
previous parts don't exist on this one. Perhaps som
From: Ayman El-Khashab
The 460SX uses a different register set than previous 44x PCIe CPUs,
so some of the checks were not valid. Added an enable for the TX
and RX. For the 460SX only: Bypassed VCO check and added PLL check.
Bypassed the link check. Changed to advertise gen 2 speeds.
Signed
owing kernel panic. ?I am not
> >> sure how to proceed here. ?I suppose we can stick with 2.6.36 since
> >> it works, but I'd like to understand what it might take to remedy
> >> this.
> >
> > Smells like somebody changed something with the OF flash code.
On Fri, Apr 01, 2011 at 11:26:19AM -0500, Ayman El-Khashab wrote:
> I've got an LSI SAS2008 controller (w/ firmware v9) that works
> fine in a Linux PC w/ a recent kernel. It does NOT work on my
> 460EX board. What I find is that the device shows up as every
> device on the subo
er. Any help would be
appreciated.
best
ayman
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On Sat, Sep 25, 2010 at 08:11:04AM +1000, Benjamin Herrenschmidt wrote:
> On Fri, 2010-09-24 at 08:08 -0500, Ayman El-Khashab wrote:
> >
> > I suppose another option is to to use the kernel profiling option I
> > always see but have never used. Is that a viable option to f
t in the current implementation we found
empirically that we could kmalloc up to but no more than 4MB. We have
also tried an approach in user memory and then using "get_user_pages"
and building a scatter-gather. We found that the compare code doesn't
perform any be
On Fri, Sep 24, 2010 at 11:07:24AM +1000, Benjamin Herrenschmidt wrote:
> On Thu, 2010-09-23 at 17:35 -0500, Ayman El-Khashab wrote:
> > Anything you allocate with kmalloc() is going to be mapped by bolted
> > > 256M TLB entries, so there should be no TLB misses happening in the
On Fri, Sep 24, 2010 at 08:01:04AM +1000, Benjamin Herrenschmidt wrote:
> On Thu, 2010-09-23 at 10:12 -0500, Ayman El-Khashab wrote:
> > I've implemented a working driver on my 460EX. it allocates a couple
> > of buffers of 4MB each. I have a custom memcmp algorithm in asm t
alloc to make sure that
the ppc44x has 4MB tlb entries for these and that they stay put?
thanks
ayman
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t the best approach for
kernel DMA memory?
This is on linux 2.6.31.5 on 460EX
thanks
ayman
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I have an odd problem when using the 460ex rev b processors. Previously,
I'd used the rev A without any issues on the same pcbs. This happens on
multiple units now. Basically, while running the system will just
randomly kernel panic. We have seen this probably 4 or 5 times on a
over the cours
ss with the TLB/cache settings? When I boot Linux I
reserve the upper 16Mb of memory (from 112-128Mb space) and then mmap
that entire region into CPU1's space. Not sure if when it is reserved
if it is treated differently by Linux or not.
Any help is
On 7/7/2010 2:48 PM, ay...@austin.rr.com wrote:
rc = io_remap_pfn_range(vma, PLB_OCM_BASE_ADDR>>PAGE_SHIFT, vma->vm_start, len,
vma->vm_page_prot);
I am fairly certain the physical address is correct, I've verified that the
TLB entries in u-boot look ok. Any tips on how to make this work?
I've got an issue with the new rev B 460EX processors that I am trying to
isolate.
(Rev A worked fine). In order to do that, I am trying to modify my driver to
map the OCM (on chip memory) from the 460EX to user space so that the rest of
the
application and codebase don't really know the differ
On 1/5/2010 10:38 PM, Bill Gatliff wrote:
Ayman El-Khashab wrote:
I've got a custom board akin to the walnut. I've successfully got
u-boot,
the kernel, and a working filesystem. The only thing I lack is a
clear idea
of how to set a GPIO.
Isn't that the "f
on what I've read it seems that I might need to add a node to the dts
and then a custom piece of code in the platform directory for my board. I
am just not sure how to proceed there.
thanks
ayman
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csi/mpt2sas/mpt2sas_scsih.c:5989/_scsih_probe()!
Thanks
Ayman
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rd as disabled.
The last issue, is that I am not quite sure exactly which kernel drivers
are needed for this device.
Here is the output from DEBUG=1 in the pci_probe. The first is without
the fusion driver, and the latter is with the fusion driver.
Thanks
Ayman
# dmesg Bus: primary=80, seconda
ayman
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> -Original Message-
> From: Ira Snyder [mailto:[EMAIL PROTECTED]
> Sent: Wednesday, December 10, 2008 6:18 PM
> To: Ayman El-Khashab
> Cc: linuxppc-dev@ozlabs.org
> Subject: Re: Help enabling PCI endpoint on 460EX, host sees disabled
>
>
> I can't hel
My system consists of a pair of 460EXs attached by way of both PCI-E and
PCI. Ultimately my goal is to communicate between them via pci-e (is
there anything out there that does this already?). For a small step, I
am trying to get the PCI to work. I already have the PCI boot ability
of the 460EXs
Benjamin Herrenschmidt wrote:
>
> Ayman, can you double check that this variant of the patch still
> fixes your problem ? Thanks !
>
I've tried it out and it is working correctly with my devices. The
subordinate bus numbers on all the ports are correct.
Be
textual description of what was
supposed to be happening, I went ahead and changed it to ...
((buses >> 8) & 0xff) != bus->number) {
And this is the code that generated the results from my previous
message.
Hope that made sense ...
Regards,
Ayman
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t me know if that was wrong.
Attached below is the dmesg output, in this case the SIL on the downstream
switch port was detected correctly. Advise if there is something else that
needs to be tried.
Thanks
Ayman
Kernel command line: ramdisk_size=65536 root=/dev/ram rw ip=169.254.0.199:169.20
UIC0
Benjamin Herrenschmidt wrote:
> On Thu, 2008-10-16 at 10:01 -0500, Ayman El-Khashab wrote:
>> Benjamin Herrenschmidt wrote:
>>> On Wed, 2008-10-15 at 10:47 -0500, Ayman El-Khashab wrote:
>>>
>>> Note for people on CC: This is a problem on 460EX on a canyonland
Benjamin Herrenschmidt wrote:
> On Wed, 2008-10-15 at 10:47 -0500, Ayman El-Khashab wrote:
>
> Note for people on CC: This is a problem on 460EX on a canyonland
> using the 4x port.
>
>> The problem occurs when Linux boots. It sees the switch (and looking
>> in /sy
in the log with provide some insight.
Thanks
Ayman
--
AND: 128 MiB
PCI: Bus Dev VenId DevId Class Int
PCIE0: link is not up.
PCIE0: initialization as root-complex failed
PCIE1: successfully set as root-complex
03 01 10b5 8509 0604 00
03 02 10b5 8509 0604 00
06
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