On Mon, Jul 18, 2011 at 02:01:15PM +1000, Tony Breeds wrote: > On Fri, Jul 15, 2011 at 11:40:27AM -0500, Ayman Elkhashab wrote: > > > @@ -1582,8 +1628,8 @@ static int __init ppc4xx_setup_one_pciex_POM(struct > > ppc4xx_pciex_port *port, > > dcr_write(port->dcrs, DCRO_PEGPL_OMR2BAH, lah); > > dcr_write(port->dcrs, DCRO_PEGPL_OMR2BAL, lal); > > dcr_write(port->dcrs, DCRO_PEGPL_OMR2MSKH, 0x7fffffff); > > - /* Note that 3 here means enabled | single region */ > > - dcr_write(port->dcrs, DCRO_PEGPL_OMR2MSKL, sa | 3); > > + dcr_write(port->dcrs, DCRO_PEGPL_OMR2MSKL, > > + sa | DCRO_PEGPL_OMRxMSKL_VAL); > > Didn't you just change "sa | 3" to "sa | 1" ? >
Yes, but I think that is correct for it to be "1". The data sheets for these parts that I checked had bit 1 marked as reserved. Only OMR1MSKL and OMR3MSKL had extra definitions such as the _IO and _UOT. The parts I checked which were the sheets for the EX and SX (which cover another 6 or 7 parts) all had it with just a single bit defined on that register. Ayman _______________________________________________ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
