On Thu, May 05, 2011 at 09:44:27AM -0700, Tirumala Marri wrote: > > > > Also, the patch removes the code for waiting for the link to be up with > > a comment "What DCR has the link status on the 460SX?". Please fix that > > (Tirumala, can you provide the missing information ?) > > > > It is not one register. Here is the flow for Gen-1. > 1. PECFGn_DLLSTA[3] will be asserted when pci-e link comes up. > 2. now progream the UTL buffer configuration registers. > 3. SW should assert PEUTLn_PCTL[0] to cause flow control initialization. > This is memory mapped using GPL register REGBH , REBAL and REGMSK > 4. Now check for the PEUTLN_PSTA[8] for the flow control init completion.
So what is the best way to handle this? It appears (based on the comments of others and my own experience) that there is no DCR that exists and behaves the way that previous SOCs behaved to give us the link status? The register above PECFGn_DLLSTA is actually in the PCIe configuration space so we would have to map that in to be able to read that register during the link check. Is that correct or ok? I've communicated with some people over email and they had tried the (PESDRn_HSSLySTS) register. Recognizing that there exists one of these for each port/lane, is there a way to use this one? It is in the indirect DCR space. I'd tried this myself and never did get it to do anything but I could have been looking at the wrong lane or something. Lastly, what was the reason for forcing the original code to be GEN-1 speeds? ayman _______________________________________________ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
