On Wed, 31 May 2023 at 23:30, Bjorn Helgaas wrote:
>
> On Wed, May 31, 2023 at 08:48:35PM +0200, Jonas Gorski wrote:
> > ...
>
> > Looking at the code I understand where coverity is coming from:
> >
> > #define __pci_dev_for_each_res0(dev, res, ...)
Hi,
On Tue, 30 May 2023 at 23:34, Bjorn Helgaas wrote:
> On Fri, May 12, 2023 at 02:48:51PM -0500, Bjorn Helgaas wrote:
> > On Fri, May 12, 2023 at 01:56:29PM +0300, Andy Shevchenko wrote:
> > > On Tue, May 09, 2023 at 01:21:22PM -0500, Bjorn Helgaas wrote:
> > > > On Tue, Apr 04, 2023 at 11:11:0
Hi,
On Fri, 10 Mar 2023 at 18:37, Amit Kumar Mahapatra
wrote:
>
> For supporting multiple CS the SPI device need to be aware of all the CS
> values. So, the "chip_select" member in the spi_device structure is now an
> array that holds all the CS values.
>
> spi_device structure now has a "cs_inde
On Mon, 6 Mar 2023 at 22:27, Sean Anderson wrote:
>
> On 3/6/23 15:51, Jonas Gorski wrote:
> > Hi,
> >
> > On Mon, 6 Mar 2023 at 20:16, Sean Anderson wrote:
> >>
> >> This is a generic binding for simple MMIO GPIO controllers. Although we
> >&g
Hi,
On Mon, 6 Mar 2023 at 18:26, Amit Kumar Mahapatra
wrote:
>
> For supporting multiple CS the SPI device need to be aware of all the CS
> values. So, the "chip_select" member in the spi_device structure is now an
> array that holds all the CS values.
>
> spi_device structure now has a "cs_index
Hi,
On Mon, 6 Mar 2023 at 20:16, Sean Anderson wrote:
>
> This is a generic binding for simple MMIO GPIO controllers. Although we
> have a single driver for these controllers, they were previously spread
> over several files. Consolidate them. The register descriptions are
> adapted from the comm
Hi Geert,
On Tue, 23 Apr 2019 at 09:49, Geert Uytterhoeven wrote:
>
> Hi Jonas,
>
> On Thu, Apr 18, 2019 at 1:12 PM Jonas Gorski wrote:
> > Add a clock specific flag to switch register accesses to big endian, to
> > allow runtime configuration of big endian divider clock
Now that clk_{readl,writel} is just an alias for {readl,writel}, we can
switch all users of clk_* to use the accessors directly and remove the
helpers.
Signed-off-by: Jonas Gorski
---
V2 -> V3:
* no actual changes
V1 -> V2:
* newly added patch
drivers/clk/clk-divider.c
Now that the powerpc clocks are properly marked as big endian, we can
remove the special handling for PowerPC.
Signed-off-by: Jonas Gorski
---
V2 -> V3:
* no actual changes
V1 -> V2:
* no actual changes
include/linux/clk-provider.h | 16
1 file changed, 16 deletions(-)
These clocks' registers are accessed as big endian, so mark them as
such.
Signed-off-by: Jonas Gorski
---
V2 -> V3:
* slightly rework to avoid a line >80 chars
V1 -> V2:
* switch from global to local flags
arch/powerpc/platforms/512x/clock-commonclk.c | 9 ++---
1 f
Add a clock specific flag to switch register accesses to big endian, to
allow runtime configuration of big endian mux clocks.
Signed-off-by: Jonas Gorski
---
V2 -> V3:
* drop unneeded else in clk_mux_readl
V1 -> V2:
* switch from global to local flag
drivers/clk/clk-mux.c
Add a clock specific flag to switch register accesses to big endian, to
allow runtime configuration of big endian multiplier clocks.
Signed-off-by: Jonas Gorski
---
V2 -> V3:
* drop unneeded else in clk_mult_readl
V1 -> V2:
* switch from global to local flag
drivers/clk/clk-multiplier.
Add a clock specific flag to switch register accesses to big endian, to
allow runtime configuration of big endian gated clocks.
Signed-off-by: Jonas Gorski
---
V2 -> V3:
* drop unneeded else in clk_gate_readl
V1 -> V2:
* switch from global to local flag
drivers/clk/clk-gate.c
Add a clock specific flag to switch register accesses to big endian, to
allow runtime configuration of big endian divider clocks.
Signed-off-by: Jonas Gorski
---
V2 -> V3:
* fix passed arguments to clk_div_readl found by kbuild
* drop unneeded else in clk_div_readl
V1 -> V2:
* switc
Add a clock specific flag to switch register accesses to big endian, to
allow runtime configuration of big endian fractional divider clocks.
Signed-off-by: Jonas Gorski
---
V2 -> V3:
* drop unneeded else in clk_fd_readl
V1 -> V2:
* switch from global to local flag
drivers/clk/clk-frac
* reordered the basic clock patches in alphabetical order
* drop clk_{readl,writel} instead of adding BE variants and use
common accessors directly
* dropped the RFC, as I got comments (yay). More always welcome of
course :-)
Jonas Gorski (8):
clk: divider: add explicit big endian supp
On Thu, 18 Apr 2019 at 01:32, Stephen Boyd wrote:
>
> Quoting Jonas Gorski (2019-04-15 03:10:39)
> > @@ -370,7 +388,7 @@ static long clk_divider_round_rate(struct clk_hw *hw,
> > unsigned long rate,
> > if (divider->flags & CLK_DIVIDER_READ_ONLY
Now that clk_{readl,writel} is just an alias for {readl,writel}, we can
switch all users of clk_* to use the accessors directly and remove the
helpers.
Signed-off-by: Jonas Gorski
---
V1 -> V2:
* newly added patch
drivers/clk/clk-divider.c | 4 ++--
drivers/clk/clk-fractio
Now that the powerpc clocks are properly marked as big endian, we can
remove the special handling for PowerPC.
Signed-off-by: Jonas Gorski
---
V1 -> V2:
* no actual changes
include/linux/clk-provider.h | 16
1 file changed, 16 deletions(-)
diff --git a/include/linux/
These clocks' registers are accessed as big endian, so mark them as
such.
Signed-off-by: Jonas Gorski
---
V1 -> V2:
* switch from global to local flags
arch/powerpc/platforms/512x/clock-commonclk.c | 11 +++
1 file changed, 7 insertions(+), 4 deletions(-)
diff --git a/arch
Add a clock specific flag to switch register accesses to big endian, to
allow runtime configuration of big endian mux clocks.
Signed-off-by: Jonas Gorski
---
V1 -> V2:
* switch from global to local flag
drivers/clk/clk-mux.c| 22 +++---
include/linux/clk-provide
Add a clock specific flag to switch register accesses to big endian, to
allow runtime configuration of big endian multiplier clocks.
Signed-off-by: Jonas Gorski
---
V1 -> V2:
* newly added patch
drivers/clk/clk-multiplier.c | 22 +++---
include/linux/clk-provider.h |
Add a clock specific flag to switch register accesses to big endian, to
allow runtime configuration of big endian gated clocks.
Signed-off-by: Jonas Gorski
---
V1 -> V2:
* switch from global to local flag
drivers/clk/clk-gate.c | 22 +++---
include/linux/clk-provide
Add a clock specific flag to switch register accesses to big endian, to
allow runtime configuration of big endian fractional divider clocks.
Signed-off-by: Jonas Gorski
---
V1 -> V2:
* newly added patch
drivers/clk/clk-fractional-divider.c | 22 +++---
include/linux/
Add a clock specific flag to switch register accesses to big endian, to
allow runtime configuration of big endian divider clocks.
Signed-off-by: Jonas Gorski
---
V1 -> V2:
* switch from global to local flag
drivers/clk/clk-divider.c| 26 ++
include/linux/
as I got comments (yay). More always welcome of
course :-)
Jonas Gorski (8):
clk: divider: add explicit big endian support
clk: fractional-divider: add explicit big endian support
clk: gate: add explicit big endian support
clk: multiplier: add explicit big endian support
clk: mux:
Switch clk-mux to the endianness aware accessors to allow big endian
mux clocks on a per device level.
Signed-off-by: Jonas Gorski
---
drivers/clk/clk-mux.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/clk-mux.c b/drivers/clk/clk-mux.c
index 2ad2df2e8909
Now that the powerpc clocks are properly marked as big endian, we can
remove the special handling for PowerPC.
Signed-off-by: Jonas Gorski
---
include/linux/clk-provider.h | 16
1 file changed, 16 deletions(-)
diff --git a/include/linux/clk-provider.h b/include/linux/clk
Add a generic flag to mark a clock as big endian register based, and add
accessors following these.
Signed-off-by: Jonas Gorski
---
drivers/clk/clk.c| 1 +
include/linux/clk-provider.h | 27 +++
2 files changed, 28 insertions(+)
diff --git a/drivers/clk
Switch clk-gate to the endianness aware accessors to allow big endian
gated clocks on a per device level.
Signed-off-by: Jonas Gorski
---
drivers/clk/clk-gate.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/clk-gate.c b/drivers/clk/clk-gate.c
index
e that registered basic
clocks.
Jonas Gorski (6):
clk: core: add support for generic big endian accesses
clk: gate: make endian-aware
clk: divider: make endian aware
clk: mux: make endian aware
powerpc/512x: mark clocks as big endian
clk: core: remove powerpc special handling
arc
Switch clk-divider to the endianness aware accessors to allow big endian
divider clocks on a per device level.
Signed-off-by: Jonas Gorski
---
drivers/clk/clk-divider.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk
These clocks' registers are accessed as big endian, so mark them as
such.
Signed-off-by: Jonas Gorski
---
arch/powerpc/platforms/512x/clock-commonclk.c | 13 -
1 file changed, 8 insertions(+), 5 deletions(-)
diff --git a/arch/powerpc/platforms/512x/clock-commonclk.c
b/arch/po
On Wed, Apr 22, 2015 at 10:46 PM, Jonas Gorski wrote:
>> ---
>> v2: Use devm_ioremap_resource() instead of_iomap()
>
> Your subject and commitlog still talk about using of_iomap(), you need
> to update them too.
Hmm I didn't see the V3. Ignore this comment (t
Hi Christophe,
On Wed, Apr 22, 2015 at 4:17 PM, Christophe Leroy
wrote:
> On CPM2, the SPI parameter RAM is dynamically allocated in the
> dualport RAM whereas in CPM1, it is statically allocated to a default
> address with capability to relocate it somewhere else via the use of
> CPM micropatch.
Hi (again),
as usual you only see issues *after* sending the email ...
On Wed, Apr 22, 2015 at 4:17 PM, Christophe Leroy
wrote:
> On CPM2, the SPI parameter RAM is dynamically allocated in the
> dualport RAM whereas in CPM1, it is statically allocated to a default
> address with capability to re
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