[PATCH RFT V2 6/8] powerpc/512x: mark clocks as big endian

[Jonas Gorski]

These clocks' registers are accessed as big endian, so mark them as
such.

Signed-off-by: Jonas Gorski <jonas.gor...@gmail.com>
---
V1 -> V2:
 * switch from global to local flags

 arch/powerpc/platforms/512x/clock-commonclk.c | 11 +++++++----
 1 file changed, 7 insertions(+), 4 deletions(-)

diff --git a/arch/powerpc/platforms/512x/clock-commonclk.c 
b/arch/powerpc/platforms/512x/clock-commonclk.c
index b3097fe6441b..0072330350fa 100644
--- a/arch/powerpc/platforms/512x/clock-commonclk.c
+++ b/arch/powerpc/platforms/512x/clock-commonclk.c
@@ -240,7 +240,8 @@ static inline struct clk *mpc512x_clk_divider(
        u32 __iomem *reg, u8 pos, u8 len, int divflags)
 {
        return clk_register_divider(NULL, name, parent_name, clkflags,
-                                   reg, pos, len, divflags, &clklock);
+                                   reg, pos, len,
+                                   divflags | CLK_DIVIDER_BIG_ENDIAN, 
&clklock);
 }
 
 static inline struct clk *mpc512x_clk_divtable(
@@ -250,7 +251,7 @@ static inline struct clk *mpc512x_clk_divtable(
 {
        u8 divflags;
 
-       divflags = 0;
+       divflags = CLK_DIVIDER_BIG_ENDIAN;
        return clk_register_divider_table(NULL, name, parent_name, 0,
                                          reg, pos, len, divflags,
                                          divtab, &clklock);
@@ -261,10 +262,12 @@ static inline struct clk *mpc512x_clk_gated(
        u32 __iomem *reg, u8 pos)
 {
        int clkflags;
+       u8 gateflags;
 
        clkflags = CLK_SET_RATE_PARENT;
+       gateflags = CLK_GATE_BIG_ENDIAN;
        return clk_register_gate(NULL, name, parent_name, clkflags,
-                                reg, pos, 0, &clklock);
+                                reg, pos, gateflags, &clklock);
 }
 
 static inline struct clk *mpc512x_clk_muxed(const char *name,
@@ -275,7 +278,7 @@ static inline struct clk *mpc512x_clk_muxed(const char 
*name,
        u8 muxflags;
 
        clkflags = CLK_SET_RATE_PARENT;
-       muxflags = 0;
+       muxflags = CLK_MUX_BIG_ENDIAN;
        return clk_register_mux(NULL, name,
                                parent_names, parent_count, clkflags,
                                reg, pos, len, muxflags, &clklock);
-- 
2.13.2