Switch clk-mux to the endianness aware accessors to allow big endian mux clocks on a per device level.
Signed-off-by: Jonas Gorski <jonas.gor...@gmail.com> --- drivers/clk/clk-mux.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/clk/clk-mux.c b/drivers/clk/clk-mux.c index 2ad2df2e8909..4a02db06eb29 100644 --- a/drivers/clk/clk-mux.c +++ b/drivers/clk/clk-mux.c @@ -73,7 +73,7 @@ static u8 clk_mux_get_parent(struct clk_hw *hw) struct clk_mux *mux = to_clk_mux(hw); u32 val; - val = clk_readl(mux->reg) >> mux->shift; + val = clk_hw_readl(hw, mux->reg) >> mux->shift; val &= mux->mask; return clk_mux_val_to_index(hw, mux->table, mux->flags, val); @@ -94,12 +94,12 @@ static int clk_mux_set_parent(struct clk_hw *hw, u8 index) if (mux->flags & CLK_MUX_HIWORD_MASK) { reg = mux->mask << (mux->shift + 16); } else { - reg = clk_readl(mux->reg); + reg = clk_hw_readl(hw, mux->reg); reg &= ~(mux->mask << mux->shift); } val = val << mux->shift; reg |= val; - clk_writel(reg, mux->reg); + clk_hw_writel(hw, reg, mux->reg); if (mux->lock) spin_unlock_irqrestore(mux->lock, flags); -- 2.13.2