Add a generic flag to mark a clock as big endian register based, and add
accessors following these.
Signed-off-by: Jonas Gorski <jonas.gor...@gmail.com>
---
drivers/clk/clk.c | 1 +
include/linux/clk-provider.h | 27 +++++++++++++++++++++++++++
2 files changed, 28 insertions(+)
diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
index 96053a96fe2f..b706022bb83d 100644
--- a/drivers/clk/clk.c
+++ b/drivers/clk/clk.c
@@ -2859,6 +2859,7 @@ static const struct {
ENTRY(CLK_IS_CRITICAL),
ENTRY(CLK_OPS_PARENT_ENABLE),
ENTRY(CLK_DUTY_CYCLE_PARENT),
+ ENTRY(CLK_IS_BIG_ENDIAN),
#undef ENTRY
};
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index b7cf80a71293..2c7c17652d75 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -35,6 +35,7 @@
#define CLK_OPS_PARENT_ENABLE BIT(12)
/* duty cycle call may be forwarded to the parent clock */
#define CLK_DUTY_CYCLE_PARENT BIT(13)
+#define CLK_IS_BIG_ENDIAN BIT(14) /* clk registers are big endian */
struct clk;
struct clk_hw;
@@ -1024,6 +1025,32 @@ static inline void clk_writel(u32 val, u32 __iomem *reg)
#endif /* platform dependent I/O accessors */
+static inline u32 clk_readl_be(u32 __iomem *reg)
+{
+ return ioread32be(reg);
+}
+
+static inline void clk_writel_be(u32 val, u32 __iomem *reg)
+{
+ iowrite32be(val, reg);
+}
+
+static inline u32 clk_hw_readl(struct clk_hw *clk, u32 __iomem *reg)
+{
+ if (clk_hw_get_flags(clk) & CLK_IS_BIG_ENDIAN)
+ return clk_readl_be(reg);
+ else
+ return clk_readl(reg);
+}
+
+static inline void clk_hw_writel(struct clk_hw *clk, u32 val, u32 __iomem *reg)
+{
+ if (clk_hw_get_flags(clk) & CLK_IS_BIG_ENDIAN)
+ clk_writel_be(val, reg);
+ else
+ clk_writel(val, reg);
+}
+
void clk_gate_restore_context(struct clk_hw *hw);
#endif /* CONFIG_COMMON_CLK */
--
2.13.2
