[PATCH RFC/RFT 3/6] clk: divider: make endian aware

[Jonas Gorski]

Switch clk-divider to the endianness aware accessors to allow big endian
divider clocks on a per device level.

Signed-off-by: Jonas Gorski <jonas.gor...@gmail.com>
---
 drivers/clk/clk-divider.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
index e5a17265cfaf..63cb8617a007 100644
--- a/drivers/clk/clk-divider.c
+++ b/drivers/clk/clk-divider.c
@@ -135,7 +135,7 @@ static unsigned long clk_divider_recalc_rate(struct clk_hw 
*hw,
        struct clk_divider *divider = to_clk_divider(hw);
        unsigned int val;
 
-       val = clk_readl(divider->reg) >> divider->shift;
+       val = clk_hw_readl(hw, divider->reg) >> divider->shift;
        val &= clk_div_mask(divider->width);
 
        return divider_recalc_rate(hw, parent_rate, val, divider->table,
@@ -370,7 +370,7 @@ static long clk_divider_round_rate(struct clk_hw *hw, 
unsigned long rate,
        if (divider->flags & CLK_DIVIDER_READ_ONLY) {
                u32 val;
 
-               val = clk_readl(divider->reg) >> divider->shift;
+               val = clk_hw_readl(hw, divider->reg) >> divider->shift;
                val &= clk_div_mask(divider->width);
 
                return divider_ro_round_rate(hw, rate, prate, divider->table,
@@ -420,11 +420,11 @@ static int clk_divider_set_rate(struct clk_hw *hw, 
unsigned long rate,
        if (divider->flags & CLK_DIVIDER_HIWORD_MASK) {
                val = clk_div_mask(divider->width) << (divider->shift + 16);
        } else {
-               val = clk_readl(divider->reg);
+               val = clk_hw_readl(hw, divider->reg);
                val &= ~(clk_div_mask(divider->width) << divider->shift);
        }
        val |= (u32)value << divider->shift;
-       clk_writel(val, divider->reg);
+       clk_hw_writel(hw, val, divider->reg);
 
        if (divider->lock)
                spin_unlock_irqrestore(divider->lock, flags);
-- 
2.13.2