On 18 September 2016 at 22:05, Byungchul Park wrote:
> On Thu, Sep 15, 2016 at 10:33:46AM -0500, Nilay Vaish wrote:
>> On 13 September 2016 at 04:45, Byungchul Park wrote:
>> > @@ -2215,6 +2178,75 @@ cache_hit:
>> > return 1;
>> > }
>> >
On 19 September 2016 at 08:09, Jiri Olsa wrote:
> diff --git a/tools/perf/util/mem-events.h b/tools/perf/util/mem-events.h
> index 7f69bf9d789d..27c6bb5abafb 100644
> --- a/tools/perf/util/mem-events.h
> +++ b/tools/perf/util/mem-events.h
> @@ -2,6 +2,10 @@
> #define __PERF_MEM_EVENTS_H
>
> #inc
On 12 July 2016 at 20:02, Fenghua Yu wrote:
> +1. Terms
> +
> +
> +We use the following terms and concepts in this documentation.
> +
> +RDT: Intel Resoure Director Technology
> +
> +CAT: Cache Allocation Technology
> +
> +CDP: Code and Data Prioritization
> +
> +CBM: Cache Bit Mask
> +
>
On 12 July 2016 at 20:02, Fenghua Yu wrote:
> From: Fenghua Yu
>
> Define two new cpuid leaves for CAT and CDP. The leaves are used in
> x86_capability to avoid hard coded index.
>
> Clean comments for RDT, CAT_L3, and CDP_L3 cpufeatures.
>
> Signed-off-by: Fenghua Yu
> Reviewed-by: Tony Luck
>
On 12 July 2016 at 20:02, Fenghua Yu wrote:
> From: Fenghua Yu
>
> Each cache is described by cacheinfo and is unique in the same index
> across the platform. But there is no id for a cache. We introduce cache
> ID to identify a cache.
>
> Intel Cache Allocation Technology (CAT) allows some contr
On 12 July 2016 at 20:02, Fenghua Yu wrote:
> From: Fenghua Yu
>
> Enable cache id in x86. Cache id comes from APIC ID and CPUID4.
>
I think one of these patches on cache ids should refer to some
documentation from Intel on this subject, either in the commit message
or in the comments in some fi
On 12 July 2016 at 20:02, Fenghua Yu wrote:
> From: Fenghua Yu
>
> rg_list is linked list to connect to other tasks in a rdtgroup.
>
> The point of rdtgroup allows the task to access its own rdtgroup directly.
>
> Signed-off-by: Fenghua Yu
> Reviewed-by: Tony Luck
> ---
> include/linux/sched.h
On 12 July 2016 at 20:02, Fenghua Yu wrote:
> From: Fenghua Yu
>
> Signed-off-by: Fenghua Yu
> Reviewed-by: Tony Luck
> ---
> include/uapi/linux/magic.h | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/include/uapi/linux/magic.h b/include/uapi/linux/magic.h
> index 546b388..655036a 1
On 12 July 2016 at 20:02, Fenghua Yu wrote:
> From: Fenghua Yu
>
> The header mainly provides functions to call from the user interface
> file intel_rdt_rdtgroup.c.
>
> Signed-off-by: Fenghua Yu
> Reviewed-by: Tony Luck
> ---
> arch/x86/include/asm/intel_rdt.h | 87
> +
On 8 September 2016 at 04:57, Fenghua Yu wrote:
> diff --git a/arch/x86/kernel/cpu/intel_rdt.c b/arch/x86/kernel/cpu/intel_rdt.c
> index 9cf3a7d..9f30492 100644
> --- a/arch/x86/kernel/cpu/intel_rdt.c
> +++ b/arch/x86/kernel/cpu/intel_rdt.c
> @@ -21,6 +21,8 @@
> */
> #include
> #include
> +#
On 8 September 2016 at 04:57, Fenghua Yu wrote:
> diff --git a/arch/x86/kernel/cpu/intel_rdt.c b/arch/x86/kernel/cpu/intel_rdt.c
> index 9f30492..4537658 100644
> --- a/arch/x86/kernel/cpu/intel_rdt.c
> +++ b/arch/x86/kernel/cpu/intel_rdt.c
> @@ -141,6 +145,80 @@ static inline bool rdt_cpumask_upd
On 13 September 2016 at 04:45, Byungchul Park wrote:
> @@ -2215,6 +2178,75 @@ cache_hit:
> return 1;
> }
>
> +/*
> + * Look up a dependency chain.
> + */
> +static inline struct lock_chain *lookup_chain_cache(u64 chain_key)
> +{
> + struct hlist_head *hash_head = chainhashentry(chai
On 13 September 2016 at 04:45, Byungchul Park wrote:
> This document describes the concept of crossrelease feature, which
> generalizes what causes a deadlock and how can detect a deadlock.
>
> Signed-off-by: Byungchul Park
> ---
> Documentation/locking/crossrelease.txt | 785
>
On 4 August 2016 at 17:21, Josh Poimboeuf wrote:
> The 'stack_start' variable is similar in usage to 'initial_code' and
> 'initial_gs': they're all stored in head_64.S and they're all updated by
> SMP and ACPI suspend before starting a CPU.
>
> Rename it to 'initial_stack' to be consistent with th
On 4 August 2016 at 17:22, Josh Poimboeuf wrote:
> There are two different pieces of code for starting a CPU: start_cpu0()
> and the end of secondary_startup_64(). They're identical except for the
> stack setup. Combine the common parts into a shared start_cpu()
> function.
>
> Signed-off-by: Jo
On 08/06/16 22:12, David Carrillo-Cisneros wrote:
diff --git a/kernel/events/core.c b/kernel/events/core.c
index 34049cc..77f1bd3 100644
--- a/kernel/events/core.c
+++ b/kernel/events/core.c
@@ -,6 +,26 @@ struct perf_read_data {
int ret;
};
+static int find_cpu_to_read(struct p
On 7 August 2016 at 15:10, David Carrillo-Cisneros wrote:
> Hi Nilay,
>
>>> static int perf_event_read(struct perf_event *event, bool group)
>>> {
>>> - int ret = 0;
>>> + int ret = 0, cpu_to_read;
>>>
>>> - /*
>>> -* If event is enabled and currently active on a CPU, u
On 16 May 2016 at 13:41, Meelis Roos wrote:
> Not sure if this is a genuine warning or a false positive but since some
> UBSAN warnings have been real and google does not find report about this
> specific warning, I'll send it in anyway.
>
> I have seen similar amd pmu warnings from UBSAN but I do
On 22 June 2016 at 04:08, Wang Nan wrote:
> @@ -1916,3 +1922,24 @@ perf_evlist__find_evsel_by_str(struct perf_evlist
> *evlist,
>
> return NULL;
> }
> +
> +struct perf_evlist *perf_evlist__new_aux(struct perf_evlist *parent)
> +{
> + struct perf_evlist *evlist;
> +
> + if (p
On 22 June 2016 at 04:08, Wang Nan wrote:
> @@ -549,17 +573,72 @@ static struct perf_event_header finished_round_event = {
> .type = PERF_RECORD_FINISHED_ROUND,
> };
>
> -static int record__mmap_read_all(struct record *rec)
> +static void
> +record__toggle_overwrite_evsels(struct record *
On 23 June 2016 at 00:27, Wang Nan wrote:
> An auxiliary evlist is created by perf_evlist__new_aux() using an
> existing evlist as its parent. An auxiliary evlist can have its own
> 'struct perf_mmap', but can't have any other data. User should use its
> parent instead when accessing other data.
>
On 23 June 2016 at 00:27, Wang Nan wrote:
> @@ -542,6 +568,79 @@ static struct perf_event_header finished_round_event = {
> .type = PERF_RECORD_FINISHED_ROUND,
> };
>
> +static void
> +record__toggle_overwrite_evsels(struct record *rec,
> + enum overwrite_evt
On 23 June 2016 at 09:31, pi3orama wrote:
>
>
> 发自我的 iPhone
>
>> 在 2016年6月23日，下午10:27，Nilay Vaish 写道：
>>
>>> On 23 June 2016 at 00:27, Wang Nan wrote:
>>> @@ -542,6 +568,79 @@ static struct perf_event_header finished_round_event =
>>&
Naveen, can you point out where in the patch you update the variable:
idx, a member of codegen_contex structure? Somehow I am unable to
figure it out. I can only see that we set it to 0 in the
bpf_int_jit_compile function. Since all your test cases pass, I am
clearly overlooking something.
Than
On 12 July 2016 at 20:02, Fenghua Yu wrote:
> diff --git a/arch/x86/include/asm/intel_rdt.h
> b/arch/x86/include/asm/intel_rdt.h
> index 4f45dc8..afb6da3 100644
> --- a/arch/x86/include/asm/intel_rdt.h
> +++ b/arch/x86/include/asm/intel_rdt.h
> @@ -3,14 +3,42 @@
>
> #ifdef CONFIG_INTEL_RDT
>
> +
On 12 July 2016 at 20:02, Fenghua Yu wrote:
> From: Vikas Shivappa
>
> Adds support for IA32_PQR_ASSOC MSR writes during task scheduling. For
> Cache Allocation, MSR write would let the task fill in the cache
> 'subset' represented by the task's capacity bit mask.
>
> The high 32 bits in the per
On 12 July 2016 at 20:02, Fenghua Yu wrote:
> diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
> index 0fe6953..42c90cb 100644
> --- a/arch/x86/kernel/cpu/common.c
> +++ b/arch/x86/kernel/cpu/common.c
> @@ -711,6 +711,21 @@ void get_cpu_cap(struct cpuinfo_x86 *c)
>
On 12 July 2016 at 20:02, Fenghua Yu wrote:
> From: Vikas Shivappa
>
> On Intel SKUs that support Code Data Prioritization(CDP), intel_rdt
> operates in 2 modes - legacy cache allocation mode/default or CDP mode.
>
> When CDP is enabled, the number of available CLOSids is halved. Hence the
> enab
On 24 May 2016 at 14:52, Andi Kleen wrote:
> From: Andi Kleen
>
> diff --git a/tools/perf/builtin-stat.c b/tools/perf/builtin-stat.c
> index 715a1128daeb..dab184d86816 100644
> --- a/tools/perf/builtin-stat.c
> +++ b/tools/perf/builtin-stat.c
> @@ -59,10 +59,13 @@
> #include "util/thread.h"
> #
On 24 May 2016 at 14:52, Andi Kleen wrote:
> +static double td_be_bound(int ctx, int cpu)
> +{
> + double sum = (td_fe_bound(ctx, cpu) +
> + td_bad_spec(ctx, cpu) +
> + td_retiring(ctx, cpu));
> + if (sum == 0)
> + return 0;
> +
This patch looks fine to me.
--
Nilay
On 1 June 2016 at 10:24, Andi Kleen wrote:
>
> Here's an updated patch addresses the duplicated issue and explicitly frees
> memory.
>
> ---
>
> Add basic plumbing for TopDown in perf stat
>
> TopDown is intended to replace the frontend cycles idle/
> backe
June 2016 at 09:56, Andi Kleen wrote:
> On Wed, Jun 01, 2016 at 09:50:07AM -0500, Nilay Vaish wrote:
>> On 24 May 2016 at 14:52, Andi Kleen wrote:
>> > +static double td_be_bound(int ctx, int cpu)
>> > +{
>> > + double sum = (td_fe_bound(ctx, cpu) +
>&g
On 7 October 2016 at 21:45, Fenghua Yu wrote:
> From: Fenghua Yu
> diff --git a/arch/x86/kernel/cpu/intel_rdt_rdtgroup.c
> b/arch/x86/kernel/cpu/intel_rdt_rdtgroup.c
> index 28df92e..efcbfe7 100644
> --- a/arch/x86/kernel/cpu/intel_rdt_rdtgroup.c
> +++ b/arch/x86/kernel/cpu/intel_rdt_rdtgroup.c
On 10 October 2016 at 11:45, Luck, Tony wrote:
> On Sat, Oct 08, 2016 at 12:11:08PM -0500, Nilay Vaish wrote:
>> On 7 October 2016 at 21:45, Fenghua Yu wrote:
>> > From: Fenghua Yu
>
>> > + caches typically exist per core, but there may not be a
>
On 8 October 2016 at 14:52, Borislav Petkov wrote:
> On Sat, Oct 08, 2016 at 01:54:54PM -0700, Fenghua Yu wrote:
>> > I think these #defines are specific to Intel. I would prefer if we
>> > have _INTEL_ somewhere in them.
>
> We don't generally add vendor names to those defines. Even more so if
>
On 10 October 2016 at 12:19, Luck, Tony wrote:
> On Sat, Oct 08, 2016 at 01:33:06PM -0700, Fenghua Yu wrote:
>> On Sat, Oct 08, 2016 at 12:12:07PM -0500, Nilay Vaish wrote:
>> > On 7 October 2016 at 21:45, Fenghua Yu wrote:
>> > > From: Fenghua Yu
>> &
On 13 October 2016 at 05:59, Stephane Eranian wrote:
> diff --git a/tools/perf/jvmti/libjvmti.c b/tools/perf/jvmti/libjvmti.c
> index ac12e4b91a92..2d9bc04b79a8 100644
> --- a/tools/perf/jvmti/libjvmti.c
> +++ b/tools/perf/jvmti/libjvmti.c
> @@ -12,6 +12,17 @@
> static int has_line_numbers;
> vo
On 7 October 2016 at 21:45, Fenghua Yu wrote:
> From: Fenghua Yu
>
> Add an ABI document entry for /sys/devices/system/cpu/cpu*/cache/index*/id.
>
> Signed-off-by: Fenghua Yu
> Signed-off-by: Tony Luck
> ---
> Documentation/ABI/testing/sysfs-devices-system-cpu | 16
> 1 file c
On 7 October 2016 at 21:45, Fenghua Yu wrote:
> From: Fenghua Yu
>
> Check CPUID leaves for all the Resource Director Technology (RDT)
> Cache Allocation Technology (CAT) bits.
>
> Prescence of allocation features:
Presence
> diff --git a/arch/x86/include/asm/cpufeatures.h
> b/arch/x86/include
On 7 October 2016 at 21:45, Fenghua Yu wrote:
> From: Fenghua Yu
>
> +L3 details (code and data prioritization disabled)
> +--
> +With CDP disabled the L3 schemata format is:
> +
> + L3:=;=;...
> +
> +L3 details (CDP enabled via mount option t
On 7 October 2016 at 21:45, Fenghua Yu wrote:
> From: Fenghua Yu
>
> diff --git a/drivers/base/cacheinfo.c b/drivers/base/cacheinfo.c
> index e9fd32e..2a21c15 100644
> --- a/drivers/base/cacheinfo.c
> +++ b/drivers/base/cacheinfo.c
> @@ -233,6 +233,7 @@ static ssize_t file_name##_show(struct devi
On 7 October 2016 at 21:45, Fenghua Yu wrote:
> From: Tony Luck
>
> diff --git a/arch/x86/include/asm/intel_rdt.h
> b/arch/x86/include/asm/intel_rdt.h
> index 251ac2a..bad8dc7 100644
> --- a/arch/x86/include/asm/intel_rdt.h
> +++ b/arch/x86/include/asm/intel_rdt.h
> @@ -40,6 +40,39 @@ struct rdt
On 7 October 2016 at 21:45, Fenghua Yu wrote:
> From: Fenghua Yu
>
> diff --git a/arch/x86/include/asm/intel_rdt.h
> b/arch/x86/include/asm/intel_rdt.h
> index bad8dc7..f63815c 100644
> --- a/arch/x86/include/asm/intel_rdt.h
> +++ b/arch/x86/include/asm/intel_rdt.h
> @@ -2,6 +2,23 @@
> #define
On 19 October 2016 at 17:01, Jin Yao wrote:
> diff --git a/tools/perf/util/callchain.h b/tools/perf/util/callchain.h
> index 40ecf25..4f6bf6c 100644
> --- a/tools/perf/util/callchain.h
> +++ b/tools/perf/util/callchain.h
> @@ -115,6 +115,10 @@ struct callchain_list {
> bool
On 20 October 2016 at 11:48, Andi Kleen wrote:
> On Thu, Oct 20, 2016 at 11:41:11AM -0500, Nilay Vaish wrote:
>> On 19 October 2016 at 17:01, Jin Yao wrote:
>> > diff --git a/tools/perf/util/callchain.h b/tools/perf/util/callchain.h
>> > index 40ecf25..4f6bf6c 100644
On 4 August 2016 at 17:22, Josh Poimboeuf wrote:
> diff --git a/arch/x86/kernel/unwind_frame.c b/arch/x86/kernel/unwind_frame.c
> new file mode 100644
> index 000..f28f1b5
> --- /dev/null
> +++ b/arch/x86/kernel/unwind_frame.c
> @@ -0,0 +1,84 @@
> +#include
> +#include
> +#include
> +#inclu
On 9 August 2016 at 17:28, David Carrillo-Cisneros wrote:
> Introduce the flag PMU_EV_CAP_READ_ACTIVE_PKG, useful for uncore events,
> that allows a PMU to signal the generic perf code that an event is readable
> in the current CPU if the event is active in a CPU in the same package as
> the curre
| 2 ++
> arch/x86/events/intel/uncore.c | 2 ++
> arch/x86/events/intel/uncore_snb.c | 2 ++
> include/linux/perf_event.h | 21 +++
> kernel/events/core.c | 52
> +++++-----
> 5 files changed, 57 insertions(+), 22 deletions(-)
>
> --
> 2.8.0.rc3.226.g39d4020
>
Reviewed-by: Nilay Vaish
On 28 August 2016 at 16:00, Madhavan Srinivasan
wrote:
> Patchset to extend PERF_SAMPLE_REGS_INTR to include
> platform specific PMU registers.
>
> Patchset applies cleanly on tip:perf/core branch
>
> It's a perennial request from hardware folks to be able to
> see the raw values of the pmu regist
On 28 August 2016 at 16:00, Madhavan Srinivasan
wrote:
> diff --git a/kernel/events/core.c b/kernel/events/core.c
> index 274288819829..e16bf4d057d1 100644
> --- a/kernel/events/core.c
> +++ b/kernel/events/core.c
> @@ -5371,16 +5371,24 @@ u64 __attribute__((weak)) perf_arch_reg_value(struct
> pe
On 15 August 2016 at 09:12, Liang, Kan wrote:
>
>
>> > diff --git a/arch/x86/events/intel/uncore_snbep.c
>> > b/arch/x86/events/intel/uncore_snbep.c
>> > index 3719af5..55a081e 100644
>> > --- a/arch/x86/events/intel/uncore_snbep.c
>> > +++ b/arch/x86/events/intel/uncore_snbep.c
>> > +
>> > +stati
On 12 August 2016 at 09:28, Josh Poimboeuf wrote:
> The frame at the end of each idle task stack has a zeroed return
> address. This is inconsistent with real task stacks, which have a real
> return address at that spot. This inconsistency can be confusing for
> stack unwinders.
>
> Make it a re
On 26 June 2016 at 06:20, He Kuang wrote:
> From: Wang Nan
>
> This patch copies "include/linux/math64.h" into
> "tools/include/linux/math64.h" and copies
> "include/asm-generic/div64.h" into
> "tools/include/asm-generic/div64.h", to enable other libraries use
> arithmetic operation defined in th
On 28 June 2016 at 06:29, Jiri Olsa wrote:
> Adding -F/--dont-fork option to bypass forking
> for each test. It's useful for debugging test.
>
> Link: http://lkml.kernel.org/n/tip-yq9gy0fcr8nl70986gwnl...@git.kernel.org
> Signed-off-by: Jiri Olsa
> ---
> tools/perf/Documentation/perf-test.txt |
On 28 June 2016 at 06:29, Jiri Olsa wrote:
> I hit a bug when running test suite without forking
> each test (-F option):
>
> $ perf test -Fv
> ...
> 34: Test thread map :
> --- start ---
> FAILED tests/thread-map.c:24 wrong comm
> end
On 28 June 2016 at 06:29, Jiri Olsa wrote:
> I hit a bug when running test suite without forking
> each test (-F option):
>
> $ perf test -F dso
>8: Test dso data read : Ok
>9: Test dso data cache : FAILED!
> 10
On 29 June 2016 at 11:07, Arnaldo Carvalho de Melo
wrote:
> Em Wed, Jun 29, 2016 at 11:04:01AM -0500, Nilay Vaish escreveu:
>> On 28 June 2016 at 06:29, Jiri Olsa wrote:
>> > Adding -F/--dont-fork option to bypass forking
>> > for each test. It's useful for debu
On 29 June 2016 at 11:06, Nilay Vaish wrote:
> On 28 June 2016 at 06:29, Jiri Olsa wrote:
>> I hit a bug when running test suite without forking
>> each test (-F option):
>>
>> $ perf test -Fv
>> ...
>> 34: Test thread map
On 29 June 2016 at 11:05, Nilay Vaish wrote:
> On 28 June 2016 at 06:29, Jiri Olsa wrote:
>> I hit a bug when running test suite without forking
>> each test (-F option):
>>
>> $ perf test -F dso
>>8: Test dso data read
On 8 September 2016 at 04:56, Fenghua Yu wrote:
> diff --git a/include/linux/cacheinfo.h b/include/linux/cacheinfo.h
> index 2189935..cf6984d 100644
> --- a/include/linux/cacheinfo.h
> +++ b/include/linux/cacheinfo.h
> @@ -18,6 +18,7 @@ enum cache_type {
>
> /**
> * struct cacheinfo - represent
On 8 September 2016 at 14:33, Thomas Gleixner wrote:
> On Thu, 8 Sep 2016, Fenghua Yu wrote:
>> +What:/sys/devices/system/cpu/cpu*/cache/index*/id
>> +Date:July 2016
>> +Contact: Linux kernel mailing list
>> +Description: Cache id
>> +
>> + The id i
On 8 September 2016 at 04:57, Fenghua Yu wrote:
> diff --git a/arch/x86/kernel/cpu/intel_rdt.c b/arch/x86/kernel/cpu/intel_rdt.c
> index fcd0642..b25940a 100644
> --- a/arch/x86/kernel/cpu/intel_rdt.c
> +++ b/arch/x86/kernel/cpu/intel_rdt.c
> @@ -21,17 +21,94 @@
> */
> #include
> #include
>
On 8 September 2016 at 04:57, Fenghua Yu wrote:
> diff --git a/arch/x86/kernel/cpu/intel_rdt.c b/arch/x86/kernel/cpu/intel_rdt.c
> index b25940a..9cf3a7d 100644
> --- a/arch/x86/kernel/cpu/intel_rdt.c
> +++ b/arch/x86/kernel/cpu/intel_rdt.c
> @@ -31,8 +31,22 @@ static struct clos_cbm_table *cctabl
On 3 September 2016 at 09:50, Nicolas Iooss wrote:
>
> arch/x86/tools/relocs.c:460:5: error: format specifies type 'int'
> but the argument has type 'Elf64_Xword' (aka 'unsigned long')
> [-Werror,-Wformat]
> sec->shdr.sh_size);
>
On 2 September 2016 at 08:59, Wang Nan wrote:
> Hugetlbfs mapping should be recognized as anon mapping so user has
> a chance to create /tmp/perf-.map file for symbol resolving. This
> patch utilizes MAP_HUGETLB to identify hugetlb mapping.
>
> After this patch, if perf is started before the progr
h | 1 +
> tools/perf/util/event.c | 7 +++
> tools/perf/util/map.c | 8 +---
> 4 files changed, 28 insertions(+), 3 deletions(-)
>
> Signed-off-by: Wang Nan
> Cc: Hou Pengyang
> Cc: He Kuang
> Cc: Arnaldo Carvalho de Melo
Reviewed-by: Nilay Vaish
F32_ST_VISIBILITY(o)
>
> +/* printf format for Elf32_Off */
> +#define PRIuELF PRIu32
> +
> #include "relocs.c"
> diff --git a/arch/x86/tools/relocs_64.c b/arch/x86/tools/relocs_64.c
> index 56b61b743c4c..2cf4de5c9d99 100644
> --- a/arch/x86/tools/relocs_64.c
> +
On 1 October 2016 at 06:45, Srinivas Pandruvada
wrote:
> diff --git a/kernel/sched/core.c b/kernel/sched/core.c
> index e86c4a5..08135ca 100644
> --- a/kernel/sched/core.c
> +++ b/kernel/sched/core.c
> @@ -6237,7 +6237,25 @@ static void init_sched_groups_capacity(int cpu, struct
> sched_domain *s
On 13 September 2016 at 04:45, Byungchul Park wrote:
> This document describes the concept of crossrelease feature, which
> generalizes what causes a deadlock and how can detect a deadlock.
>
> Signed-off-by: Byungchul Park
> ---
> Documentation/locking/crossrelease.txt | 785
>
On 10 August 2016 at 08:53, Steven Rostedt wrote:
> diff --git a/kernel/trace/trace_hwlat.c b/kernel/trace/trace_hwlat.c
> new file mode 100644
> index ..08dfabe4e862
> --- /dev/null
> +++ b/kernel/trace/trace_hwlat.c
> @@ -0,0 +1,527 @@
> +/*
> + * trace_hwlatdetect.c - A simple Hardw
On 12 August 2016 at 09:28, Josh Poimboeuf wrote:
> There are two different pieces of code for starting a CPU: start_cpu0()
> and the end of secondary_startup_64(). They're identical except for the
> stack setup. Combine the common parts into a shared start_cpu()
> function.
>
> Signed-off-by: J
On 12 August 2016 at 16:30, Kan Liang wrote:
> From: Kan Liang
>
> The method to build PCI bus to socket mapping is similar among
> platforms. However, the PCI location where store Node ID mapping could
I think we should replace "where store" with "which store".
> vary for different platforms.
On 12 August 2016 at 16:30, Kan Liang wrote:
> From: Kan Liang
>
> This patch implements the uncore monitoring driver for Skylake server.
> The uncore subsystem in Skylake server is similar to previous
> server. There are some differences in config register encoding and pci
> device IDs. Besides,
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