On 12 July 2016 at 20:02, Fenghua Yu <fenghua...@intel.com> wrote: > From: Fenghua Yu <fenghua...@intel.com> > > Enable cache id in x86. Cache id comes from APIC ID and CPUID4. >
I think one of these patches on cache ids should refer to some documentation from Intel on this subject, either in the commit message or in the comments in some file. I found one: https://software.intel.com/sites/default/files/63/1a/Kuo_CpuTopology_rc1.rh1.final.pdf. You would know better than me which document we should be looking at. Thanks Nilay
