On 7 October 2016 at 21:45, Fenghua Yu <fenghua...@intel.com> wrote: > From: Fenghua Yu <fenghua...@intel.com> > > Check CPUID leaves for all the Resource Director Technology (RDT) > Cache Allocation Technology (CAT) bits. > > Prescence of allocation features:
Presence > diff --git a/arch/x86/include/asm/cpufeatures.h > b/arch/x86/include/asm/cpufeatures.h > index 92a8308..64dd8274 100644 > --- a/arch/x86/include/asm/cpufeatures.h > +++ b/arch/x86/include/asm/cpufeatures.h > @@ -196,6 +196,10 @@ > > #define X86_FEATURE_INTEL_PT ( 7*32+15) /* Intel Processor Trace */ > > +#define X86_FEATURE_CAT_L3 ( 7*32+16) /* Cache Allocation Technology L3 > */ > +#define X86_FEATURE_CAT_L2 ( 7*32+17) /* Cache Allocation Technology L2 > */ > +#define X86_FEATURE_CDP_L3 ( 7*32+18) /* Code and Data Prioritization L3 > */ > + > /* Virtualization flags: Linux defined, word 8 */ > #define X86_FEATURE_TPR_SHADOW ( 8*32+ 0) /* Intel TPR Shadow */ > #define X86_FEATURE_VNMI ( 8*32+ 1) /* Intel Virtual NMI */ > @@ -220,6 +224,7 @@ > #define X86_FEATURE_RTM ( 9*32+11) /* Restricted > Transactional Memory */ > #define X86_FEATURE_CQM ( 9*32+12) /* Cache QoS Monitoring */ > #define X86_FEATURE_MPX ( 9*32+14) /* Memory Protection > Extension */ > +#define X86_FEATURE_RDT_A ( 9*32+15) /* Resource Director Technology > Allocation */ > #define X86_FEATURE_AVX512F ( 9*32+16) /* AVX-512 Foundation */ > #define X86_FEATURE_AVX512DQ ( 9*32+17) /* AVX-512 DQ (Double/Quad > granular) Instructions */ > #define X86_FEATURE_RDSEED ( 9*32+18) /* The RDSEED instruction */ I think these #defines are specific to Intel. I would prefer if we have _INTEL_ somewhere in them. -- Nilay
