On 7 October 2016 at 21:45, Fenghua Yu <fenghua...@intel.com> wrote: > From: Fenghua Yu <fenghua...@intel.com> > > +L3 details (code and data prioritization disabled) > +-------------------------------------------------- > +With CDP disabled the L3 schemata format is: > + > + L3:<cache_id0>=<cbm>;<cache_id1>=<cbm>;... > + > +L3 details (CDP enabled via mount option to resctrl) > +---------------------------------------------------- > +When CDP is enabled, you need to specify separate cache bit masks for > +code and data access. The generic format is: > + > + L3:<cache_id0>=<d_cbm>,<i_cbm>;<cache_id1>=<d_cbm>,<i_cbm>;...
Can we drop L3 here and instead say: L<level>:<cache_id0>=<d_cbm>,<i_cbm>;<cache_id1>=<d_cbm>,<i_cbm>;... and similarly for without CDP as well. -- Nilay
