rq_domain_free(struct irq_domain *domain,
>
Looks good to me. Thanks for the fix.
Acked-by: Ray Jui
smime.p7s
Description: S/MIME Cryptographic Signature
a6_phy0: sata-phy@0 {
> - reg = <0>;
> - #phy-cells = <0>;
> - };
> - };
> -
> - sata7: ahci@13 {
> - compatible = "brcm,iproc-ahci", "generic-ahci";
> - reg = <0x0013 0x1000>;
> - reg-names = "ahci";
> - interrupts = ;
> - #address-cells = <1>;
> - #size-cells = <0>;
> - status = "disabled";
> -
> - sata7_port0: sata-port@0 {
> - reg = <0>;
> - phys = <&sata7_phy0>;
> - phy-names = "sata-phy";
> - };
> - };
> -
> - sata_phy7: sata_phy@132100 {
> - compatible = "brcm,iproc-sr-sata-phy";
> - reg = <0x00132100 0x1000>;
> - reg-names = "phy";
> - #address-cells = <1>;
> - #size-cells = <0>;
> - status = "disabled";
> -
> - sata7_phy0: sata-phy@0 {
> - reg = <0>;
> - #phy-cells = <0>;
> - };
> - };
> - };
> diff --git a/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi
> b/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi
> index b425b12c3ed2..2ffb2c92182a 100644
> --- a/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi
> +++ b/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi
> @@ -285,7 +285,6 @@
> };
>
> #include "stingray-fs4.dtsi"
> - #include "stingray-sata.dtsi"
> #include "stingray-pcie.dtsi"
> #include "stingray-usb.dtsi"
>
> @@ -309,12 +308,6 @@
> #size-cells = <0>;
> };
>
> - mdio@2 { /* SATA */
> - reg = <0x2>;
> - #address-cells = <1>;
> - #size-cells = <0>;
> - };
> -
> mdio@3 { /* USB */
> reg = <0x3>;
> #address-cells = <1>;
>
The entire change looks good to me!
Acked-by: Ray Jui
smime.p7s
Description: S/MIME Cryptographic Signature
he interconnect can only address up
> + * to 40-bit
> + */
> + dma-ranges = <0 0 0 0 0x100 0x0>;
> +
Should have had my signed-off since during our internal review, I added
the above comment to explain why we set it to 40-bit here despite th
On 1/15/2021 2:09 AM, Jiapeng Zhong wrote:
> Fix the follow coccicheck warnings:
>
> ./drivers/pinctrl/bcm/pinctrl-ns2-mux.c:856:29-38: WARNING:
> Comparison to bool.
>
Sorry I must be missing something here. Why is there a warning while
'pull_up' and 'pull_down' are already of type 'bool' and
>> Yes we can set the "dma-rages" to 40 bit DMA ranges. Tested, it is working.
>>>
>>> -Original Message-
>>> From: Ray Jui
>>>
>>> Bharat can correct me if I'm wrong, but I don't think we have a bug in
>>> the
On 1/12/2021 12:40 PM, Arnd Bergmann wrote:
> On Tue, Jan 12, 2021 at 7:28 PM Ray Jui wrote:
>> On 2020-12-15 7:49 a.m., Arnd Bergmann wrote:
>>> On Tue, Dec 15, 2020 at 4:41 PM Florian Fainelli
>>> wrote:
>>>>
>>>> On 12/15/2020 5:19 AM, Bh
Hi Arnd,
On 2020-12-15 7:49 a.m., Arnd Bergmann wrote:
On Tue, Dec 15, 2020 at 4:41 PM Florian Fainelli wrote:
On 12/15/2020 5:19 AM, Bharat Gooty wrote:
Since the IOMMU is disabled and DMA engine is on 32-bit bus, We can not
give the complete DDR for the USB DMA.
So restricting the usable D
On 12/16/2020 8:08 PM, Rayagonda Kokatanur wrote:
> On Wed, Dec 2, 2020 at 11:14 PM Ray Jui wrote:
>>
>>
>>
>> On 12/2/2020 6:35 AM, Wolfram Sang wrote:
>>>
>>>> All review comments are scattered now, please let me know what has to be
>>&g
+ Bharat
On 11/28/2020 1:58 AM, Arnd Bergmann wrote:
> On Sat, Nov 28, 2020 at 5:53 AM Florian Fainelli wrote:
>>
>> On Fri, 16 Oct 2020 17:08:32 +0800, Zhen Lei
>> wrote:
>>> The scripts/dtc/checks.c requires that the node have empty "dma-ranges"
>>> property must have the same "#address-cells
s done, we can make a decision between keeping the
tasklet based approach vs irq thread.
Thanks.
> If nothing to be done, please acknowledge the patch.
>
> Best regards,
> Raygonda
>
>
> On Sat, Nov 14, 2020 at 6:47 AM Dhananjay Phadke
> mailto:dpha...@linux
On 12/2/2020 6:35 AM, Wolfram Sang wrote:
>
>> All review comments are scattered now, please let me know what has to be
>> done further,
>> Are we going to change the tasklet to irq thread ?
>> Are we going to remove batching 64 packets if transaction > 64B and use rx
>> fifo threshold ?
>>
>> I
ile changed, 22 insertions(+), 7 deletions(-)
>> I need Ray a/o Scott ACK to proceed.
> Let's see if Ray has anything to add.
>
> Acked-by: Scott Branden
I reviewed them internally before they were sent out. I just reviewed
them again and yes they look fine to me.
1/3 and 2/3 are critical fixes for kernel crash and boot up issue in
corner cases (Fixes tag already applied and should be picked up by LTS
once merged).
Thanks.
Acked-by: Ray Jui
>>
>> Thanks,
>> Lorenzo
>
smime.p7s
Description: S/MIME Cryptographic Signature
EN, gpio, true);
> raw_spin_unlock_irqrestore(&chip->lock, flags);
>
> dev_dbg(chip->dev, "gpio:%u set output, value:%d\n", gpio, val);
>
The fix looks good to me. Thanks!
Acked-by: Ray Jui
smime.p7s
Description: S/MIME Cryptographic Signature
OC_GPIO_OUT_EN_OFFSET, gpio, true);
> raw_spin_unlock_irqrestore(&chip->lock, flags);
>
> dev_dbg(chip->dev, "gpio:%u set output, value:%d\n", gpio, val);
>
Thanks. The fix looks good. Would you be able to also help fix this in
pinctrl-nsp-gpio.c ?
Acked-by: Ray Jui
smime.p7s
Description: S/MIME Cryptographic Signature
On 11/9/2020 8:23 PM, Rayagonda Kokatanur wrote:
> Hi Ray,
>
> Could you please check Dhananjay comments and update your thoughts.
>
> On Fri, Nov 6, 2020 at 11:11 PM Dhananjay Phadke
> wrote:
>>
>> On Thu, 5 Nov 2020 15:13:04 +0530, Rayagonda Kokatanur wrote:
So the suggestion was to set
On 11/3/2020 7:57 PM, Rayagonda Kokatanur wrote:
> On Wed, Nov 4, 2020 at 9:05 AM Florian Fainelli wrote:
>>
>>
>>
>> On 11/2/2020 10:19 PM, Dhananjay Phadke wrote:
>>> On Mon, 2 Nov 2020 09:24:32 +0530, Rayagonda Kokatanur wrote:
>>>
Handle single or multi byte master read request with or
On 10/26/2020 8:13 AM, Rayagonda Kokatanur wrote:
> Hi Dhanajay,
>
> On Fri, Oct 23, 2020 at 11:12 PM Ray Jui wrote:
>>
>>
>>
>> On 10/12/2020 3:03 PM, Dhananjay Phadke wrote:
>>> From: Rayagonda Kokatanur
>>>
>>> On Sun, 11 Oct 2020
On 10/12/2020 3:03 PM, Dhananjay Phadke wrote:
> From: Rayagonda Kokatanur
>
> On Sun, 11 Oct 2020 23:52:54 +0530, Rayagonda Kokatanur wrote:
>> Add code to handle IS_S_RX_FIFO_FULL_SHIFT interrupt to support
>> master write request with >= 64 bytes.
>>
>> Iproc has a slave rx fifo size of 64 b
On 10/13/2020 10:12 PM, Rayagonda Kokatanur wrote:
>
>
> On Wed, Oct 14, 2020 at 8:50 AM Dhananjay Phadke
> mailto:dpha...@linux.microsoft.com>> wrote:
>
> On Sun, 11 Oct 2020 23:52:53 +0530, Rayagonda Kokatanur wrote:
> > --- a/drivers/i2c/busses/i2c-bcm-iproc.c
> > +++ b/drivers/
On 10/11/2020 11:22 AM, Rayagonda Kokatanur wrote:
> Fix typo in bcm_iproc_i2c_slave_isr().
>
> Fixes: c245d94ed106 ("i2c: iproc: Add multi byte read-write support for slave
> mode")
This is merely a fix of typo in code comment and there's no functional
impact. Why do we need a Fixes tag on th
+ | BIT(IS_S_TX_UNDERRUN_SHIFT) | BIT(IS_S_RX_FIFO_FULL_SHIFT)\
> + | BIT(IS_S_RX_THLD_SHIFT))
>
> static int bcm_iproc_i2c_reg_slave(struct i2c_client *slave);
> static int bcm_iproc_i2c_unreg_slave(struct i2c_client *slave);
>
Acked-by: Ray Jui
smime.p7s
Description: S/MIME Cryptographic Signature
iproc_i2c, IS_OFFSET);
> + /* process only slave interrupt which are enabled */
> + slave_status = status & iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET) &
> +ISR_MASK_SLAVE;
> +
> + if (slave_status) {
> + ret = bcm_iproc_i2c_slave_is
ted read transaction\n");
> /* re-initialize i2c for recovery */
> bcm_iproc_i2c_enable_disable(iproc_i2c, false);
> bcm_iproc_i2c_slave_init(iproc_i2c, true);
>
This looks fine to me. Thanks.
Acked-by: Ray Jui
smime.p7s
Description: S/MIME Cryptographic Signature
quot;Hauke Mehrtens");
> MODULE_DESCRIPTION("Broadcom iProc PCIe BCMA driver");
>
Looks good to me. Thanks.
Acked-by: Ray Jui
The Broadcom QSPI driver now falls back to no MSPI_DEV support as the
default setting in the generic compatible string, explicit settings for
STB chips 7425, 7429, and 7435 can be removed.
Signed-off-by: Ray Jui
---
drivers/spi/spi-bcm-qspi.c | 12
1 file changed, 12 deletions
Add compatible string for BRCMSTB 7445 SoCs and indicate it has MSPI rev
support.
Signed-off-by: Ray Jui
---
drivers/spi/spi-bcm-qspi.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/spi/spi-bcm-qspi.c b/drivers/spi/spi-bcm-qspi.c
index 681d09085175..c5209b42b0d2 100644
--- a
kernel.org/linux-arm-kernel/20200909211857.4144718-1-f.faine...@gmail.com/T/#u
Signed-off-by: Ray Jui
---
drivers/spi/spi-bcm-qspi.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/spi/spi-bcm-qspi.c b/drivers/spi/spi-bcm-qspi.c
index c5209b42b0d2..b78d47a4403c 10
Add compatible string for brcmstb 7445 SoCs.
Signed-off-by: Ray Jui
---
Documentation/devicetree/bindings/spi/brcm,spi-bcm-qspi.txt | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/spi/brcm,spi-bcm-qspi.txt
b/Documentation/devicetree/bindings/spi/brcm,spi
procslow>, <&iprocslow>;
> - clock-names = "wdogclk", "apb_pclk";
> + clock-names = "wdog_clk", "apb_pclk";
> };
>
> lcpll0: lcpll0@3f100 {
>
Reviewed-by: Ray Jui
= <&axi81_clk>;
> - clock-names = "apb_pclk";
> + clocks = <&axi81_clk>, <&axi81_clk>;
> + clock-names = "wdog_clk", "apb_pclk";
> };
>
> gpio_ccm: gpio@1800a000 {
>
Reviewed-by: Ray Jui
clocks = <&hsls_25m_div2_clk>, <&hsls_div4_clk>;
> - clock-names = "wdogclk", "apb_pclk";
> + clock-names = "wdog_clk", "apb_pclk";
> timeout-sec = <60>;
> };
>
>
Although not currently used in the driver, this indeed should be fixed
to match DT documentation and be ready for future clock support in the
driver (i.e., getting clock by name).
Reviewed-by: Ray Jui
On 8/19/2020 1:49 PM, Florian Fainelli wrote:
> On 8/19/20 1:48 PM, Christian Lamparter wrote:
>> On 2020-08-19 06:23, Florian Fainelli wrote:
>>> The pin controller resources start at 0xc0 from the CRU base which is at
>>> 0x100 from th DMU base, for a final address of 0x1800_c1c0, whereas we
>
; ranges;
> #address-cells = <1>;
> #size-cells = <1>;
>
> - pin-controller@1c0 {
> - compatible = "brcm,bcm4708-pinmux";
> - reg = <0x1c0 0x24>;
> + pinctrl: pin-controller@c0 {
> + compatible = "brcm,bcm53012-pinmux";
> + reg = <0xc0 0x24>;
> reg-names = "cru_gpio_control";
>
> spi-pins {
>
Reviewed-by: Ray Jui
On 8/12/2020 1:06 PM, Wolfram Sang wrote:
> On Mon, Aug 10, 2020 at 05:42:40PM -0700, Dhananjay Phadke wrote:
>> When i2c client unregisters, synchronize irq before setting
>> iproc_i2c->slave to NULL.
>>
>> (1) disable_irq()
>> (2) Mask event enable bits in control reg
>> (3) Erase slave addres
Fix additional checkpatch warnings in the iProc I2C driver by using
'BIT' marcro.
Reported-by: Wolfram Sang
Signed-off-by: Ray Jui
---
drivers/i2c/busses/i2c-bcm-iproc.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/i2c/busses/i2c-bcm-iproc.c
b/d
(BIT(S_FIFO_RX_FLUSH_SHIFT) | BIT(S_FIFO_TX_FLUSH_SHIFT));
> + iproc_i2c_wr_reg(iproc_i2c, S_FIFO_CTRL_OFFSET, tmp);
> +
> + /* clear all pending slave interrupts */
> + iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET, ISR_MASK_SLAVE);
> +
> + iproc_i2c->slave = NULL;
> +
> + enable_irq(iproc_i2c->irq);
> +
> return 0;
> }
>
>
Thanks again, Dhananjay! Looks good to me.
Acked-by: Ray Jui
On 8/8/2020 7:47 AM, Florian Fainelli wrote:
>
>
> On 8/7/2020 8:55 PM, Dhananjay Phadke wrote:
>> On 8/7/2020, Florian Fainelli wrote:
When i2c client unregisters, synchronize irq before setting
iproc_i2c->slave to NULL.
(1) disable_irq()
(2) Mask event enable bits in
Hi Rayagonda/Dhananjay,
On 8/5/2020 2:17 AM, Wolfram Sang wrote:
> On Mon, Jul 27, 2020 at 01:43:40PM -0700, Ray Jui wrote:
>>
>>
>> On 7/27/2020 1:26 PM, Wolfram Sang wrote:
>>> On Mon, Jul 27, 2020 at 08:13:46PM +0200, Wolfram Sang wrote:
>>>>
>
->hwirq) + target_cpu;
> + irq_data_update_effective_affinity(data, cpumask_of(target_cpu));
>
> - return IRQ_SET_MASK_OK;
> + return ret;
> }
>
> static void iproc_msi_irq_compose_msi_msg(struct irq_data *data,
>
Looks good with the Fixes tag added. Thanks.
Reviewed-by: Ray Jui
get_cpu;
> + irq_data_update_effective_affinity(data, cpumask_of(target_cpu));
>
> - return IRQ_SET_MASK_OK;
> + return ret;
> }
>
> static void iproc_msi_irq_compose_msi_msg(struct irq_data *data,
>
This change looks good to me. Thanks.
Reviewed-by: Ray Jui
On 7/30/2020 9:09 AM, Bjorn Helgaas wrote:
> [+cc Lorenzo, Rob]
>
> On Thu, Jul 30, 2020 at 03:37:46PM +1200, Mark Tomlinson wrote:
>> The pci_generic_config_write32() function will give warning messages
>> whenever writing less than 4 bytes at a time. As there is nothing we can
>> do about thi
On 7/27/2020 1:26 PM, Wolfram Sang wrote:
> On Mon, Jul 27, 2020 at 08:13:46PM +0200, Wolfram Sang wrote:
>>
>>> Can you confirm that even if we have irq pending at the i2c IP core
>>> level, as long as we execute Step 2. below (to disable/mask all slave
>>> interrupts), after 'enable_irq' is ca
Hi Wolfram,
On 7/25/2020 3:18 AM, Wolfram Sang wrote:
>
>> I think the following sequence needs to be implemented to make this
>> safe, i.e., after 'synchronize_irq', no further slave interrupt will be
>> fired.
>>
>> In 'bcm_iproc_i2c_unreg_slave':
>>
>> 1. Set an atomic variable 'unreg_slave' (
s: daa5abc41c80 ("pwm: Add support for Broadcom iProc PWM controller")
> Signed-off-by: Rayagonda Kokatanur
> Signed-off-by: Scott Branden
> Reviewed-by: Ray Jui
>
> ---
> Changes from v3: fixed typo in commit message: Reviewed-off-by.
> Hopefully everything clean no
On 7/22/2020 8:51 AM, Ray Jui wrote:
>
> On 7/22/2020 3:41 AM, Wolfram Sang wrote:
>>
>>>> + synchronize_irq(iproc_i2c->irq);
>>>
>>> If one takes a look at the I2C slave ISR routine, there are places where
>>> IRQ can be re-enabled in th
On 7/22/2020 3:41 AM, Wolfram Sang wrote:
>
>>> + synchronize_irq(iproc_i2c->irq);
>>
>> If one takes a look at the I2C slave ISR routine, there are places where
>> IRQ can be re-enabled in the ISR itself. What happens after we mask all
>> slave interrupt and when 'synchronize_irq' is called,
On 7/18/2020 4:39 PM, Dhananjay Phadke wrote:
> When i2c client unregisters, synchronize irq before setting
> iproc_i2c->slave to NULL.
>
> Unable to handle kernel NULL pointer dereference at virtual address
> 0318
>
> [ 371.020421] pc : bcm_iproc_i2c_isr+0x530/0x11f0
> [ 371.02
Hi Stephen/Michael,
Could you please help to review this patch?
Thanks,
Ray
On 6/12/2020 3:52 PM, Ray Jui wrote:
> From: Lori Hikichi
>
> Change from 'DIV_ROUND_UP' to 'DIV_ROUND_CLOSEST' when calculating the
> clock divisor in the iProc ASIU clock driver
t; Signed-off-by: Scott Branden
> Reviewed-off-by: Ray Jui
Typo. Should be 'Reviewed-by: Ray Jui ', :)
>
> ---
> Changes from v2: update commit message to remove <= condition
> as clk_get_rate only returns value >= 0
> ---
> drivers/pwm/pwm-bcm-i
d = 0;
> + state->duty_cycle = 0;
> + return;
> + }
> +
> value = readl(ip->base + IPROC_PWM_PRESCALE_OFFSET);
> prescale = value >> IPROC_PWM_PRESCALE_SHIFT(pwm->hwpwm);
> prescale &= IPROC_PWM_PRESCALE_MAX;
>
This patch looks good to me. Thanks!
Reviewed-by: Ray Jui
On 7/17/2020 10:07 AM, Scott Branden wrote:
> From: Rayagonda Kokatanur
>
> Handle clk_get_rate() returning <= 0 condition to avoid
> possible division by zero.
>
> Fixes: daa5abc41c80 ("pwm: Add support for Broadcom iProc PWM controller")
> Signed-off-by: Rayagonda Kokatanur
> Signed-off-by
int nsp_gpio_probe(struct platform_device *pdev)
> girq->num_parents = 0;
> girq->parents = NULL;
> girq->default_type = IRQ_TYPE_NONE;
> - girq->handler = handle_simple_irq;
> + girq->handler = handle_bad_irq;
> }
>
> ret = devm_gpiochip_add_data(dev, gc, chip);
>
This change looks good to me. Thanks!
Reviewed-by: Ray Jui
On 6/30/2020 9:44 PM, Florian Fainelli wrote:
>
>
> On 6/30/2020 9:37 PM, Mark Tomlinson wrote:
>> On Tue, 2020-06-30 at 20:14 -0700, Florian Fainelli wrote:
>>> Sorry, it looks like I made a mistake in my testing (or I was lucky),
and this patch doesn't fix the issue. What is happening i
Hi Mark,
On 6/30/2020 1:47 PM, Mark Tomlinson wrote:
> Rather than always using handle_simple_irq() as the gpio_irq_chip
> handler, set a more appropriate handler based on the IRQ trigger type
> requested. This is important for level triggered interrupts which need
> to be masked during handling.
Hi Mark,
On 6/30/2020 2:29 PM, Mark Tomlinson wrote:
> The GPIO specified in the DTS file references the pinctrl, which is
> specified after the GPIO. If the GPIO is initialised before pinctrl,
May I know which GPIO driver you are referring to on NSP? Both the iProc
GPIO driver and the NSP GPIO d
From: Lori Hikichi
Change from 'DIV_ROUND_UP' to 'DIV_ROUND_CLOSEST' when calculating the
clock divisor in the iProc ASIU clock driver to allow to get to the
closest clock rate.
Fixes: 5fe225c105fd ("clk: iproc: add initial common clock support")
Signed-off-by: Lo
On 9/24/19 11:57 AM, Wolfram Sang wrote:
In my opinion, it's probably better to continue to support master_xfer in
our driver (with obvious limitations), in order to allow i2ctransfer (or any
apps that use I2C RDWR) to continue to work.
What do you think?
Yes, don't break it for users. We
Hi Wolfram,
On 9/4/19 2:37 PM, Wolfram Sang wrote:
I think you are right that the controller does not seem to support
additional I2C features in addition to SMBUS.
However, my concern of switching to the smbus_xfer API is:
1) Some customers might have used I2C_RDWR based API from i2cdev. Cha
On 9/11/19 10:53 AM, Sheetal Tigadoli wrote:
Thanks for the review and comments.
On Tue, Sep 10, 2019 at 10:46 PM Greg Kroah-Hartman
wrote:
On Tue, Sep 10, 2019 at 08:47:04PM +0530, Sheetal Tigadoli wrote:
From: Vikas Gupta
This driver registers on TEE bus to interact with OP-TEE based
On 9/11/19 2:34 AM, Linus Walleij wrote:
On Thu, Aug 29, 2019 at 5:52 AM Srinath Mannam
wrote:
From: Li Jin
Fix drive strength for AON/CRMU controller; fix pull-up/down setting
for CCM/CDRU controller.
Fixes: 616043d58a89 ("pinctrl: Rename gpio driver from cygnus to iproc")
Signed-off-by
<&pinmux 135 77 6>,
<&pinmux 141 67 4>,
- <&pinmux 145 149 6>,
- <&pinmux 151 91 4>;
+ <&pinmux 145 149 6>;
};
i2c1: i2c@e {
Thanks for the fix. Looks good to me!
Reviewed-by: Ray Jui
S_NUM_IOMUX_REGS; i++) {
for (j = 0; j < CYGNUS_NUM_MUX_PER_REG; j++) {
log = &pinctrl->mux_log[i * CYGNUS_NUM_MUX_PER_REG
Change looks good to me. Thanks!
Reviewed-by: Ray Jui
On 8/31/19 2:49 AM, Wolfram Sang wrote:
Hi Ray,
With all the limitations in place, I wonder if it might be easier to
implement an smbus_xfer callback instead? What is left that makes this
controller more than SMBus and real I2C?
Right. But what is the implication of using smbus_xfer inste
On 8/30/19 5:56 AM, Wolfram Sang wrote:
Hi everyone,
+/*
+ * If 'process_call' is true, then this is a multi-msg transfer that requires
+ * a repeated start between the messages.
+ * More specifically, it must be a write (reg) followed by a read (data).
+ * The i2c quirks are set to enforce
v->base = devm_ioremap_resource(&pdev->dev, res);
+ priv->base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(priv->base)) {
dev_err(&pdev->dev, "failed to ioremap register\n");
return PTR_ERR(priv->base);
Looks good to me. Thanks.
Reviewed-by: Ray Jui
msgs
in a transfer is limited to two, and must be a write
followed by a read.
Signed-off-by: Lori Hikichi
Signed-off-by: Rayagonda Kokatanur
Signed-off-by: Icarus Chau
Signed-off-by: Ray Jui
Signed-off-by: Shivaraj Shetty
---
Note this patch has gone through internal review and testing on
ks = &bcm_iproc_i2c_quirks;
adap->dev.parent = &pdev->dev;
Looks good, thanks!
Reviewed-by: Ray Jui
gt;algo->reg_slave)
val |= I2C_FUNC_SLAVE;
Change looks good to me. Thanks.
Reviewed-by: Ray Jui
SHIFT) & M_RX_DATA_MASK;
> + (val >> M_RX_DATA_SHIFT) & M_RX_DATA_MASK;
> iproc_i2c->rx_bytes++;
> }
> }
>
Thanks for the fix. This fix looks good to me!
Reviewed-by: Ray Jui
ght, usually not needed if devm_ioremap_resource is used since it was
checked there. But in this case, I do think it needs to be checked. This
change looks good to me. Thanks.
> pinctrl->base1 = devm_ioremap_nocache(&pdev->dev, res->start,
> resource_size(res));
> if (!pinctrl->base1) {
>
Reviewed-by: Ray Jui
S_CMD_START_BUSY_SHIFT);
> + iproc_i2c_wr_reg(iproc_i2c, S_CMD_OFFSET, val);
> }
>
> /* Stop */
> if (status & BIT(IS_S_START_BUSY_SHIFT)) {
> i2c_slave_event(iproc_i2c->slave, I2C_SLAVE_STOP, &value);
> - iproc_i2c->xfer_dir = I2C_SLAVE_DIR_NONE;
> + /*
> + * Enable interrupt for TX FIFO becomes empty and
> + * less than PKT_LENGTH bytes were output on the SMBUS
> + */
> + val = iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);
> + val &= ~BIT(IE_S_TX_UNDERRUN_SHIFT);
> + iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, val);
> }
>
> /* clear interrupt status */
>
This was already reviewed internally. I just reviewed it again and it
looks fine to me. Thanks.
Reviewed-by: Ray Jui
he linux-i2c mailing list:
https://patchwork.ozlabs.org/project/linux-i2c/list/
> Best regards
> Rayagonda
>
> On Thu, May 9, 2019, 9:58 PM Ray Jui <mailto:ray@broadcom.com> wrote:
>
> Why is the email sent twice? What has changed?
>
> On 5/8/2019 9
Why is the email sent twice? What has changed?
On 5/8/2019 9:21 PM, Rayagonda Kokatanur wrote:
> Add multiple byte read-write support for slave mode.
>
> Signed-off-by: Rayagonda Kokatanur
> Signed-off-by: Srinath Mannam
> ---
> drivers/i2c/busses/i2c-bcm-iproc.c | 117
> +
regs = iproc_pcie_reg_paxb_v2;
> + pcie->iproc_cfg_read = true;
> pcie->has_apb_err_disable = true;
> if (pcie->need_ob_cfg) {
> pcie->ob_map = paxb_v2_ob_map;
>
Fix looks good to me. Thanks!
Reviewed-by: Ray Jui
On 4/17/2019 11:21 PM, Peter Rosin wrote:
> On 2019-04-18 01:48, Ray Jui wrote:
>>
>>
>> On 4/14/2019 11:56 PM, Peter Rosin wrote:
>>> On 2019-04-13 00:59, Peter Rosin wrote:
>>>> On 2019-04-03 23:05, Ray Jui wrote:
>>>>> Change the i
On 4/14/2019 11:56 PM, Peter Rosin wrote:
> On 2019-04-13 00:59, Peter Rosin wrote:
>> On 2019-04-03 23:05, Ray Jui wrote:
>>> Change the iProc I2C driver to use the 'BIT' macro from all '1 << XXX'
>>> bit operations to get rid of com
gister_driver() to register watchdog device
> - Replace shutdown function with call to watchdog_stop_on_reboot()
>
> Cc: Florian Fainelli
> Cc: Ray Jui
> Cc: Scott Branden
> Cc: bcm-kernel-feedback-l...@broadcom.com
> Signed-off-by: Guenter Roeck
> ---
> drivers/watchdog/bcm
On 3/25/2019 1:59 PM, Richard Laing wrote:
> It is possible for the i2c bus to become locked up preventing
> communication with devices on the bus. This can occur when
> another i2c device fails to be reset correctly. In this case
> the SDA line will be held low preventing further communication
Hi Lorenzo,
On 4/3/2019 4:31 AM, Lorenzo Pieralisi wrote:
> On Wed, Apr 03, 2019 at 08:41:44AM +0530, Srinath Mannam wrote:
>> Hi Lorenzo,
>>
>> Please see my reply below,
>>
>> On Tue, Apr 2, 2019 at 7:08 PM Lorenzo Pieralisi
>> wrote:
>>>
>>> On Tue, Apr 02, 2019 at 04:16:13PM +0530, Srinath Ma
Change the iProc I2C driver to use the 'BIT' macro from all '1 << XXX'
bit operations to get rid of compiler warning and improve readability of
the code
Signed-off-by: Ray Jui
---
drivers/i2c/busses/i2c-bcm-iproc.c | 6 +++---
1 file changed, 3 insertions(+), 3
Hi Wolfram,
On 4/3/2019 1:44 PM, Wolfram Sang wrote:
> On Tue, Apr 02, 2019 at 06:18:21PM -0700, Ray Jui wrote:
>> This patch series adds the following support to the iProc I2C driver:
>> - Increase maximum read transfer size to 255 bytes
>> - I2C slave mode
>> - Pol
From: Shreesha Rajashekar
Add slave mode support to the iProc I2C driver.
Signed-off-by: Rayagonda Kokatanur
Signed-off-by: Michael Cheng
Signed-off-by: Shreesha Rajashekar
Signed-off-by: Ray Jui
---
drivers/i2c/busses/Kconfig | 1 +
drivers/i2c/busses/i2c-bcm-iproc.c | 304
From: Rayagonda Kokatanur
Add polling support to the iProc I2C driver. Polling mode is
activated when the driver fails to obtain an interrupt ID from device
tree
Signed-off-by: Rayagonda Kokatanur
Signed-off-by: Ray Jui
---
drivers/i2c/busses/i2c-bcm-iproc.c | 298
Signed-off-by: Rayagonda Kokatanur
Signed-off-by: Ray Jui
Reviewed-by: Rob Herring
---
Documentation/devicetree/bindings/i2c/brcm,iproc-i2c.txt | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/i2c/brcm,iproc-i2c.txt
b/Documentation
From: Michael Cheng
Add support for more master error status including FIFO underrun and RX
FIFO full
Signed-off-by: Michael Cheng
Signed-off-by: Ray Jui
---
drivers/i2c/busses/i2c-bcm-iproc.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/i2c/busses/i2c-bcm-iproc.c
From: Rayagonda Kokatanur
Add NIC I2C support to the iProc I2C driver. Access to the NIC I2C base
registers requires going through the IDM wrapper to map into the NIC's
address space
Signed-off-by: Rayagonda Kokatanur
Signed-off-by: Ray Jui
---
drivers/i2c/busses/i2c-bcm-iproc.c
fall
back to polling mode
Signed-off-by: Ray Jui
Signed-off-by: Rayagonda Kokatanur
Reviewed-by: Rob Herring
---
.../devicetree/bindings/i2c/brcm,iproc-i2c.txt| 11 ---
1 file changed, 8 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/i2c/b
From: Rayagonda Kokatanur
Add NIC i2c device node.
Signed-off-by: Rayagonda Kokatanur
Signed-off-by: Ray Jui
---
.../boot/dts/broadcom/stingray/stingray.dtsi | 18 ++
1 file changed, 18 insertions(+)
diff --git a/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi
b/arch
preps the driver for support of indirect register access required
by certain SoCs with this iProc I2C block integrated
Signed-off-by: Rayagonda Kokatanur
Signed-off-by: Ray Jui
---
drivers/i2c/busses/i2c-bcm-iproc.c | 140 -
1 file changed, 77 insertions(+), 63
From: Shreesha Rajashekar
Add support to allow I2C master read transfer up to 255 bytes.
Signed-off-by: Shreesha Rajashekar
Signed-off-by: Rayagonda Kokatanur
Signed-off-by: Ray Jui
---
drivers/i2c/busses/i2c-bcm-iproc.c | 96 +++---
1 file changed, 74 insertions
ed to v5.0-rc3
Changes from v2:
- Address Ray's review comments.
Changes from v1:
- Rebased to Linux v5.0.0-rc2
Michael Cheng (1):
i2c: iproc: Add support for more master error status
Ray Jui (1):
dt-bindings: i2c: iproc: make 'interrupts' optional
Rayagonda Kokatanur (5
On 4/2/2019 10:57 AM, Ray Jui wrote:
>
>
> On 4/2/2019 3:27 AM, Wolfram Sang wrote:
[...]
>>> + iproc_i2c->type =
>>> + (enum bcm_iproc_i2c_type) of_device_get_match_data(&pdev->dev);
>>
>> No need to cast a void*.
>>
In fa
On 4/2/2019 3:27 AM, Wolfram Sang wrote:
>
>> +#define IDM_CTRL_DIRECT_OFFSET 0x00
>
> And this IDM thing is also never used outside of the I2C context? In
> other words, it also doesn't need a seperate DT node?
>
>
That is correct. Only in the I2C context in our use case.
>> +/*
to understand how it
> correlates to the code you are changing - I still have not figured it
> out myself.
>
> Please explain in detail to me how this works, forget DT changes I
> want to understand how HW works.
>
> Lorenzo
>
>> Example given in commit log is describing ranges
On 3/27/2019 3:27 PM, Wolfram Sang wrote:
> On Thu, Feb 14, 2019 at 09:57:17AM -0800, Ray Jui wrote:
>> This patch series adds the following support to the iProc I2C driver:
>> - Increase maximum read transfer size to 255 bytes
>> - I2C slave mode
>> - Polling mode
&
Hi Wolfram,
On 3/27/2019 3:24 PM, Wolfram Sang wrote:
>
>> Update iProc I2C binding document to add new compatible string
>> "brcm,iproc-nic-i2c". Optional property "brcm,ape-hsls-addr-mask" is
>> also added that allows configuration of the host view into the APE's
>> address for "brcm,iproc-nic-
On 3/27/2019 3:17 PM, Wolfram Sang wrote:
>
>> +if (!((readl(iproc_i2c->base +
>> +M_FIFO_CTRL_OFFSET) >>
>> +M_FIFO_RX_CNT_SHIFT) &
>> +M_FIFO_RX_CNT_MASK))
>
> Don't be too strict with the 80 char limit. I think the above is hardly
> readable..
Hi Wolfram/Rayagonda,
On 3/27/2019 3:14 PM, Wolfram Sang wrote:
>
>> +static void bcm_iproc_i2c_slave_init(
>> +struct bcm_iproc_i2c_dev *iproc_i2c, bool need_reset)
>> +{
>> +u32 val;
>> +
>> +if (need_reset) {
>> +/* put controller in reset */
>> +val = readl
Hi Richard,
On 3/21/2019 4:35 PM, Richard Laing wrote:
> It is possible for the i2c bus to become locked up preventing
> communication with devices on the bus, add the hooks required to
> allow the existing i2c recovery code to be used to clear the lock up.>
Can you be more specific on how the lo
xx.c:43:2-8: ERROR: missing of_node_put;
> acquired a node pointer with refcount incremented on line 35, but without a
> corresponding object release within this function.
>
> Signed-off-by: Wen Yang
> Reviewed-by: Florian Fainelli
> Cc: Florian Fainelli
> Cc: Ray Jui
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