> -Original Message-
> From: Hogander, Jouni
> Sent: Monday, May 27, 2024 12:52 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Manna, Animesh ; Kahola, Mika
> ; Hogander, Jouni
> Subject: [PATCH v3 05/20] drm/i915/psr: modify psr status debugfs to
> support eDP Panel Replay
>
> Some PS
Hi Maintainers,
There are some flaky tests reported for i915 driver testing in drm-ci
for the below boards.
*)
# Board Name: asus-C523NA-A20057-coral
# IGT Version: 1.28-g0df7b9b97
# Linux Version: 6.9.0-rc7
# Failure Rate: 50
kms_fb_coherency@memset-crc
*)
# Board Name: asus-C436FA-Flip-hatc
> -Original Message-
> From: Hogander, Jouni
> Sent: Monday, May 27, 2024 12:52 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Manna, Animesh ; Kahola, Mika
> ; Hogander, Jouni
> Subject: [PATCH v3 04/20] drm/i915/psr: Move printing PSR mode to own
> function
>
> intel_psr_status has g
> -Original Message-
> From: Hogander, Jouni
> Sent: Monday, May 27, 2024 12:52 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Manna, Animesh ; Kahola, Mika
> ; Hogander, Jouni
> Subject: [PATCH v3 03/20] drm/i915/psr: Move printing sink PSR support to
> own function
>
> intel_psr_stat
> -Original Message-
> From: Hogander, Jouni
> Sent: Monday, May 27, 2024 12:52 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Manna, Animesh ; Kahola, Mika
> ; Hogander, Jouni
> Subject: [PATCH v3 02/20] drm/panel replay: Add edp1.5 Panel Replay bits
> and register
>
> Add PANEL_REPLA
> -Original Message-
> From: Hogander, Jouni
> Sent: Monday, May 27, 2024 12:52 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Manna, Animesh ; Kahola, Mika
> ; Hogander, Jouni
> Subject: [PATCH v3 01/20] drm/i915/psr: Store pr_dpcd in intel_dp
>
> We need pr_dpcd contents for early tr
> -Original Message-
> From: Intel-gfx On Behalf Of Jani
> Nikula
> Sent: Monday, May 27, 2024 4:12 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Nikula, Jani ; ville.syrj...@linux.intel.com
> Subject: [PATCH 0/6] drm/i915/pps: pass dev_priv explicitly to PPS regs
>
> Continue avoidin
> -Original Message-
> From: Intel-gfx On Behalf Of Jani
> Nikula
> Sent: Monday, May 27, 2024 4:41 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Nikula, Jani
> Subject: [PATCH 00/11] drm/i915: pass dev_priv explicitly to DIP regs
>
> Continue removing implicit dev_priv references.
>
Hi Max,
Please provide the test results.
Hi Imre,
Meanwhile, my question here is the link status is not checked in MST mode
according to the current flow. The changes below
for MST are same as
https://patchwork.freedesktop.org/patch/591953/?series=132685&rev=6. Please
check it.
diff -
== Series Details ==
Series: series starting with [1/2] drm/i915: move rawclk init to
intel_cdclk_init() (rev2)
URL : https://patchwork.freedesktop.org/series/132168/
State : failure
== Summary ==
Error: patch
https://patchwork.freedesktop.org/api/1.0/series/132168/revisions/2/mbox/ not
app
On Mon, 27 May 2024, Jani Nikula wrote:
> On Mon, 08 Apr 2024, Ville Syrjälä wrote:
>> On Mon, Apr 08, 2024 at 08:28:27PM +0300, Ville Syrjälä wrote:
>>> On Mon, Apr 08, 2024 at 08:23:14PM +0300, Jani Nikula wrote:
>>> > The rawclk initialization is a bit out of place in
>>> > intel_device_info_r
On Mon, 08 Apr 2024, Ville Syrjälä wrote:
> On Mon, Apr 08, 2024 at 08:28:27PM +0300, Ville Syrjälä wrote:
>> On Mon, Apr 08, 2024 at 08:23:14PM +0300, Jani Nikula wrote:
>> > The rawclk initialization is a bit out of place in
>> > intel_device_info_runtime_init(). Move it to intel_cdclk_init(), w
Hello Vinschen,
Hope you are doing well. I am Chaitanya from the linux graphics team in Intel.
This mail is regarding a regression we are seeing in our CI runs[1] on
drm-tip[2] repository.
Since the version CI_DRM_14817[3], we are seeing the following regression
```
== Series Details ==
Series: drm/client: Detect when ACPI lid is closed during initialization
URL : https://patchwork.freedesktop.org/series/134092/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_14823 -> Patchwork_134092v1
On Mon, May 27, 2024 at 11:47:49AM +0100, Andi Shyti wrote:
> On Fri, May 24, 2024 at 10:07:44AM -0400, Rodrigo Vivi wrote:
> > On Fri, May 24, 2024 at 01:58:53AM +0200, Andi Shyti wrote:
> > > Following the guidelines it takes 3 seconds to perform an FLR
> > > reset. Let's give it a bit more slack
If the lid on a laptop is closed when eDP connectors are populated
then it remains enabled when the initial framebuffer configuration
is built.
When creating the initial framebuffer configuration detect the ACPI
lid status and if it's closed disable any eDP connectors.
Suggested-by: Alex Deucher
On Mon, 27 May 2024, Andy Shevchenko wrote:
> On Mon, May 27, 2024 at 12:43 PM Jani Nikula wrote:
>>
>> Use the mem_is_zero() helper where possible.
>
> ...
>
>> - if (memchr_inv(guid, 0, 16) == NULL) {
>> + if (mem_is_zero(guid, 16)) {
>> tmp64 = get_jiffies_64();
>>
== Series Details ==
Series: drm/i915: pass dev_priv explicitly to DIP regs
URL : https://patchwork.freedesktop.org/series/134074/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_14823 -> Patchwork_134074v1
Summary
---
On Mon, 27 May 2024, Andy Shevchenko wrote:
> On Mon, May 27, 2024 at 12:43 PM Jani Nikula wrote:
>>
>> Almost two thirds of the memchr_inv() usages check if the memory area is
>> all zeros, with no interest in where in the buffer the first non-zero
>> byte is located. Checking for !memchr_inv(s,
== Series Details ==
Series: drm/i915: pass dev_priv explicitly to DIP regs
URL : https://patchwork.freedesktop.org/series/134074/
State : warning
== Summary ==
Error: dim checkpatch failed
df89c96ca80c drm/i915: pass dev_priv explicitly to HSW_TVIDEO_DIP_CTL
-:79: WARNING:LONG_LINE: line leng
Hi all, the Intel graphics CI hits a lockdep issue with commit
86167183a17e ("igc: fix a log entry using uninitialized netdev") in
v6.10-rc1.
The commit moved igc_ptp_init() which initializes spinlocks after
igt_reset() which ends up using the adapter->ptp_tx_lock. Lockdep isn't
happy:
<3>[ 1
== Series Details ==
Series: drm/i915/pps: pass dev_priv explicitly to PPS regs
URL : https://patchwork.freedesktop.org/series/134073/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_14823 -> Patchwork_134073v1
Summary
--
== Series Details ==
Series: drm/i915/pps: pass dev_priv explicitly to PPS regs
URL : https://patchwork.freedesktop.org/series/134073/
State : warning
== Summary ==
Error: dim checkpatch failed
9a1686c5ec1d drm/i915: pass dev_priv explicitly to _MMIO_PPS
491e963cbb41 drm/i915: pass dev_priv ex
On Mon, May 27, 2024 at 12:43 PM Jani Nikula wrote:
>
> Almost two thirds of the memchr_inv() usages check if the memory area is
> all zeros, with no interest in where in the buffer the first non-zero
> byte is located. Checking for !memchr_inv(s, 0, n) is also not very
> intuitive or discoverable
On Mon, May 27, 2024 at 12:43 PM Jani Nikula wrote:
>
> Use the mem_is_zero() helper where possible.
...
> - if (memchr_inv(guid, 0, 16) == NULL) {
> + if (mem_is_zero(guid, 16)) {
> tmp64 = get_jiffies_64();
> memcpy(&guid[0], &tmp64, sizeof(u64));
>
On Mon, May 27, 2024 at 01:14:32PM +0800, gareth...@intel.com wrote:
Hi,
> A bad link in MST is not retrained. Please also consider MST.
> The issue ticket is
> https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10902.
>
> if (intel_dp->is_mst) {
> /*
>*
== Series Details ==
Series: Panel Replay eDP support (rev4)
URL : https://patchwork.freedesktop.org/series/133684/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_14821 -> Patchwork_133684v4
Summary
---
**SUCCESS**
== Series Details ==
Series: series starting with [1/2] string: add mem_is_zero() helper to check if
memory area is all zeros
URL : https://patchwork.freedesktop.org/series/134068/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_14821 -> Patchwork_134068v1
=
Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the ADL_TVIDEO_DIP_AS_SDP_DATA register macro.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_hdmi.c | 2 +-
drivers/gpu/drm/i915/i915_reg.h | 2 +-
2 files changed, 2 insertions(+), 2 de
Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the ICL_VIDEO_DIP_PPS_DATA register macro.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_hdmi.c | 2 +-
drivers/gpu/drm/i915/i915_reg.h | 2 +-
2 files changed, 2 insertions(+), 2 deleti
Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the ICL_VIDEO_DIP_PPS_ECC register macro.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/i915_reg.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/g
Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the GLK_TVIDEO_DIP_DRM_DATA register macro.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_hdmi.c | 2 +-
drivers/gpu/drm/i915/i915_reg.h | 2 +-
2 files changed, 2 insertions(+), 2 delet
Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the HSW_TVIDEO_DIP_VSC_DATA register macro.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_hdmi.c | 2 +-
drivers/gpu/drm/i915/i915_reg.h | 2 +-
2 files changed, 2 insertions(+), 2 delet
Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the HSW_TVIDEO_DIP_GMP_DATA register macro.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_hdmi.c | 2 +-
drivers/gpu/drm/i915/i915_reg.h | 2 +-
2 files changed, 2 insertions(+), 2 delet
Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the HSW_TVIDEO_DIP_VS_DATA register macro.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_hdmi.c | 2 +-
drivers/gpu/drm/i915/i915_reg.h | 2 +-
2 files changed, 2 insertions(+), 2 deleti
Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the HSW_TVIDEO_DIP_SPD_DATA register macro.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_hdmi.c | 2 +-
drivers/gpu/drm/i915/i915_reg.h | 2 +-
2 files changed, 2 insertions(+), 2 delet
Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the HSW_TVIDEO_DIP_GCP register macro.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_hdmi.c | 4 ++--
drivers/gpu/drm/i915/i915_reg.h | 2 +-
drivers/gpu/drm/i915/intel_gvt_mmio_tabl
Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the HSW_TVIDEO_DIP_AVI_DATA register macro.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_hdmi.c | 2 +-
drivers/gpu/drm/i915/i915_reg.h | 2 +-
2 files changed, 2 insertions(+), 2 delet
Continue removing implicit dev_priv references.
Jani Nikula (11):
drm/i915: pass dev_priv explicitly to HSW_TVIDEO_DIP_CTL
drm/i915: pass dev_priv explicitly to HSW_TVIDEO_DIP_GCP
drm/i915: pass dev_priv explicitly to HSW_TVIDEO_DIP_AVI_DATA
drm/i915: pass dev_priv explicitly to HSW_TVIDEO
Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the HSW_TVIDEO_DIP_CTL register macro.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_dp.c | 3 ++-
drivers/gpu/drm/i915/display/intel_hdmi.c | 7 ---
drivers/gpu/drm/i915/display/intel_l
== Series Details ==
Series: Link off between frames for edp (rev6)
URL : https://patchwork.freedesktop.org/series/130650/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: Link off between frames for edp (rev6)
URL : https://patchwork.freedesktop.org/series/130650/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_14821 -> Patchwork_130650v6
Summary
---
**SUCCE
== Series Details ==
Series: Link off between frames for edp (rev6)
URL : https://patchwork.freedesktop.org/series/130650/
State : warning
== Summary ==
Error: dim checkpatch failed
c37a38167321 drm/i915/alpm: Move alpm parameters from intel_psr
-:83: WARNING:LONG_LINE: line length of 104 exce
On Mon, 27 May 2024, Jani Nikula wrote:
> On Fri, 24 May 2024, Mitul Golani
> wrote:
>> diff --git a/drivers/gpu/drm/i915/intel_vrr_reg.h
>> b/drivers/gpu/drm/i915/intel_vrr_reg.h
>> new file mode 100644
>> index ..e1273b4e1b9b
>> --- /dev/null
>> +++ b/drivers/gpu/drm/i915/intel_vr
On Fri, 24 May 2024, Mitul Golani wrote:
> diff --git a/drivers/gpu/drm/i915/intel_vrr_reg.h
> b/drivers/gpu/drm/i915/intel_vrr_reg.h
> new file mode 100644
> index ..e1273b4e1b9b
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/intel_vrr_reg.h
We'll want to call this intel_vrr_regs.h, n
On Fri, May 24, 2024 at 10:07:44AM -0400, Rodrigo Vivi wrote:
> On Fri, May 24, 2024 at 01:58:53AM +0200, Andi Shyti wrote:
> > Following the guidelines it takes 3 seconds to perform an FLR
> > reset. Let's give it a bit more slack because this time can
> > change depending on the platform and on t
Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the PP_DIVISOR register macro.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_lvds.c | 4 ++--
drivers/gpu/drm/i915/display/intel_pps.c | 2 +-
drivers/gpu/drm/i915/display/intel_pps_regs.
Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the PP_OFF_DELAYS register macro.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_lvds.c | 4 ++--
drivers/gpu/drm/i915/display/intel_pps.c | 2 +-
drivers/gpu/drm/i915/display/intel_pps_re
Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the PP_ON_DELAYS register macro.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_lvds.c | 4 ++--
drivers/gpu/drm/i915/display/intel_pps.c | 10 +-
drivers/gpu/drm/i915/display/int
Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the PP_CONTROL register macro.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_dsi_vbt.c | 4 ++--
drivers/gpu/drm/i915/display/intel_lvds.c | 11 ++-
drivers/gpu/drm/i915/display/inte
Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the PP_STATUS register macro.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_display_power.c | 2 +-
drivers/gpu/drm/i915/display/intel_lvds.c | 6 +++---
drivers/gpu/drm/i915/display/inte
Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the _MMIO_PPS register macro.
While at it, use __to_intel_display() to allow passing in struct
intel_display at a later time.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_pps_regs.h | 16 +++
Continue avoiding the implicit dev_priv local variable.
Jani Nikula (6):
drm/i915: pass dev_priv explicitly to _MMIO_PPS
drm/i915: pass dev_priv explicitly to PP_STATUS
drm/i915: pass dev_priv explicitly to PP_CONTROL
drm/i915: pass dev_priv explicitly to PP_ON_DELAYS
drm/i915: pass dev_
Hi Angus,
On Fri, May 24, 2024 at 05:33:49PM +, Chen, Angus wrote:
> The WA should be extended to cover VDBOX engine. We found that
> 28-channels 1080p VP9 encoding may hit this issue.
>
> v3: update the WA number and explain the reason why
> this workaround is needed
> v2: add WA number
== Series Details ==
Series: Panel Replay eDP support (rev4)
URL : https://patchwork.freedesktop.org/series/133684/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_14821 -> Patchwork_133684v4
Summary
---
**FAILURE**
== Series Details ==
Series: Panel Replay eDP support (rev4)
URL : https://patchwork.freedesktop.org/series/133684/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: Panel Replay eDP support (rev4)
URL : https://patchwork.freedesktop.org/series/133684/
State : warning
== Summary ==
Error: dim checkpatch failed
68a6d15a8e6f drm/i915/psr: Store pr_dpcd in intel_dp
684085ce69fe drm/panel replay: Add edp1.5 Panel Replay bits and re
== Series Details ==
Series: Implement CMRR Support (rev9)
URL : https://patchwork.freedesktop.org/series/126443/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_14815 -> Patchwork_126443v9
Summary
---
**SUCCESS**
N
On Mon, 2024-05-27 at 13:56 +0530, Animesh Manna wrote:
> Link Off Between Active Frames (LOBF) allows an eDP link to be turned
> Off and On
> durning long VBLANK durations without enabling any of the PSR/PSR2/PR
> modes of operation.
>
> Bspec: 71477
>
> Note: Lobf need to be enabled adaptive sy
Use the mem_is_zero() helper where possible.
Conversion done using cocci:
| @@
| expression PTR;
| expression SIZE;
| @@
|
| <...
| (
| - memchr_inv(PTR, 0, SIZE) == NULL
| + mem_is_zero(PTR, SIZE)
| |
| - !memchr_inv(PTR, 0, SIZE)
| + mem_is_zero(PTR, SIZE)
| |
| - memchr_inv(PTR, 0, SIZE)
| +
Almost two thirds of the memchr_inv() usages check if the memory area is
all zeros, with no interest in where in the buffer the first non-zero
byte is located. Checking for !memchr_inv(s, 0, n) is also not very
intuitive or discoverable. Add an explicit mem_is_zero() helper for this
use case.
Sign
Link Off Between Active Frames, is a new feature for eDP
that allows the panel to go to lower power state after
transmission of data. This is a feature on top of ALPM, AS SDP.
Add compute config during atomic-check phase.
v1: RFC version.
v2: Add separate flag for auxless-alpm. [Jani]
v3:
- intel_
For validation purpose add debugfs for LOBF.
v1: Initial version.
v2: Add aux-wake/less info along with lobf status. [Jouni]
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_alpm.c | 49 +++
drivers/gpu/drm/i915/display/intel_alpm.h | 2 +
.../drm/i91
From: Jouni Högander
eDP1.5 adds some more bits into DP_RECEIVER_ALPM_CAP and
DP_RECEIVER_ALPM_CONFIG registers. Add definitions for these.
Signed-off-by: Jouni Högander
---
include/drm/display/drm_dp.h | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/include/drm/display
Set the Link Off Between Frames Enable bit in ALPM_CTL register.
Note: Lobf need to be enabled adaptive sync fixed refresh mode
where vmin = vmax = flipline, which will arise after cmmr feature
enablement. Will add enabling sequence in a separate patch.
v1: Initial version.
v2: Condition check mo
Move ALPM feature related code as it will be used for
non-psr panel also thorugh LOBF feature.
v1: Initial version.
v2: Correct ordering in makefile. [Jani]
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/display/intel_alpm.c | 295 ++
ALPM can be enabled for non psr panel and currenly aplm-params are
encapsulated under intel_psr struct, so moving out to intel_dp struct.
Signed-off-by: Animesh Manna
---
.../drm/i915/display/intel_display_types.h| 21 +
drivers/gpu/drm/i915/display/intel_psr.c | 44 +---
Link Off Between Active Frames (LOBF) allows an eDP link to be turned Off and On
durning long VBLANK durations without enabling any of the PSR/PSR2/PR modes of
operation.
Bspec: 71477
Note: Lobf need to be enabled adaptive sync fixed refresh mode
where vmin = vmax = flipline, which will arise af
== Series Details ==
Series: Panel Replay eDP support (rev3)
URL : https://patchwork.freedesktop.org/series/133684/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_14819 -> Patchwork_133684v3
Summary
---
**FAILURE**
== Series Details ==
Series: Panel Replay eDP support (rev3)
URL : https://patchwork.freedesktop.org/series/133684/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: Panel Replay eDP support (rev3)
URL : https://patchwork.freedesktop.org/series/133684/
State : warning
== Summary ==
Error: dim checkpatch failed
a6760c452878 drm/i915/psr: Store pr_dpcd in intel_dp
dda76ebd3328 drm/panel replay: Add edp1.5 Panel Replay bits and re
On Fri, 24 May 2024, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Fix up the SEL_FETCH_{SIZE,OFFSET} registers. A classic
> copy-paste fail on my part.
>
> I even had a small test to confirm that the old and new register
> offsets match, but somehow I must have screwed things up when
> running
On Fri, 2024-05-24 at 05:53 +, Manna, Animesh wrote:
>
>
> > -Original Message-
> > From: Hogander, Jouni
> > Sent: Tuesday, May 21, 2024 2:17 PM
> > To: intel-gfx@lists.freedesktop.org
> > Cc: Manna, Animesh ; Kahola, Mika
> > ; Hogander, Jouni
> > Subject: [PATCH v2 00/17] Panel R
eDP1.5 adds some more bits into DP_RECEIVER_ALPM_CAP and
DP_RECEIVER_ALPM_CONFIG registers. Add definitions for these.
Signed-off-by: Jouni Högander
---
include/drm/display/drm_dp.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/include/drm/display/drm_dp.h b/include/drm/display/drm_dp.h
eDP1.5 support ALPM with Panel Replay as well. We need to check ALPM
related things for Panel Replay as well.
Bspec: 68920
Signed-off-by: Jouni Högander
---
drivers/gpu/drm/i915/display/intel_psr.c | 45 +---
1 file changed, 24 insertions(+), 21 deletions(-)
diff --git a/dr
Move Early Transport validity check to be performed for Panel Replay as
well and use Early Transport for eDP Panel Replay always.
Signed-off-by: Jouni Högander
---
drivers/gpu/drm/i915/display/intel_psr.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i
Take into account that 128b/132b Panel Replay is not supported on eDP.
Bspec: 68920
Signed-off-by: Jouni Högander
---
drivers/gpu/drm/i915/display/intel_psr.c | 16 ++--
1 file changed, 14 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
b/driver
Add PANEL_REPLAY_CONFIGURATION_2 register and some missing Panel Replay
bits.
Signed-off-by: Jouni Högander
---
include/drm/display/drm_dp.h | 16 +---
1 file changed, 13 insertions(+), 3 deletions(-)
diff --git a/include/drm/display/drm_dp.h b/include/drm/display/drm_dp.h
index 906
Currently there is no way to disable Panel Replay without disabling
PSR. Add new debug bit to be used with i915_edp_psr_debug debugfs
interface.
v2: ensure that fastset is performed when the bit changes
Signed-off-by: Jouni Högander
---
drivers/gpu/drm/i915/display/intel_display_types.h | 1 +
Display version >= 20 support eDP 1.5. Inform Panel Replay source support
on eDP for display version >= 20.
Bspec: 68920
Signed-off-by: Jouni Högander
---
drivers/gpu/drm/i915/display/intel_psr.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/disp
There are couple of bits in PSR2_CTL which needs to be written in case of
eDP Panel Replay
Bspec: 68920
Signed-off-by: Jouni Högander
---
drivers/gpu/drm/i915/display/intel_psr.c | 12
1 file changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
b/driver
Take into account in Panel Replay compute config that HW will not allow PR
on eDP when HDCP enabled.
Signed-off-by: Jouni Högander
---
drivers/gpu/drm/i915/display/intel_psr.c | 18 --
1 file changed, 16 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/in
This reverts commit f3c2031db7dfdf470a2d9bf3bd1efa6edfa72d8d.
We want to notice possible issues faced with PSR2 Region Early Transport as
early as possible -> let's revert patch disabling Region Early Transport by
default. Also eDP 1.5 Panel Replay requires Early Transport.
Signed-off-by: Jouni H
Early Transport is possible and in our HW mandatory on eDP Panel
Replay. Add parameter to intel_psr2_config_et_valid to differentiate
validity check for Panel Replay.
Signed-off-by: Jouni Högander
---
drivers/gpu/drm/i915/display/intel_psr.c | 21 -
1 file changed, 12 inserti
We want to have sink Early Transport capability and usage in our psr
debugfs status interface.
v3: remove extra space from "PSR mode: disabled"
v2: printout "Selective Update enabled (Early Transport)" instead of
"Selective Update Early Transport enabled"
Signed-off-by: Jouni Högander
---
eDP1.5 allows Panel Replay on eDP as well. Take this into account when
enabling sink PSR/Panel Replay. Write also PANEL_REPLAY_CONFIG2 register
accordingly.
Signed-off-by: Jouni Högander
---
drivers/gpu/drm/i915/display/intel_psr.c | 63 +---
1 file changed, 46 insertions(+),
Our HW doesn't support panel replay without Early Transport on eDP.
Bspec: 68920
Signed-off-by: Jouni Högander
---
drivers/gpu/drm/i915/display/intel_psr.c | 19 +--
1 file changed, 13 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
b/driver
We are about to add more checks for Panel Replay. Due to that it makes
sense to add now Panel Replay compute config helper.
Signed-off-by: Jouni Högander
---
drivers/gpu/drm/i915/display/intel_psr.c | 11 +--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i
intel_psr_status has grown and is about to grow even. Let's split it a bit
and move printing sink psr support to an own function.
Signed-off-by: Jouni Högander
---
drivers/gpu/drm/i915/display/intel_psr.c | 22 +++---
1 file changed, 15 insertions(+), 7 deletions(-)
diff --git a
intel_psr_status has grown and is about to grow even. Let's split it a bit
and move printing PSR mode to an own function.
v2: s/intel_psr_psr_mode/intel_psr_print_mode/
Signed-off-by: Jouni Högander
---
drivers/gpu/drm/i915/display/intel_psr.c | 26
1 file changed, 17 i
Some PSR2_CTL bits are applicable for eDP panel replay as well.
Dump this register for eDP Panel Replay as well.
Bspec: 68920
Signed-off-by: Jouni Högander
---
drivers/gpu/drm/i915/display/intel_psr.c | 11 ++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/dr
Our HW doesn't support Panel Replay without AUX_LESS ALPM on eDP. Check
panel support for this and prevent eDP panel replay if it doesn't exits.
Bspec: 68920
Signed-off-by: Jouni Högander
---
drivers/gpu/drm/i915/display/intel_psr.c | 32
1 file changed, 16 insertions(+
We need pr_dpcd contents for early transport validity check on eDP Panel
Replay and in debugfs interface to dump out panel early transport
capability. Also remove unnecessarily printing out "Panel replay is not
supported by panel"
v2: commit message modified
Signed-off-by: Jouni Högander
---
..
This patch set is implementing eDP1.5 Panel Replay for Intel hw. Also
Region Early Transport information is added into debugfs interface
and patch to disable Region Early Transport by default is reverted as
it is needed by eDP Panel Replay.
v3:
- commit message modifications
- s/intel_psr_psr_
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