eDP1.5 allows Panel Replay on eDP as well. Take this into account when
enabling sink PSR/Panel Replay. Write also PANEL_REPLAY_CONFIG2 register
accordingly.
Signed-off-by: Jouni Högander <jouni.hogan...@intel.com>
---
drivers/gpu/drm/i915/display/intel_psr.c | 63 +++++++++++++++++-------
1 file changed, 46 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
b/drivers/gpu/drm/i915/display/intel_psr.c
index fcf73a5cbfc2..16e06312a8be 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -692,6 +692,23 @@ static unsigned int
intel_psr_get_enable_sink_offset(struct intel_dp *intel_dp)
PANEL_REPLAY_CONFIG : DP_PSR_EN_CFG;
}
+static void intel_psr_enable_sink_alpm(struct intel_dp *intel_dp,
+ const struct intel_crtc_state
*crtc_state)
+{
+ u32 val;
+
+ if (!crtc_state->has_sel_update && (!crtc_state->has_panel_replay ||
+ !intel_dp_is_edp(intel_dp)))
+ return;
+
+ val = DP_ALPM_ENABLE | DP_ALPM_LOCK_ERROR_IRQ_HPD_ENABLE;
+
+ if (crtc_state->has_panel_replay)
+ val |= DP_ALPM_MODE_AUX_LESS;
+
+ drm_dp_dpcd_writeb(&intel_dp->aux, DP_RECEIVER_ALPM_CONFIG, val);
+}
+
/*
* Note: Most of the bits are same in PANEL_REPLAY_CONFIG and DP_PSR_EN_CFG. We
* are relying on PSR definitions on these "common" bits.
@@ -700,43 +717,55 @@ void intel_psr_enable_sink(struct intel_dp *intel_dp,
const struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
- u8 dpcd_val = DP_PSR_ENABLE;
+ u8 enable_val = DP_PSR_ENABLE;
+ u8 panel_replay_config2 = 0;
+
+ intel_psr_enable_sink_alpm(intel_dp, crtc_state);
if (crtc_state->has_sel_update) {
- /* Enable ALPM at sink for psr2 */
- if (!crtc_state->has_panel_replay) {
- drm_dp_dpcd_writeb(&intel_dp->aux,
- DP_RECEIVER_ALPM_CONFIG,
- DP_ALPM_ENABLE |
- DP_ALPM_LOCK_ERROR_IRQ_HPD_ENABLE);
+ /* PSR2 and Panel Replay SU on eDP */
+ if (intel_dp_is_edp(intel_dp)) {
+ if (crtc_state->req_psr2_sdp_prior_scanline) {
+ if (crtc_state->has_panel_replay)
+ panel_replay_config2 |=
+
DP_PANEL_REPLAY_SU_REGION_SCANLINE_CAPTURE;
+ else
+ enable_val |=
DP_PSR_SU_REGION_SCANLINE_CAPTURE;
+ }
if (psr2_su_region_et_valid(intel_dp,
intel_dp->psr.panel_replay_enabled))
- dpcd_val |= DP_PSR_ENABLE_SU_REGION_ET;
+ enable_val |= DP_PSR_ENABLE_SU_REGION_ET;
}
- dpcd_val |= DP_PSR_ENABLE_PSR2 | DP_PSR_IRQ_HPD_WITH_CRC_ERRORS;
+ enable_val |= DP_PSR_ENABLE_PSR2 |
DP_PSR_IRQ_HPD_WITH_CRC_ERRORS;
} else {
+ /* PSR2 and Panel Replay Full Frame Update */
if (intel_dp->psr.link_standby)
- dpcd_val |= DP_PSR_MAIN_LINK_ACTIVE;
+ enable_val |= DP_PSR_MAIN_LINK_ACTIVE;
if (!crtc_state->has_panel_replay && DISPLAY_VER(dev_priv) >= 8)
- dpcd_val |= DP_PSR_CRC_VERIFICATION;
+ enable_val |= DP_PSR_CRC_VERIFICATION;
}
- if (crtc_state->has_panel_replay)
- dpcd_val |= DP_PANEL_REPLAY_UNRECOVERABLE_ERROR_EN |
+ if (crtc_state->has_panel_replay) {
+ enable_val |= DP_PANEL_REPLAY_UNRECOVERABLE_ERROR_EN |
DP_PANEL_REPLAY_RFB_STORAGE_ERROR_EN;
- if (crtc_state->req_psr2_sdp_prior_scanline)
- dpcd_val |= DP_PSR_SU_REGION_SCANLINE_CAPTURE;
+ if (intel_dp_is_edp(intel_dp))
+ enable_val |= DP_PANEL_REPLAY_VSC_SDP_CRC_EN;
+ }
if (intel_dp->psr.entry_setup_frames > 0)
- dpcd_val |= DP_PSR_FRAME_CAPTURE;
+ enable_val |= DP_PSR_FRAME_CAPTURE;
drm_dp_dpcd_writeb(&intel_dp->aux,
intel_psr_get_enable_sink_offset(intel_dp),
- dpcd_val);
+ enable_val);
+
+ if (crtc_state->has_panel_replay && intel_dp_is_edp(intel_dp))
+ drm_dp_dpcd_writeb(&intel_dp->aux, PANEL_REPLAY_CONFIG2,
+ panel_replay_config2);
if (intel_dp_is_edp(intel_dp))
drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
DP_SET_POWER_D0);
--
2.34.1
