> -----Original Message-----
> From: Hogander, Jouni <jouni.hogan...@intel.com>
> Sent: Monday, May 27, 2024 12:52 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Manna, Animesh <animesh.ma...@intel.com>; Kahola, Mika
> <mika.kah...@intel.com>; Hogander, Jouni <jouni.hogan...@intel.com>
> Subject: [PATCH v3 05/20] drm/i915/psr: modify psr status debugfs to
> support eDP Panel Replay
>
> Some PSR2_CTL bits are applicable for eDP panel replay as well.
> Dump this register for eDP Panel Replay as well.
>
> Bspec: 68920
>
> Signed-off-by: Jouni Högander <jouni.hogan...@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_psr.c | 11 ++++++++++-
> 1 file changed, 10 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index dfd45f6d7edd..19f8ac12f995 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -3628,7 +3628,7 @@ static int intel_psr_status(struct seq_file *m, struct
> intel_dp *intel_dp)
> struct intel_psr *psr = &intel_dp->psr;
> intel_wakeref_t wakeref;
> bool enabled;
> - u32 val;
> + u32 val, psr2_ctl;
>
> intel_psr_sink_capability(intel_dp, m);
>
> @@ -3649,6 +3649,12 @@ static int intel_psr_status(struct seq_file *m,
> struct intel_dp *intel_dp)
>
> if (psr->panel_replay_enabled) {
> val = intel_de_read(dev_priv,
> TRANS_DP2_CTL(cpu_transcoder));
> +
> + if (intel_dp_is_edp(intel_dp))
> + psr2_ctl = intel_de_read(dev_priv,
> + EDP_PSR2_CTL(dev_priv,
> + cpu_transcoder));
> +
> enabled = val & TRANS_DP2_PANEL_REPLAY_ENABLE;
> } else if (psr->sel_update_enabled) {
> val = intel_de_read(dev_priv,
> @@ -3660,6 +3666,9 @@ static int intel_psr_status(struct seq_file *m, struct
> intel_dp *intel_dp)
> }
> seq_printf(m, "Source PSR/PanelReplay ctl: %s [0x%08x]\n",
> str_enabled_disabled(enabled), val);
> + if (psr->panel_replay_enabled && intel_dp_is_edp(intel_dp))
> + seq_printf(m, "PSR2_CTL: 0x%08x\n",
> + psr2_ctl);
Just a nitpick: A code comment describing the bitfield of PSR2_CTL register
used for validation will be helpful from code readability pov. The same maybe
applicable for psr-ctl as well.
With or without above fix.
Reviewed-by: Animesh Manna <animesh.ma...@intel.com>
Regards,
Animesh
> psr_source_status(intel_dp, m);
> seq_printf(m, "Busy frontbuffer bits: 0x%08x\n",
> psr->busy_frontbuffer_bits);
> --
> 2.34.1
