[PATCH 02/11] drm/i915: pass dev_priv explicitly to HSW_TVIDEO_DIP_GCP

[Jani Nikula]

Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the HSW_TVIDEO_DIP_GCP register macro.

Signed-off-by: Jani Nikula <jani.nik...@intel.com>
---
 drivers/gpu/drm/i915/display/intel_hdmi.c   | 4 ++--
 drivers/gpu/drm/i915/i915_reg.h             | 2 +-
 drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 6 +++---
 3 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c 
b/drivers/gpu/drm/i915/display/intel_hdmi.c
index 4557acdd8b3c..18a95d7f2771 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -986,7 +986,7 @@ static bool intel_hdmi_set_gcp_infoframe(struct 
intel_encoder *encoder,
                return false;
 
        if (HAS_DDI(dev_priv))
-               reg = HSW_TVIDEO_DIP_GCP(crtc_state->cpu_transcoder);
+               reg = HSW_TVIDEO_DIP_GCP(dev_priv, crtc_state->cpu_transcoder);
        else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
                reg = VLV_TVIDEO_DIP_GCP(crtc->pipe);
        else if (HAS_PCH_SPLIT(dev_priv))
@@ -1011,7 +1011,7 @@ void intel_hdmi_read_gcp_infoframe(struct intel_encoder 
*encoder,
                return;
 
        if (HAS_DDI(dev_priv))
-               reg = HSW_TVIDEO_DIP_GCP(crtc_state->cpu_transcoder);
+               reg = HSW_TVIDEO_DIP_GCP(dev_priv, crtc_state->cpu_transcoder);
        else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
                reg = VLV_TVIDEO_DIP_GCP(crtc->pipe);
        else if (HAS_PCH_SPLIT(dev_priv))
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0331fdd61f33..ff520171ac16 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3476,7 +3476,7 @@
 #define _ICL_VIDEO_DIP_PPS_ECC_B       0x613D4
 
 #define HSW_TVIDEO_DIP_CTL(dev_priv, trans)            _MMIO_TRANS2(dev_priv, 
trans, _HSW_VIDEO_DIP_CTL_A)
-#define HSW_TVIDEO_DIP_GCP(trans)              _MMIO_TRANS2(dev_priv, trans, 
_HSW_VIDEO_DIP_GCP_A)
+#define HSW_TVIDEO_DIP_GCP(dev_priv, trans)            _MMIO_TRANS2(dev_priv, 
trans, _HSW_VIDEO_DIP_GCP_A)
 #define HSW_TVIDEO_DIP_AVI_DATA(trans, i)      _MMIO_TRANS2(dev_priv, trans, 
_HSW_VIDEO_DIP_AVI_DATA_A + (i) * 4)
 #define HSW_TVIDEO_DIP_VS_DATA(trans, i)       _MMIO_TRANS2(dev_priv, trans, 
_HSW_VIDEO_DIP_VS_DATA_A + (i) * 4)
 #define HSW_TVIDEO_DIP_SPD_DATA(trans, i)      _MMIO_TRANS2(dev_priv, trans, 
_HSW_VIDEO_DIP_SPD_DATA_A + (i) * 4)
diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c 
b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
index 027cd273d775..349578cc0fc8 100644
--- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
+++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
@@ -1235,9 +1235,9 @@ static int iterate_bxt_mmio(struct 
intel_gvt_mmio_table_iter *iter)
        MMIO_D(BXT_DSI_PLL_ENABLE);
        MMIO_D(GEN9_CLKGATE_DIS_0);
        MMIO_D(GEN9_CLKGATE_DIS_4);
-       MMIO_D(HSW_TVIDEO_DIP_GCP(TRANSCODER_A));
-       MMIO_D(HSW_TVIDEO_DIP_GCP(TRANSCODER_B));
-       MMIO_D(HSW_TVIDEO_DIP_GCP(TRANSCODER_C));
+       MMIO_D(HSW_TVIDEO_DIP_GCP(dev_priv, TRANSCODER_A));
+       MMIO_D(HSW_TVIDEO_DIP_GCP(dev_priv, TRANSCODER_B));
+       MMIO_D(HSW_TVIDEO_DIP_GCP(dev_priv, TRANSCODER_C));
        MMIO_D(RC6_CTX_BASE);
        MMIO_D(GEN8_PUSHBUS_CONTROL);
        MMIO_D(GEN8_PUSHBUS_ENABLE);
-- 
2.39.2