Currently MI_BATCH_BUFFER_END is missed in null state batch buffer.
This fix is trying to append the missed instruction at the end of
null state batch buffer gem bo after it was initialized and filled
with null state commands.
This issue was exposed under full GPU virtualization(Intel GVT-g) envir
This patch introduces exit/activate functions for PSR
on VLV+. Since on VLV+ HW cannot track frame updates and force PSR
exit let's use fully SW tracking available.
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/intel_dp.c | 94 +++--
1 file changed, 81
Add debugfs support for Valleyview and Cherryview considering that
we have PSR per pipe and we don't have any kind of
performance counter as we have on other platforms that support PSR.
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/i915_debugfs.c | 34 +-
Just a bit of organization and comment.
In the past we had two functions psr_exit
and psr_do_exit. psr_exit is the propper name now.
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/intel_dp.c | 13 ++---
1 file changed, 10 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm
VLV PSR support PSR per pipe, including the status. So we have to check
if it is enabled per pipe on status.
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/intel_dp.c | 23 +--
1 file changed, 21 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.
Altought VLV/CHV PSR supports per pipe PSR on VLV it isn't available
on pipe C.
Cherryview supports on all 3 pipes.
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/intel_dp.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/i
Since active function on VLV immediately activate PSR let's give more
time for idleness.
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/intel_dp.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
i
This patch is the last in series of VLV/CHV PSR,
that finnaly enable psr by adding it to HAS_PSR
and calling the propper enable and disable
functions on the right places.
Although it is still disabled by default.
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/i915_drv.h | 3 ++-
drivers/g
Let's clear a bit the difference between enable_source and activate
and explain it on comments and docs.
After that we will be able to introduce inactivate/activate VLV+
functions
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/intel_dp.c | 34 +++---
1 file cha
This series introduce support for PSR on Valleyview and Cherryview plataforms.
On these platforms the PSR implementation on Hardware was completelly different
from what we had on
HSW/BDW so I put more comment and function headers to explain it better to help
reviewer.
I had giving up on PSR Bay
Baytrail (Valleyview) and Braswell (Cherryview) uses a complete different
implementation of PSR that we currently have supported for
Haswell and Broadwell. So let's start by adding registers definitions.
I usually don't like commit that adds just registers without using,
but after I put all in one
The biggest difference from HSW/BDW PSR here is that VLV enable_source
function enables PSR but let it in Inactive state. So it might be called
on early stage along with setup and enable_sink ones.
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/intel_dp.c | 161
commit c675949ec58ca50d5a3ae3c757892f1560f6e896
drm/i915: do not setup backlight if not available according to VBT
prevents backlight setup on Macbook 2,1. Apply quirk to ignore the VBT
check so backlight is set up properly.
Signed-off-by: Jens Stein Jørgensen
---
drivers/gpu/drm/i915/intel
+WaForceEnableNonCoherent:chv
+WaHdcDisableFetchWhenMasked:chv
For: VIZ-4090
Signed-off-by: Arun Siluvery
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_ringbuffer.c | 10 ++
2 files changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b
WaDisablePartialInstShootdown:chv and
WaDisableThreadStallDopClockGating:chv are related to the same
register so combine them.
Signed-off-by: Arun Siluvery
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i
-WaDisableDopClockGating:chv
-WaDisableSamplerPowerBypass:chv
-WaDisableGunitClockGating:chv
-WaDisableFfDopClockGating:chv
-WaDisableDopClockGating:chv
v2: Remove pre-production WA instead of restricting them
based on revision id (Ville)
For: VIZ-4090
Signed-off-by: Arun Siluvery
---
drivers/g
The patches in this series adds two new workarounds for CHV and
removes pre-production ones.
Based on review comments from Ville, add/remove patches are split-up
which helps in reverting them if required.
The initial patch can be found at,
https://patchwork.kernel.org/patch/5178021/
Arun Siluver
On Tue, Oct 28, 2014 at 10:57:38AM -0700, Jesse Barnes wrote:
> On Thu, 16 Oct 2014 20:52:33 +0300
> ville.syrj...@linux.intel.com wrote:
>
> > From: Ville Syrjälä
> >
> > In case the cmnlane power well is down but cmnreset isn't asserted we
> > would currently skip the off+on toggle for the pow
On Mon, 27 Oct 2014 16:07:32 +0200
ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> It seems that the pipe-a power well has replaced the disp2d power well
> on chv. At least that's the case with the current punit firmware. So
> enable the pipe-a power and expand its domains to cove
On Thu, 16 Oct 2014 20:52:33 +0300
ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> In case the cmnlane power well is down but cmnreset isn't asserted we
> would currently skip the off+on toggle for the power well. That could
> leave cmnreset deasserted while cmnlane is powered dow
On 28/10/2014 17:06, Ville Syrjälä wrote:
On Tue, Oct 28, 2014 at 03:48:24PM +, Arun Siluvery wrote:
+WaForceEnableNonCoherent:chv
+WaHdcDisableFetchWhenMasked:chv
-WaDisableDopClockGating:chv
-WaDisableSamplerPowerBypass:chv
-WaDisableGunitClockGating:chv
-WaDisableFfDopClockGating:chv
-WaD
From: Michel Thierry
Following the legacy ring submission example, update the
ring->init_context() hook to support the execlist submission mode.
v2: update to use the new workaround macros and cleanup unused code.
This takes care of both bdw and chv workarounds.
v2.1: Add missing call to init_c
On Tue, Oct 28, 2014 at 03:48:24PM +, Arun Siluvery wrote:
> +WaForceEnableNonCoherent:chv
> +WaHdcDisableFetchWhenMasked:chv
> -WaDisableDopClockGating:chv
> -WaDisableSamplerPowerBypass:chv
> -WaDisableGunitClockGating:chv
> -WaDisableFfDopClockGating:chv
> -WaDisableDopClockGating:chv
>
> W
On Tue, Oct 21, 2014 at 04:02:03PM +0300, Ander Conselvan de Oliveira wrote:
> The new struct will be used in a follow up patch to allow a current and
> a staged config to exist for the same shared DPLL.
>
> Signed-off-by: Ander Conselvan de Oliveira
>
This needs to be rebased on top of Ville's
Hi,
On 17 October 2014 01:36, Jiang, Fei wrote:
> Thanks for Emil's suggestion. You are right, we need make sure structure
> size aligned on 8 bytes, which is important for 32bit-64bit compatible case.
While you're at it, please don't use enum as a type inside ioctls, since
the size can vary b
From: Michel Thierry
Following the legacy ring submission example, update the
ring->init_context() hook to support the execlist submission mode.
v2: update to use the new workaround macros and cleanup unused code.
This takes care of both bdw and chv workarounds.
Issue: VIZ-4092
Issue: GMIN-3475
Because the plane registers are different in Skylake we need to adapt
the MMIO code as well.
v2: Don't introduce yet another vfunc when the direction is do
consolidate the plane updates to use the same code path (Daniel)
v3:
- Use enum pipe instead of int (Ville)
- Also update PLANE_STRIDE wh
Reviewed-by: Rodrigo Vivi
On Tue, Oct 28, 2014 at 4:53 AM, Jani Nikula wrote:
> Keep the driver modifications to ELD together. This also sets the
> Conn_Type for G4X DP which wasn't done before.
>
> Clean up the debugs while at it; this is all obvious from the connector
> name.
>
> v3: add missi
On Tue, Oct 28, 2014 at 06:39:27PM +0530, akash.g...@intel.com wrote:
> From: Akash Goel
>
> A new libdrm interface 'drm_intel_gem_bo_map_wc' is provided by this
> patch. Through this interface Gfx clients can create write combining
> virtual mappings of the Gem object. It will provide the same f
On 19/10/2014 15:15, Daniel Vetter wrote:
On Fri, Oct 10, 2014 at 12:41:12PM +0100, john.c.harri...@intel.com wrote:
From: John Harrison
For: VIZ-4377
Signed-off-by: john.c.harri...@intel.com
I think this should be squashed (well, split first) into the relevant
earlier patches. Generally I mu
+WaForceEnableNonCoherent:chv
+WaHdcDisableFetchWhenMasked:chv
-WaDisableDopClockGating:chv
-WaDisableSamplerPowerBypass:chv
-WaDisableGunitClockGating:chv
-WaDisableFfDopClockGating:chv
-WaDisableDopClockGating:chv
WaDisablePartialInstShootdown:chv and
WaDisableThreadStallDopClockGating:chv are r
On Tue, 2014-10-28 at 16:15 +0200, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> The pps timestamp initialization was accidentally lost on vlv/chv in
>
> commit a4a5d2f8a96e09844a91469e889f15bd5e927399
> Author: Ville Syrjälä
> Date: Thu Sep 4 14:54:20 2014 +0300
>
>
On 19/10/2014 15:14, Daniel Vetter wrote:
On Tue, Oct 07, 2014 at 05:47:29PM +0100, john.c.harri...@intel.com wrote:
From: John Harrison
For: VIZ-4377
Signed-off-by: john.c.harri...@intel.com
Why? If it's just for performance I think we should do this as part of the
switch to struct fence, wh
On Mon, 27 Oct 2014, Rodrigo Vivi wrote:
> On Mon, Oct 27, 2014 at 7:26 AM, Jani Nikula wrote:
>> There's some serious confusion regarding ELD valid bit that gets set and
>> cleared back and forth etc. Rewrite it all based on the documented audio
>> codec enable/disable sequences.
>
> Could you p
Signed-off-by: Thomas Wood
---
docs/reference/intel-gpu-tools/Makefile.am | 20 ++-
.../intel-gpu-tools/igt_test_programs.xml.header | 65 ++
.../intel-gpu-tools/intel-gpu-tools-docs.xml | 1 +
3 files changed, 84 insertions(+), 2 deletions(-)
create mode
Signed-off-by: Thomas Wood
---
lib/igt_core.c | 19 ---
lib/igt_core.h | 3 +++
2 files changed, 19 insertions(+), 3 deletions(-)
diff --git a/lib/igt_core.c b/lib/igt_core.c
index e3d5fb0..3861121 100644
--- a/lib/igt_core.c
+++ b/lib/igt_core.c
@@ -223,6 +223,7 @@ bool test_ch
Signed-off-by: Thomas Wood
---
tests/core_getclient.c | 5 ++---
tests/core_getstats.c | 3 +++
tests/core_getversion.c | 6 +++---
tests/kms_3d.c | 2 ++
tests/kms_cursor_crc.c | 8
tests/kms_fbc_crc.c | 5 +
tests/kms_fence_pin_leak.c
Hi,
I have had some problems with crashes involving suspend-to-disk after
updating to v3.16.
Below is a log with 3.16.6 from a failed suspend attempt after which I
get a NULL deref in ext4 code.
A couple of weeks ago I got something similar, with backtraces from
ext4 (ext4_alloc_inode) and NUL
On Tue, Sep 23, 2014 at 04:10:51PM +0100, Damien Lespiau wrote:
> From: Pradeep Bhat
>
> This patch defines the structures needed for computation of
> watermarks of pipes and planes for SKL.
>
> v2: Incorporated Damien's review comments and removed unused fields
> in structs for future featu
On Tue, Oct 28, 2014 at 03:03:53PM +, Thomas Wood wrote:
> +extern const char* __igt_test_description __attribute__((weak));
> +#define IGT_TEST_DESCRIPTION(a) const char* __igt_test_description = a;
It's usual to omit the ';' here to have the macro invokation always
finish with a ';' (your ne
On 19/10/2014 15:12, Daniel Vetter wrote:
On Mon, Oct 06, 2014 at 03:15:25PM +0100, john.c.harri...@intel.com wrote:
From: John Harrison
For: VIZ-4377
Signed-off-by: john.c.harri...@intel.com
I think this should be split up into the different parts:
- s/obj->ring/obj->last_read_req->ring/ fo
On Tue, 28 Oct 2014, Johan Hovold wrote:
> Hi,
>
> I have had some problems with crashes involving suspend-to-disk after
> updating to v3.16.
>
> Below is a log with 3.16.6 from a failed suspend attempt after which I
> get a NULL deref in ext4 code.
>
> A couple of weeks ago I got something simil
Ensure that other components are built before generating the
documentation.
Signed-off-by: Thomas Wood
---
Makefile.am | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Makefile.am b/Makefile.am
index 1dacb17..0c799d2 100644
--- a/Makefile.am
+++ b/Makefile.am
@@ -21,7 +21,7 @@
On Tue, 28 Oct 2014, Ville Syrjälä wrote:
> On Tue, Oct 28, 2014 at 01:32:01PM +, Siluvery, Arun wrote:
>> On 28/10/2014 12:23, Ville Syrjälä wrote:
>> > On Tue, Oct 28, 2014 at 11:57:50AM +, Arun Siluvery wrote:
>> >> WaDisableInstructionShootdown:chv
>> >> WaForceEnableNonCoherent:chv
>>
On Tue, 2014-10-28 at 11:43 -0200, Paulo Zanoni wrote:
> 2014-10-28 11:12 GMT-02:00 Imre Deak :
> > On Mon, 2014-10-27 at 17:54 -0200, Paulo Zanoni wrote:
> >> From: Paulo Zanoni
> >>
> >> Because, really, the abstraction is not working for us. It is nice for
> >> VLV, but doesn't add anything use
On Tue, Oct 28, 2014 at 01:32:01PM +, Siluvery, Arun wrote:
> On 28/10/2014 12:23, Ville Syrjälä wrote:
> > On Tue, Oct 28, 2014 at 11:57:50AM +, Arun Siluvery wrote:
> >> WaDisableInstructionShootdown:chv
> >> WaForceEnableNonCoherent:chv
> >> WaHdcDisableFetchWhenMasked:chv
> >> WaDisable
On Tue, Oct 28, 2014 at 11:26:51AM -0200, Paulo Zanoni wrote:
> 2014-10-28 5:49 GMT-02:00 Daniel Vetter :
> > On Mon, Oct 27, 2014 at 05:47:51PM -0200, Paulo Zanoni wrote:
> >> From: Paulo Zanoni
> >>
> >> On HSW+, one encoder (DDI) can have multiple connectors (HDMI and DP).
> >> If no connector
In the interest of reducing magic numbers and having to cross check with
the specs all the time.
Signed-off-by: Jani Nikula
---
include/drm/drm_edid.h | 102 +
1 file changed, 102 insertions(+)
diff --git a/include/drm/drm_edid.h b/include/drm/drm
The Baseline_ELD_Len field does not include ELD Header Block size.
From High Definition Audio Specification, Revision 1.0a:
The header block is a fixed size of 4 bytes. The baseline block
is variable size in multiple of 4 bytes, and its size is defined
in the header block
On Tue, Oct 28, 2014 at 03:10:14PM +0200, Ander Conselvan de Oliveira wrote:
> Currently we program just DPSCNTR and DSPSTRIDE directly from the ring
> interrupt handler, which is fine since the hardware guarantees that
> those are update atomically. When we have atomic page flips we'll want
> to b
From: Ville Syrjälä
When we suspend we turn everything off so the pps should be idle, and we
also (or at least should) disable all power wells which will reset the
power sequencer port assignment. So when we resume all power sequencers
should be in their reset state. However it's at least theoret
From: Ville Syrjälä
The pps timestamp initialization was accidentally lost on vlv/chv in
commit a4a5d2f8a96e09844a91469e889f15bd5e927399
Author: Ville Syrjälä
Date: Thu Sep 4 14:54:20 2014 +0300
drm/i915: Track which port is using which pipe's power sequencer
Restore it so that we av
On 19/10/2014 15:09, Daniel Vetter wrote:
On Mon, Oct 06, 2014 at 03:15:24PM +0100, john.c.harri...@intel.com wrote:
From: John Harrison
For: VIZ-4377
Signed-off-by: john.c.harri...@intel.com
We have places that shovel stuff onto the ring without an explicit
add_request. Or at least we've had
On 19/10/2014 15:04, Daniel Vetter wrote:
On Fri, Oct 10, 2014 at 12:39:49PM +0100, john.c.harri...@intel.com wrote:
From: John Harrison
For: VIZ-4377
Signed-off-by: john.c.harri...@intel.com
---
drivers/gpu/drm/i915/i915_debugfs.c |3 +--
drivers/gpu/drm/i915/i915_drv.h | 18 ++
On 19/10/2014 13:55, Daniel Vetter wrote:
On Mon, Oct 06, 2014 at 03:15:13PM +0100, john.c.harri...@intel.com wrote:
From: John Harrison
To thin commit message.
Also I wonder whethere we should track the olr state more explicitly in
the request structure instead of jumping through all these h
2014-10-28 11:12 GMT-02:00 Imre Deak :
> On Mon, 2014-10-27 at 17:54 -0200, Paulo Zanoni wrote:
>> From: Paulo Zanoni
>>
>> Because, really, the abstraction is not working for us. It is nice for
>> VLV, but doesn't add anything useful on SNB/HSW/BDW. We want to change
>> this code due to a recentl
On 28/10/2014 12:23, Ville Syrjälä wrote:
On Tue, Oct 28, 2014 at 11:57:50AM +, Arun Siluvery wrote:
WaDisableInstructionShootdown:chv
WaForceEnableNonCoherent:chv
WaHdcDisableFetchWhenMasked:chv
WaDisableFenceDestinationToSLM:chv (pre-production)
s/WaDisableDopClockGating/WaDisableRowChick
2014-10-28 5:49 GMT-02:00 Daniel Vetter :
> On Mon, Oct 27, 2014 at 05:47:51PM -0200, Paulo Zanoni wrote:
>> From: Paulo Zanoni
>>
>> On HSW+, one encoder (DDI) can have multiple connectors (HDMI and DP).
>> If no connector is connected, we consider the encoder type to be
>> INTEL_OUTPUT_UNKNOWN.
2014-05-19 11:19 GMT-03:00 :
> From: Ville Syrjälä
>
> On pre-HSW we have two encoders per digital port: one HDMI, one DP.
> However they are the same physical port in hardware and we can't enable
> both at the same time. Reject the modeset if the user attempts this.
>
> So far we've been saved b
On Mon, 2014-10-27 at 17:54 -0200, Paulo Zanoni wrote:
> From: Paulo Zanoni
>
> Because, really, the abstraction is not working for us. It is nice for
> VLV, but doesn't add anything useful on SNB/HSW/BDW. We want to change
> this code due to a recently-discovered bug, but we can't seem to find
>
A follow up patch will call this funcion from a work context for the
mmio flip, in which case we cannot acquire the modeset locks. That's
not a problem though, since the check is there to protect vblank and
the mode, but the code that changes that waits for pending flips
first.
Signed-off-by: Ande
Signed-off-by: Ander Conselvan de Oliveira
---
drivers/gpu/drm/i915/intel_sprite.c | 25 +
1 file changed, 25 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_sprite.c
b/drivers/gpu/drm/i915/intel_sprite.c
index 8b80d68..f9ddedc 100644
--- a/drivers/gpu/drm/i915/in
Currently we program just DPSCNTR and DSPSTRIDE directly from the ring
interrupt handler, which is fine since the hardware guarantees that
those are update atomically. When we have atomic page flips we'll want
to be able to update also the offset registers, and then we need to use
the vblank evade
From: Akash Goel
A new libdrm interface 'drm_intel_gem_bo_map_wc' is provided by this
patch. Through this interface Gfx clients can create write combining
virtual mappings of the Gem object. It will provide the same funtionality
of 'mmap_gtt' interface without the constraints of limited aperture
On Fri, Oct 24, 2014 at 02:51:35PM +0100, Gustavo Padovan wrote:
> From: Gustavo Padovan
>
> Merge it into the plane update_plane() callback and make other
> users use the update_plane() functions instead.
>
> The fb != crtc->cursor->fb was already inside intel_crtc_cursor_set_obj()
> so we fold
On Tue, Oct 28, 2014 at 11:57:50AM +, Arun Siluvery wrote:
> WaDisableInstructionShootdown:chv
> WaForceEnableNonCoherent:chv
> WaHdcDisableFetchWhenMasked:chv
> WaDisableFenceDestinationToSLM:chv (pre-production)
>
> s/WaDisableDopClockGating/WaDisableRowChickenDopClockGating, because another
Similar to the hsw/bdw enable sequence rewrite.
v3: replace vblank wait with a comment
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/intel_audio.c | 58 +-
1 file changed, 26 insertions(+), 32 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_audio.
There's some serious confusion regarding ELD valid bit that gets set and
cleared back and forth etc. Rewrite it all based on the documented audio
codec enable/disable sequences.
v3: replace vblank wait with a comment
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/intel_audio.c | 110 ++
Hi Ville,
2014-10-24 Ville Syrjälä :
> On Fri, Oct 24, 2014 at 02:51:35PM +0100, Gustavo Padovan wrote:
> > From: Gustavo Padovan
> >
> > Merge it into the plane update_plane() callback and make other
> > users use the update_plane() functions instead.
> >
> > The fb != crtc->cursor->fb was al
Some of the workarounds are not required to be applied in later
revisions so restrict them based on revision.
For: VIZ-4090
Signed-off-by: Arun Siluvery
---
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/intel_ringbuffer.c | 20
2 files changed, 14 ins
WaDisableInstructionShootdown:chv
WaForceEnableNonCoherent:chv
WaHdcDisableFetchWhenMasked:chv
WaDisableFenceDestinationToSLM:chv (pre-production)
s/WaDisableDopClockGating/WaDisableRowChickenDopClockGating, because another
CHV WA is defined with the same name in intel_pm.c for a different reg.
F
Keep the driver modifications to ELD together. This also sets the
Conn_Type for G4X DP which wasn't done before.
Clean up the debugs while at it; this is all obvious from the connector
name.
v3: add missing ~ (Rodrigo)
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/intel_audio.c | 19
On Tue, Oct 28, 2014 at 10:57:45AM +, Damien Lespiau wrote:
> Because the plane registers are different in Skylake we need to adapt
> the MMIO code as well.
>
> v2: Don't introduce yet another vfunc when the direction is do
> consolidate the plane updates to use the same code path (Daniel)
>
From: Ville Syrjälä
The power seqeuencer kick procedure requires the DPLL to be running
in order to complete successfully. In case the DPLL isn't currently
running when we need to kick the power seqeuncer enable it
temporarily. This can happen eg. during ->detect() when the pipe is
not already ac
On Tue, Oct 28, 2014 at 08:46:21AM -0200, Paulo Zanoni wrote:
> 2014-10-28 5:49 GMT-02:00 Daniel Vetter :
> > On Mon, Oct 27, 2014 at 05:47:51PM -0200, Paulo Zanoni wrote:
> >> From: Paulo Zanoni
> >>
> >> On HSW+, one encoder (DDI) can have multiple connectors (HDMI and DP).
> >> If no connector
Because the plane registers are different in Skylake we need to adapt
the MMIO code as well.
v2: Don't introduce yet another vfunc when the direction is do
consolidate the plane updates to use the same code path (Daniel)
Signed-off-by: Damien Lespiau
---
drivers/gpu/drm/i915/intel_display.c | 3
Hello Chris Wilson,
The patch 1893a71b1eba: "drm/i915: Inline feature detection into
sanitize_enable_ppgtt" from Sep 19, 2014, leads to the following
static checker warning:
drivers/gpu/drm/i915/i915_gem_gtt.c:70 sanitize_enable_ppgtt()
warn: we tested 'has_aliasing_ppgtt' before
2014-10-28 5:49 GMT-02:00 Daniel Vetter :
> On Mon, Oct 27, 2014 at 05:47:51PM -0200, Paulo Zanoni wrote:
>> From: Paulo Zanoni
>>
>> On HSW+, one encoder (DDI) can have multiple connectors (HDMI and DP).
>> If no connector is connected, we consider the encoder type to be
>> INTEL_OUTPUT_UNKNOWN.
On Tue, Oct 28, 2014 at 11:07:27AM +0200, Ville Syrjälä wrote:
> On Tue, Oct 28, 2014 at 09:34:40AM +0100, Daniel Vetter wrote:
> > On Tue, Oct 28, 2014 at 10:14:54AM +0200, Ville Syrjälä wrote:
> > > On Tue, Oct 28, 2014 at 09:10:13AM +0100, Daniel Vetter wrote:
> > > > On Thu, Oct 16, 2014 at 09:
i-g-t has become a fairly big project with lots of people involved, so
lets document the basics and formalize the current process a bit.
Also use this opportunity to announce Thomas Wood as igt maintainer
once more.
v2: Recommend --subject-prefix="PATCH i-g-t" as suggested by Damien.
v3: Clean o
On Mon, 27 Oct 2014, Rodrigo Vivi wrote:
> On Mon, Oct 27, 2014 at 7:26 AM, Jani Nikula wrote:
>> Keep the driver modifications to ELD together. This also sets the
>> Conn_Type for G4X DP which wasn't done before.
>>
>> Clean up the debugs while at it; this is all obvious from the connector
>> na
On Tue, Oct 28, 2014 at 09:34:40AM +0100, Daniel Vetter wrote:
> On Tue, Oct 28, 2014 at 10:14:54AM +0200, Ville Syrjälä wrote:
> > On Tue, Oct 28, 2014 at 09:10:13AM +0100, Daniel Vetter wrote:
> > > On Thu, Oct 16, 2014 at 09:27:28PM +0300, ville.syrj...@linux.intel.com
> > > wrote:
> > > > From
From: Ville Syrjälä
The power seqeuencer kick procedure requires the DPLL to be running
in order to complete succesfully. In case the DPLL isn't currently
running when we need to kick the power seqeuncer enable it
temporarily. This can happen eg. during ->detect() when the pipe is
not already act
> From: Daniel Vetter
> Sent: Thursday, October 23, 2014 8:10 PM
>
> On Thu, Oct 23, 2014 at 01:01:28PM +0200, Gerd Hoffmann wrote:
> > Hi,
> >
> > > Stuf like driver load/unload, suspend/resume, runtime pm and gpu reset
> are
> > > already supre-fragile as-is. Every time we change something in
On Mon, Oct 27, 2014 at 11:03:26AM +, Ceraolo Spurio, Daniele wrote:
> On 10/27/2014 8:49 AM, Chris Wilson wrote:
> >On Fri, Oct 24, 2014 at 04:30:52PM +0100, daniele.ceraolospu...@intel.com
> >wrote:
> >>From: Daniele Ceraolo Spurio
> >>
> >>These tracepoints are useful for observing the cre
On Tue, Oct 28, 2014 at 10:14:54AM +0200, Ville Syrjälä wrote:
> On Tue, Oct 28, 2014 at 09:10:13AM +0100, Daniel Vetter wrote:
> > On Thu, Oct 16, 2014 at 09:27:28PM +0300, ville.syrj...@linux.intel.com
> > wrote:
> > > From: Ville Syrjälä
> > >
> > > eDP ports need the power seqeuncer whenever
Hi Zhigang,
On Tue, Oct 28, 2014 at 7:31 AM, Zhigang Gong
wrote:
> Vasily,
>
> Could you try ImageMagick(convert) again with latest git master
> beignet(git-e46764f). It should work now.
It works fine now. Thank you!
Regards,
Vasily
>
> Thanks,
> Zhigang Gong.
>
> On Fri, Oct 24, 2014 at 04:36
On Mon, Oct 27, 2014 at 07:56:50PM +0200, Imre Deak wrote:
> On Thu, 2014-10-16 at 21:27 +0300, ville.syrj...@linux.intel.com wrote:
> > From: Ville Syrjälä
> >
> > After weeks or months of beating on the hardware I finally managed
> > to figure out how to kick the vlv/chv power sequencer in a re
On Thu, Oct 16, 2014 at 09:29:59PM +0300, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> In case we fumble something and end up picking an already used power
> seqeuencer in vlv_power_sequencer_pipe() at least try to steal it
> gracefully. In theory this should never happen though
On Mon, 27 Oct 2014, Rodrigo Vivi wrote:
> On Mon, Oct 27, 2014 at 7:26 AM, Jani Nikula wrote:
>> The audio programming sequence states that the ELD must be written and
>> enabled after the pipe is ready. Indeed, this should clarify the
>> situation with
>
> Where/what doc can I confirm this?
Bs
On Tue, Oct 28, 2014 at 09:22:12AM +0100, Daniel Vetter wrote:
> On Thu, Oct 16, 2014 at 09:29:45PM +0300, ville.syrj...@linux.intel.com wrote:
> > From: Ville Syrjälä
> >
> > The power seqeuencer kick procedure requires the DPLL to be running
> > in order to complete succesfully. In case the DPL
> From: Daniel Vetter [mailto:daniel.vet...@ffwll.ch] On Behalf Of Daniel Vetter
> Sent: Thursday, October 23, 2014 4:56 PM
>
> On Thu, Oct 23, 2014 at 11:13:51AM +0800, Jike Song wrote:
> > On 10/22/2014 05:48 PM, Daniel Vetter wrote:
> > >So on a very high level I don't understand this design. F
On Tue, Oct 28, 2014 at 10:03:10AM +0200, Ville Syrjälä wrote:
> On Mon, Oct 27, 2014 at 07:10:08PM +0200, Imre Deak wrote:
> > On Thu, 2014-10-16 at 21:29 +0300, ville.syrj...@linux.intel.com wrote:
> > > From: Ville Syrjälä
> > >
> > > If there's no power sequencer assigned to the port currentl
On Thu, Oct 16, 2014 at 09:29:45PM +0300, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> The power seqeuencer kick procedure requires the DPLL to be running
> in order to complete succesfully. In case the DPLL isn't currently
> running when we need to kick the power seqeuncer enab
On Wed, Oct 22, 2014 at 08:10:40AM -0700, Todd Previte wrote:
>
> On 10/16/2014 11:27 AM, ville.syrj...@linux.intel.com wrote:
> >From: Ville Syrjälä
> >
> >There's no point in checking if the data lanes came out of reset after
> >link training. If the data lanes aren't ready link training will f
On Tue, Oct 28, 2014 at 09:10:13AM +0100, Daniel Vetter wrote:
> On Thu, Oct 16, 2014 at 09:27:28PM +0300, ville.syrj...@linux.intel.com wrote:
> > From: Ville Syrjälä
> >
> > eDP ports need the power seqeuncer whenever the port is active. Warn if
> > we accidentally steal the power sequener from
On Mon, Oct 27, 2014 at 04:55:16PM +0200, Ville Syrjälä wrote:
> On Mon, Oct 27, 2014 at 04:43:07PM +0200, Imre Deak wrote:
> > On Thu, 2014-10-16 at 21:27 +0300, ville.syrj...@linux.intel.com wrote:
> > > From: Ville Syrjälä
> > >
> > > Since we read the current power seqeuncer delays from the r
On Thu, Oct 16, 2014 at 09:27:28PM +0300, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> eDP ports need the power seqeuncer whenever the port is active. Warn if
> we accidentally steal the power sequener from an active eDP port. This
> should not happen unless there's a bug somewh
On Tue, Oct 28, 2014 at 10:03:10AM +0200, Ville Syrjälä wrote:
> Oh that makes me think of another issue. What if someone has set
> disable_power_wells=0 and then suspends the machine? I think currently
> we'd end up leaving the power wells enabled which doesn't sound very
> nice, and also it would
On Mon, Oct 27, 2014 at 07:10:08PM +0200, Imre Deak wrote:
> On Thu, 2014-10-16 at 21:29 +0300, ville.syrj...@linux.intel.com wrote:
> > From: Ville Syrjälä
> >
> > If there's no power sequencer assigned to the port currently we can't
> > very well have vdd or panel power enabled either. If we wo
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