On 08/02/2013 02:25 PM, Josep Lladonosa wrote:
> Hello,
>
> I am using a Lenovo Edge E530 and, with kernel 3.11.0-rc3, I had to
> change to this parameter to the kernel boot:
>
>
> GRUB_CMDLINE_LINUX="acpi_osi=\"!Windows 2012\""
What if you remove the above from kernel command line, and add
vid
On 08/01/2013 04:07 PM, Borislav Petkov wrote:
> On Wed, Jul 31, 2013 at 11:16:52PM +0200, Rafael J. Wysocki wrote:
>> Does reverting efaa14c help?
>
> Nope.
>
> But see my other reply to Aaron.
Assume you have specified to use intel_backlight in xorg.conf, does
booting with video.brightness_swi
Summary
We covered the platform: Haswell mobile, HSW desktop, HSW ULT, IvyBridge,
SandyBridge, IronLake. in this circle, 16 new bugs are filed, 27 bugs are still
opened, no WONTFIX bugs, 1 NOTOURBUG bugs, 2 Duplicated bugs, 5 bugs are closed.
Test Environment
Kernel: (drm-intel-testing)515726
On 08/01/2013 05:07 PM, Aaron Lu wrote:
> On 08/01/2013 04:12 PM, Borislav Petkov wrote:
>> On Thu, Aug 01, 2013 at 09:13:35AM +0800, Aaron Lu wrote:
>>> Can you please run acpi_listen and then press the Fn-Fx key, see if the
>>> events are correctly sent out?
>>
>> Like this?
>>
>> # acpi_listen
>
This one may have been going on for some time - I haven't updated the
old Intel Mac Mini in a while.
And by "not updated" I also mean that it's some really old user-space:
the machine is running F14, and cannot be updated to anything newer
without having to reinstall everything because of a stupid
The default LLC age was changed:
commit 0d8ff15e9a15f2b393e53337a107b7a1e5919b6d
Author: Ben Widawsky
Date: Thu Jul 4 11:02:03 2013 -0700
drm/i915/hsw: Set correct Haswell PTE encodings.
This caused a regression in performance on certain benchmarks. While I
think a discussion still needs to ha
The default LLC age was changed:
commit 0d8ff15e9a15f2b393e53337a107b7a1e5919b6d
Author: Ben Widawsky
Date: Thu Jul 4 11:02:03 2013 -0700
drm/i915/hsw: Set correct Haswell PTE encodings.
This caused a regression in performance on certain benchmarks. While I
think a discussion still needs to ha
Haswell GT3e has the unique feature of supporting Write-Through cacheing
of objects within the eLLC/LLC. The purpose of this is to enable the display
plane to remain coherent whilst objects lie resident in the eLLC/LLC - so
that we, in theory, get the best of both worlds, perfect display and fast
a
Some of our macros we trying to convert from an drm_device to a
drm_i915_private and then use the pointer inline. This is not only
cumbersome but prone to error. Replacing it with a typesafe function
should help catch those errors in future.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i
On 07/31/2013 04:07 PM, Ben Widawsky wrote:
The default LLC age was changed:
commit 0d8ff15e9a15f2b393e53337a107b7a1e5919b6d
Author: Ben Widawsky
Date: Thu Jul 4 11:02:03 2013 -0700
drm/i915/hsw: Set correct Haswell PTE encodings.
This caused a regression in performance on certain benchmarks
2013/7/30 Chris Wilson :
> On Mon, Jul 29, 2013 at 05:48:21PM -0300, Paulo Zanoni wrote:
>> From: Paulo Zanoni
>>
>> If the error interrupts are already disabled, don't disable and
>> reenable them. This is going to be needed when we're in PC8+, where
>> all the interrupts are disabled so we won't
Since commit 29a241c (ACPICA: Add argument typechecking for all
predefined ACPI names), _DSM parameters are validated which trigger the
following warning:
ACPI Warning: \_SB_.PCI0.GFX0._DSM: Argument #4 type mismatch - Found
[Integer], ACPI requires [Package] (20130517/nsarguments-95)
ACP
On Fri, Jul 05, 2013 at 04:48:28PM +0300, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> Certain SNB steppings need to disable DOP clock gating, and the only
> way to do that is to use the MISCCPCTL register.
Based on some more research it appears we don't need this after all.
It
On Thu, Aug 01, 2013 at 04:18:50PM +0300, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> Rather than having to read the latency values out every time, just
> store them in dev_priv.
>
> On ILK and IVB there is a difference between some of the latency
> values for different planes
From: Ville Syrjälä
All the ILK+ WM compute functions take the latency values in 0.1us
units. Add a few comments to remind people about that.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_pm.c | 17 ++---
1 file changed, 14 insertions(+), 3 deletions(-)
diff --git a/
From: Ville Syrjälä
Adjust the current ILK/SNB/IVB watermark codepaths to use the
pre-populated latency values from dev_priv instead of reading
them out from the registers every time.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_reg.h | 9 ---
drivers/gpu/drm/i915/intel_pm.c
From: Ville Syrjälä
Return UINT_MAX for the calculated WM level if the latency is zero.
This will lead to marking the WM level as disabled.
I'm not sure if latency==0 should mean that we want to disable the
level. But that's the implication I got from the fact that we don't
even enable the water
From: Ville Syrjälä
Seeing the watermark latency values in dmesg might help sometimes.
v2: Use DRM_ERROR() when expected latency values are missing
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_pm.c | 37 +
1 file changed, 37 insertions(+)
di
From: Ville Syrjälä
Rather than pass around the plane latencies, just grab them from
dev_priv nearer to where they're needed. Do the same for cursor
latencies.
v2: Add some comments about latency units
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_pm.c | 34 -
From: Ville Syrjälä
Rather than having to read the latency values out every time, just
store them in dev_priv.
On ILK and IVB there is a difference between some of the latency
values for different planes, so store the latency values for each
plane type separately, and apply the necesary fixups d
From: Ville Syrjälä
ILK has a slightly different way to read out the watermark
latency values. On ILK the LP0 latenciy values are in fact
not stored in any register, and instead we must use fixed
values.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_pm.c | 7 +++
1 file chang
From: Ville Syrjälä
SNB and IVB have slightly a different way to read out the
watermark latency values.
Reviewed-by: Paulo Zanoni
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_pm.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drive
From: Ville Syrjälä
The LP1+ watermark latency values need to be multiplied by 5 to
make the suitable for watermark calculations. However on pre-HSW
platforms we're going to need the raw value later when we have to
write it to the WM_LPn registers' latency field. So delay the
multiplication until
From: Ville Syrjälä
For calculating watermarks we want to know whether sprites are
scaled. Pass that information to update_sprite_watermarks() so that
eventually we may do some watermark pre-computing.
v2: Use "enabled" consistently, fix commit msg
Reviewed-by: Paulo Zanoni
Signed-off-by: Vill
From: Ville Syrjälä
The latency values fit in uint16_t, so let's save a few bytes.
Reviewed-by: Paulo Zanoni
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_pm.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu
From: Ville Syrjälä
Move parsing of MCH_SSKPD to a separate function, we'll add other
platforms there later.
Reviewed-by: Paulo Zanoni
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_pm.c | 34 --
1 file changed, 20 insertions(+), 14 deletions(-)
d
From: Ville Syrjälä
These functions are appropriate for everything since ILK.
Reviewed-by: Paulo Zanoni (SNB/IVB only)
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_pm.c | 40
1 file changed, 20 insertions(+), 20 deletions(-)
diff --git
From: Ville Syrjälä
The FBC watermark doesn't depend on the latency value, so no point in
passing it in.
Reviewed-by: Paulo Zanoni
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_pm.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/int
From: Ville Syrjälä
hsw_wm_get_pixel_rate() isn't specific to HSW. In fact it should be made
to handle all gens, but for now it depends on the PCH panel fitter
state, so give it an ilk_ prefix.
Reviewed-by: Paulo Zanoni
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_pm.c | 6 +++-
From: Ville Syrjälä
Don't subtract one from the sprite width before watermark calculations.
Reviewed-by: Paulo Zanoni
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_pm.c | 2 +-
drivers/gpu/drm/i915/intel_sprite.c | 18 +-
2 files changed, 10 insertions(+), 1
From: Ville Syrjälä
Using the destination width in the sprite WM calculations isn't correct.
We should be using the source width.
Reviewed-by: Paulo Zanoni
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_sprite.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --
Here's a repost of the beginning of the ILK watermark series.
I was a bit lazy and decided to repost all the patches up to a point. I
dropped the 'bool is_lp' > 'int level' patch, and I added a few extra
patches to the end of the series.
I still left the WaDoubleCursorLP3Latency handling in becau
On Tue, Jul 16, 2013 at 9:12 AM, Daniel Vetter wrote:
> All the gem based kms drivers really want the same function to
> destroy a dumb framebuffer backing storage object.
>
> So give it to them and roll it out in all drivers.
>
> This still leaves the option open for kms drivers which don't use G
On 08/01/2013 04:12 PM, Borislav Petkov wrote:
> On Thu, Aug 01, 2013 at 09:13:35AM +0800, Aaron Lu wrote:
>> Can you please run acpi_listen and then press the Fn-Fx key, see if the
>> events are correctly sent out?
>
> Like this?
>
> # acpi_listen
> video/brightnessdown BRTDN 0087
>
HI Chris,
I retested idle power, idle power is the same(12.5 w) with patch and without
patch. maybe the machine is unstable after plugged in power.
> -Original Message-
> From: Chris Wilson [mailto:ch...@chris-wilson.co.uk]
> Sent: Thursday, August 01, 2013 3:44 PM
> To: Zhang, Ouping
>
On Tue, Jul 30, 2013 at 04:49:18PM -0300, Paulo Zanoni wrote:
> 2013/7/5 :
> > From: Ville Syrjälä
> >
> > Passing the level insted of "is_lp" seems easier. The end result is the
> > same though.
> >
> > Signed-off-by: Ville Syrjälä
> > ---
> > drivers/gpu/drm/i915/intel_pm.c | 8
> >
On Thu, Aug 01, 2013 at 05:15:36AM +, Zhang, Ouping wrote:
> Test patch on Harris Beach,
> max frequency: 1100
> lowest frequency : 200
>
> For doom3, When waking from idle, boost the render frequency to RP1(200). At
> every upclock request, increase to halfway between the current frequency
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