On Fri, Jul 05, 2013 at 04:48:28PM +0300, ville.syrj...@linux.intel.com wrote: > From: Ville Syrjälä <ville.syrj...@linux.intel.com> > > Certain SNB steppings need to disable DOP clock gating, and the only > way to do that is to use the MISCCPCTL register.
Based on some more research it appears we don't need this after all. It should only affect pre-production hardware. > Just disable it for every SNB, and then I suppose we may not have to > worry about WaRevertDopClockGateFix2. > > There's also another seemingly related workaround called > WaForTogglingDopClkGatingBit, but there are no details to explain what > needs to be done. Which could mean we need to look into these two... > > Signed-off-by: Ville Syrjälä <ville.syrj...@linux.intel.com> > --- > drivers/gpu/drm/i915/intel_pm.c | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index b6d8d81..d18fb39 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -4565,6 +4565,10 @@ static void gen6_init_clock_gating(struct drm_device > *dev) > I915_WRITE(CACHE_MODE_0, > _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB)); > > + /* WaDisableDopClockGating:snb */ > + I915_WRITE(GEN6_MISCCPCTL, I915_READ(GEN6_MISCCPCTL) & > + ~GEN6_DOP_CLOCK_GATE_ENABLE); > + > I915_WRITE(GEN6_UCGCTL1, > I915_READ(GEN6_UCGCTL1) | > GEN6_BLBUNIT_CLOCK_GATE_DISABLE | > -- > 1.8.1.5 -- Ville Syrjälä Intel OTC _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
