Re: [gem5-users] LPDDR4 SDRAM support in gem5?

Hi Dhaval, I am not sure what your "LPDDR4 DRAM memory component" meant. If you refers to an LPDDR4 controller model, the answer is *yes*. Gem5's memory controller supports the basic features of LPDDR4. It already provides you the default LPDDR3's timing. You can start from it with necessary modif

Re: [gem5-users] Slides available from MICRO-48 tutorial on AMD's APU model in gem5.

Thank you very much for the sharing! -Tao -Tao On Tue, Dec 15, 2015 at 8:30 AM, Gutierrez, Anthony < anthony.gutier...@amd.com> wrote: > Hello All, > > > > As many of you probably know we (AMD) recently made our APU/compute-GPU > model publically available, and it should be pushed to the gem5 s

Re: [gem5-users] gem5 stable release proposal [PLEASE VOTE!]

Hi Jason, Thanks for the proposal. Regarding the branch option for stable release, can we do it by git tagging? I think one-release per year is too long. I prefer three-release per year. Thanks, -Tao On Mon, Dec 16, 2019 at 11:50 AM Jason Lowe-Power wrote: > Hi all, > > As many of you have

Re: [gem5-users] fast forward in SMT processor

After the fast-forward, gem5 will switch the cpu to detailed or inorder mode, which can satisfy your requirement. -Tao From: gem5-users-boun...@gem5.org [mailto:gem5-users-boun...@gem5.org] On Behalf Of Fangfei Liu Sent: Wednesday, November 07, 2012 11:32 PM To: gem5-users@gem5.org Subjec

Re: [gem5-users] fast forward in SMT processor

@gem5.org [gem5-users-boun...@gem5.org] on behalf of Tao Zhang [tao.zhang.0...@gmail.com] Sent: Wednesday, November 07, 2012 11:45 PM To: 'gem5 users mailing list' Subject: Re: [gem5-users] fast forward in SMT processor After the fast-forward, gem5 will switch the cpu to detailed or inor

Re: [gem5-users] fast forward in SMT processor

in atomic mode, but it's supposed not to be able to simulate SMT in atomic mode. Have you ever tried to do fast-forward for SMT processor? Thanks! Fangfei _ From: gem5-users-boun...@gem5.org [gem5-users-boun...@gem5.org] on behalf of Tao Zhang [tao.zhang.0...@gmail.com]

Re: [gem5-users] Could not load kernel file /vmlinux.arm.smp.fb.2.6.38.8

You can use "--kernal" in the command line to specify the path for your kernel. See configs/common/Options.py for detail. -Tao From: gem5-users-boun...@gem5.org [mailto:gem5-users-boun...@gem5.org] On Behalf Of pmo...@masonlive.gmu.edu Sent: Saturday, November 24, 2012 10:31 AM To: gem5-use

Re: [gem5-users] (no subject)

this is correct. However, there should be more tag bits for the purpose of cache conherence and replacement (e.g., valid, dirty, LRU...) -Tao On 11/24/2012 01:23 AM, Nitin Chaturvedi wrote: Dear sir srry for wrong interpretation..please check again and correct me if i am wrong

Re: [gem5-users] Fwd: Only one CPU active in a multicore environment during simulation in SE mode

Hi Pushkar, According to my experience, you should create new liveprocess for each (same) executive file. You can first use different benchmarks to see whether the problem (segmentation fault) is still there. If not, then you can come back to this special simulation: create new (empty) livepr

Re: [gem5-users] Fwd: Only one CPU active in a multicore environment during simulation in SE mode

You try to generate the multiprocesses in the SMT session (line 120--154). In this session, line 151 modified the numThreads to 4. Therefore, each CPU assumes it has 4 threads (line 158). However, definitely, you just assigned one workload to each CPU... You can manually set numThreads to 1 an

Re: [gem5-users] Could not load kernel file/vmlinux.arm.smp.fb.2.6.38.8

--- *From:* gem5-users-boun...@gem5.org [gem5-users-boun...@gem5.org] on behalf of Tao Zhang [tao.zhang.0...@gmail.com] *Sent:* Saturday, November 24, 2012 10:34 AM *To:* 'gem5 users mailing list' *Subject:* Re: [gem5-users] Could not load kernel file /vmlinux

Re: [gem5-users] can't load the kernel ( successfully changed the kernel location and am using sudo)

Kernel should be a file (e.g., vmlinux) but not a directory. -Tao From: gem5-users-boun...@gem5.org [mailto:gem5-users-boun...@gem5.org] On Behalf Of pmo...@masonlive.gmu.edu Sent: Saturday, November 24, 2012 11:57 AM To: gem5-users@gem5.org Subject: [gem5-users] can't load the kernel ( su

Re: [gem5-users] system.cc, line 62 and 124--can't load the kernel ( successfully changed the kernel location and am using sudo)

know what to do now. Could someone help me please? Thank you, Parnian _ From: gem5-users-boun...@gem5.org [gem5-users-boun...@gem5.org] on behalf of Tao Zhang [tao.zhang.0...@gmail.com] Sent: Saturday, November 24, 2012 11:58 AM To: 'gem5 users mailing list' Subject: Re: [gem

Re: [gem5-users] DRAMSim2 Patch--deleted link

Hi Mansour, For some reason, the patch is not available anymore. Sorry for the inconvenience. -Tao From: gem5-users-boun...@gem5.org [mailto:gem5-users-boun...@gem5.org] On Behalf Of Mansour Shafaei Moghaddam Sent: Monday, January 07, 2013 11:07 AM To: gem5-users@gem5.org Subject: [gem5

Re: [gem5-users] DRAMSim2 Patch--deleted link

s-boun...@gem5.org] On Behalf Of Tao Zhang Sent: Monday, January 07, 2013 4:28 PM To: 'gem5 users mailing list' Subject: Re: [gem5-users] DRAMSim2 Patch--deleted link Hi Mansour, For some reason, the patch is not available anymore. Sorry for the inconvenience. -Tao From:

Re: [gem5-users] DRAMSim2 Patch--deleted link

Hi Andreas, I am not sure if you have added the tFAW and tRRD in SimpleDRAM. I saw the slides on MICRO tutorial that tFAW had been completed but I didn't find any change in the latest code. Regards, -Tao -Original Message- From: gem5-users-boun...@gem5.org [mailto:gem5-users-boun...@ge

Re: [gem5-users] question about simpleDRAM

Hi Shuchang, Did you fast-forward any instructions? If so, the atomicCPU will be used during the fastforward. In my case, the SimpleDRAM works well. -Tao From: gem5-users-boun...@gem5.org [mailto:gem5-users-boun...@gem5.org] On Behalf Of 单书畅 Sent: Wednesday, January 09, 2013 10:56 PM

Re: [gem5-users] question about simpleDRAM

long simulation, the simulation was not halted, which means that the simulation never called doDRAMAccess function. Regards, Shuchang 2013/1/10 Tao Zhang Hi Shuchang, Did you fast-forward any instructions? If so, the atomicCPU will be used during the fastforward. In my case, the

Re: [gem5-users] question about reading out a whole DRAM row data

Hi Shuchang, In my opinion, your code are almost correct expect that the pkt->getSize() does return the cacheline size (64 in byte). You don’t need to multiply another 64 again. In fact, AbstractMemory has the function “access(PacketPtr pkt)” in which the data is also copied. You can read

Re: [gem5-users] question about reading out a whole DRAM row data

point to the start address > of the row (given pkt->getAddr)? > > > /===/ > /uint8_t *myHostAddr = pmemAddr + (pkt->getAddr() - pkt->getAddr() % > linesPerRow) - range.start;/ > /=======

Re: [gem5-users] question about reading out a whole DRAM row data

t reading out a whole DRAM row data Hi Tao: Thanks for your reply. :) Shuchang 2013/1/28 Tao Zhang <mailto:tao.zhang.0...@gmail.com>> Hi Shuchang, If we assume the memory space in both host machine and simulator is continuous, then we can calculate the row address as

Re: [gem5-users] get same results from different benchmarks

Hi Mitch, I agree with you. The original command didn't use either checkpoint or fastforward. Therefore, no cpu switching is expected by gem5. However, the PARSEC script (i assume it is generated automatically) forces the cpu switching. This should be the reason of assertion failure. Bahar,

Re: [gem5-users] Unimplemented Function

Hi Rodrigo, Yes, SPEC2006 can be run in SE mode definitely. However, perlbench has some trouble so that it should be skipped. see http://www.gem5.org/SPEC2006_benchmarks for the detail. -Tao On 02/02/2013 11:34 AM, Rodrigo Reynolds Ramírez wrote: Hello everyone: I am trying to run the SPEC

Re: [gem5-users] Memory Initialization

do you mean cache or main memory? -Tao On 02/05/2013 11:46 AM, Yinchong Feng wrote: Hi All, I'm new at using gem5, and I'm trying to run benchmarks on gem5 in SE mode. I feel confused about the momory initialization in SE mode. When I ran the bianries with debug-flags MemoryAccess, MemDepUni

Re: [gem5-users] help with Gem5

Hi Madarbux, If you are using the classic memory model, then you can get the memory address from the packet by using getAddr(). You can refer to packet.hh and abstract_mem.hh for the detail. -Tao On 02/05/2013 05:54 AM, ridwan madarbux wrote: Dear Sir, My name is Ridwan and I am a

Re: [gem5-users] Memory Initialization

stem.physmem: 0070 04 00 00 00 07 00 00 00 d4 d6 07 00 d4 d6 > 08 00 TV TV > > Do you have any idea? > > Thanks, > Yinchong > > > 2013/2/5 Tao Zhang <mailto:tao.zhang.0...@gmail.com>> > > do you mean cache or main memory? > > -Tao >

Re: [gem5-users] Access to PC

Hi Rodrigo, please try "pkt->req->getPC()". There is a request point in packet.hh. see request.hh for the function information. -Tao On 02/05/2013 01:11 PM, Rodrigo Reynolds Ramírez wrote: Hello everyone, I am working in some cache replacement policies, for some of them I need the PC value

Re: [gem5-users] Default Memory Hierarchy Port Configuration?

Hi Gabriel, When you use both L1 and L2 cache, the second figure is correct. When you only use L1, Icache and Dcache will connect to memory bus separately. (just remove L2 in figure 2). You can refer to configs/common/CacheConfig.py for the connection detail. -Tao On 02/21/2013 07:30 PM, Ga

Re: [gem5-users] Does SE mode support L3 cache!!

Hi Alshamlan, you can attach a L3 cache quickly by using the classic memory model. What you need to do is to 1) instantiate a L3 cache (you can use the class of L2Cache); 2) create a tol3bus and 3) connect the l2 and l3 port on the bus. Please see configs/common/Caches.py for the L2Cache cla

Re: [gem5-users] How to get started with Ruby

Hi Shivam, gem5 has two different memory systems: classic memory and ruby memory. You cannot use both simultaneously. http://www.gem5.org/General_Memory_System Generally, you can directly use the existing DRAM model in classic memory (SimpleMemory, SimpleDDR3, SimpleLPDDR2_S4, see src/mem/S

Re: [gem5-users] How to get started with Ruby

25, 2013 at 11:29 PM, Tao Zhang <mailto:tao.zhang.0...@gmail.com>> wrote: Hi Shivam, gem5 has two different memory systems: classic memory and ruby memory. You cannot use both simultaneously. http://www.gem5.org/General_Memory_System Generally, you can directly use th

Re: [gem5-users] Unexpected results on addition of L3 Cache in Classic Memory Model

Hi Shivam, It seems weird since L2 reports should have been there. How did you declare your L3Cache() and l2_cache_class()? Did you see both "l2" and "l3" in m5out/config.ini? -Tao On 02/27/2013 12:58 PM, Shivam Agarwal wrote: Hello all I have incorporated an L3 cache in configs/common/C

Re: [gem5-users] SE+Ruby problem

Hi Hamid, ALPHA SE mode supports Ruby. In your command, you didn't specify the cpu type as "detailed" or "timing" that ruby requires. Please add "--cpu-type=detailed" or "--cpu-type=timing" in your command and try again. Also, make sure the "m" is compiled with "-static" option. -Tao On 03/

Re: [gem5-users] Extending the SimpleMemory class

Hi Lluc, you may include #include "params/MyMemory.hh" in my_mem.hh. -Tao On 03/08/2013 11:02 AM, Lluc Alvarez Marti wrote: Hi! I'm trying to create a MyMemory class that is a subclass of the SimpleMemory class in order to have a new kind of memory with additional features. Unfortunately, I

Re: [gem5-users] which class simulate Memory?

Hi Chuanlei, You can look at simple_dram.cc. It could be used as DDR3 timing model. -Tao From: gem5-users-boun...@gem5.org [mailto:gem5-users-boun...@gem5.org] On Behalf Of zhengchl Sent: Wednesday, March 20, 2013 8:47 AM To: gem5 users mailing list Subject: [gem5-users] which class si

[gem5-users] gem5 build problem

ialized in this function scons: *** [build/ALPHA/python/swig/debug_wrap.fo] Error 1 scons: building terminated because of errors. ======== Regards, -- ** Tao Zhang Department of Computer Science& Engineering, Col

Re: [gem5-users] gem5 build problem

env.Append(CCFLAGS='-Werror') Steve On Wed, Mar 20, 2013 at 7:52 PM, Tao Zhang <mailto:tao.zhang.0...@gmail.com>> wrote: Dear all, When I built the latest gem5, the following compilation erros came up. More interesting, it only happens when buiding gem5.fast.

[gem5-users] Is cache warmed up during fastforwarding?

iming CPU mode). Is it necessary to use the stardard switch--"-F -s -W -I" to warm up the cache? Regards, -- ** Tao Zhang Department of Computer Science& Engineering, College of Engineering, Pennsylvania State University 354B IST Building

Re: [gem5-users] gem5 build problem

boun...@gem5.org [mailto:gem5-users-boun...@gem5.org] *On Behalf Of *Steve Reinhardt *Sent:* Wednesday, March 20, 2013 8:09 PM *To:* gem5 users mailing list *Subject:* Re: [gem5-users] gem5 build problem The quickest fix is to delete this line in src/SConscript: swig_env.Append(CCFLAGS=&

Re: [gem5-users] About --max-inst

Hi Rodrigo, The CPU run as detailed by 250M, which is specified by –max-inst. See more details in configs/common/Simulation.py. -Tao From: gem5-users-boun...@gem5.org [mailto:gem5-users-boun...@gem5.org] On Behalf Of Rodrigo Reynolds Ramírez Sent: Wednesday, March 27, 2013 8:37 AM To: g

Re: [gem5-users] fatal: SimpleDRAM system.physmem is unconnected!

Hi Tejasi, To my knowledge, SimpleDRAM and SimpleMemory cannot work with Ruby directly. please use the classic memory instead. -Tao On 03/27/2013 08:44 PM, tejasi pimpalkhute wrote: Hi All, I am trying to run se.py using SimpleDDR3 in place of SimpleMemory and I am getting the error- fat

Re: [gem5-users] --maxinsts does not stop

Hi Rodrigo, Can you remove the –fast-forward=0 and try again? -Tao From: gem5-users-boun...@gem5.org [mailto:gem5-users-boun...@gem5.org] On Behalf Of Rodrigo Reynolds Ramírez Sent: Tuesday, April 16, 2013 12:11 PM To: gem5-users Subject: [gem5-users] --maxinsts does not stop Hello

Re: [gem5-users] --maxinsts does not stop

Please check the status of SPEC2006 benchmarks. GCC has some problem for the big (reference) input. Is this benchmark critical to your work? http://www.gem5.org/SPEC2006_benchmarks -Tao On 04/16/2013 01:01 PM, Rodrigo Reynolds Ramírez wrote: I removed –fast-forward=0 and it works, also setting

Re: [gem5-users] SimpleDRAM accuracy

Hi Amin, You can refer to Andreas's clarification for the similar concern. http://www.mail-archive.com/gem5-users@gem5.org/msg07444.html. As he said, you can use SimpleDDR3 or LPDDR2_S4 to capture a more accurate memory timing

Re: [gem5-users] SimpleDRAM accuracy

ed in terms of making a choice. Other benefits of the SimpleDRAM models (DDR3, LPDDR2 etc) is that they are fast and very configurable. Andreas From: Tao Zhang Reply-To: gem5 users mailing list Date: Thursday, 9 May 2013 04:17 To: 'gem5 users mailing list' Subject: Re: [gem5-us

Re: [gem5-users] Configuring a 3 level memory hierarchy

Hi Mohammed, Please see my answers to your questions below. -Tao From: gem5-users-boun...@gem5.org [mailto:gem5-users-boun...@gem5.org] On Behalf Of Mohammed G. Khatib Sent: Tuesday, May 28, 2013 4:43 PM To: gem5-users@gem5.org Subject: [gem5-users] Configuring a 3 level memory hierarc

Re: [gem5-users] Configuring a 3 level memory hierarchy

: www.nec-labs.com/~khatib USA On Tue, May 28, 2013 at 5:15 PM, Tao Zhang wrote: Hi Mohammed, Please see my answers to your questions below. -Tao From: gem5-users-boun...@gem5.org [mailto:gem5-users-boun...@gem5.org] On Behalf Of Mohammed G. Khatib Sent: Tuesday

Re: [gem5-users] Configuring a 3 level memory hierarchy

4 Independence Way, Suite 200 E: mghia...@gmail.com Princeton, NJ 08540 W: www.nec-labs.com/~khatib USA On Tue, May 28, 2013 at 5:42 PM, Tao Zhang wrote: Hi Mohammed, I am not quite sure what you mean “sacrifice

Re: [gem5-users] Timing CPU model

Hi Guru, Can you try --cpu-type -Tao From: gem5-users-boun...@gem5.org [mailto:gem5-users-boun...@gem5.org] On Behalf Of Guru Prasad Sent: Thursday, May 30, 2013 2:56 PM To: gem5 users mailing list Subject: Re: [gem5-users] Timing CPU model Hi Andrws, I'm running the simulations ri

Re: [gem5-users] Timing CPU model

Hi Guru, I am not quite sure the problem but I saw that you were specifying timing mode CPU model while you didn’t enable cache. Usually the system requires you use cache when timing memory model is used. Another issue is the arm_detailed core. Since you are running simulation under ARM arc

Re: [gem5-users] (no subject)

Hi Mahshid, You can use the "add_option" to add any desired options in the command line. To do this, you just add the line below (or something like it) at the beginning of your fs.py. parser.add_option("-rob", "--robsize", type="int", default=128, help="specify the rob size"); Then, af

Re: [gem5-users] Weird IPC statistics for Spec2006 Multiprogram mode

Hi Fulya, What's the L2 cache size of the 1-core test? Is it equal to the total capacity of 4-core case? The stats indicates that 4-core test has less L2 cache miss rate, which may be the reason of IPC improvement. -Tao From: gem5-users-boun...@gem5.org [mailto:gem5-users-boun...@gem5.

Re: [gem5-users] DRAMSim2+GEM5 Error

Hi Andreas, The decoupling of directory controller and memory controller is the task of Ruby rather than DRAMSim2. As long as they can be decoupled, the DRAMSim2 can be easily attached as the classic memory does. Regards, -Tao From: gem5-users-boun...@gem5.org [mailto:gem5-users-bo

Re: [gem5-users] How to Inject Bugs

Hi Zhongyuan, What do you mean "inject bugs"? You want to inject some erratic data to the main memory? -Tao On Thu, Mar 20, 2014 at 12:52 PM, Zhongyuan Ni wrote: > Hi all, > > I'm a newbie of Gem5. I am doing a project which requires injecting bugs > into memory components (uncore components)

Re: [gem5-users] Disk image not updated when resuming from checkpoint

Hi Matt, Thanks a lot for posting this. This will be helpful. I used to fix the problem by install a virtualbox ( https://www.virtualbox.org/) and do the mount/unmounts in the virtual machine. -Tao On Fri, Mar 28, 2014 at 8:57 AM, Christian Pinto wrote: > Thank you so much, > > i also have t

Re: [gem5-users] Modeling a DRAM cache by creating subclass of BaseCache or Cache?

Hi Jiakun, FYI, as an alternative, I believe you can also find the existing DRAM cache model in NVMain. You can contact Matt ( poremba at cse dot psu dot edu) to get the source code from http://wiki.nvmain.org/. thanks, -Tao On Tue, Apr 8, 2014 at 8:07 AM, jiakunli2010 wrote: > Hello all! I

[gem5-users] Welcome to our tutorial in ISCA

Dear all, We (Dr. Yuan Xie, Matt Poremba, Dr. Ke Chen, Cong Xu, and Tao Zhang) will host a tutorial co-located in this year ISCA. The tutorial is titled as Achitectural Modeling for Emerging Memory Technologies, in which we will present our latest memory models for various memories. You can

[gem5-users] SPEC2006 simulation problem

example/se_spec2006.py -b bzip2 --caches -l2cache -t -n 1 --clock 2GHz". I also sticked the config file from m5out. Thanks a lot, Description: Description: 19 ********** Tao Zhang Department of Computer Science & Engineering, College of Engineering, Penn

Re: [gem5-users] SPEC2006 simulation problem

alpha/process.cc) with a larger stack. Ali On Aug 31, 2011, at 9:15 PM, Tao Zhang wrote: Dear all, Even though 450.soplex can be run correctly, the rest benchmarks are always aborted after 1000+ "increasing stack size by one page" and the fatal information "over ma

[gem5-users] issue about ruby interconnection

le as reference). Thanks a lot, Description: 19 ****** Tao Zhang Department of Computer Science & Engineering, College of Engineering, Pennsylvania State University 351 IST Building University Park, PA 16802 (Office) 814-863-1047 (Mobile) 814

Re: [gem5-users] How to enable fast forwarding when ruby module is loaded?

Hi Yongbing, If you are using Ruby as the memory system, you can NOT leverage the fast forwarding feature because Ruby doesn't support it. Please refer to http://www.gem5.org/General_Memory_System for the comparison between classic and ruby memory system. -Tao From: gem5-users-boun...@g

Re: [gem5-users] is tick == cycle ?

Hi Mahmood, >From my point of view, tick is the time unit that can be treated as 1ps. For example, if one sets the clock frequency as "1GHz". The tick increases by every thousand. Of course, GEM5 may not execute one instruction in every clock cycle (CPI not equal to 1). So one instruction can stal

Re: [gem5-users] is tick == cycle ?

ify slide 118 with your comment? On 9/19/11, Tao Zhang wrote: > Hi Mahmood, > > From my point of view, tick is the time unit that can be treated as > 1ps. For example, if one sets the clock frequency as "1GHz". The tick > increases by every thousand. Of course, GEM5 may no

Re: [gem5-users] Is M5 support snooping cache coherence

Hi DF, The classic memory model leverages MOESI snooping protocol. Please refer to http://www.gem5.org/Classic_Memory_System for the detail. -Tao From: gem5-users-boun...@gem5.org [mailto:gem5-users-boun...@gem5.org] On Behalf Of DF liu Sent: Monday, September 19, 2011 11:14 PM To: gem5

Re: [gem5-users] Is M5 support snooping cache coherence

ge and i still have a question, how to enable the classic > memory model(because in build_opts dir,i find all configures are using Cache > coherence based directory) > Any suggestions are appreciated. > On Tue, Sep 20, 2011 at 10:19 PM, Tao Zhang wrote: > >>Hi DF, &g

Re: [gem5-users] When I use 4x4 mesh network, the simulation detects a deadlock and cannot continue

I am not sure whether it's related to the cache cohenrence protocol so i just give some hint. From your command, you didn't specify any cache coherence protocol. In other words, you use the default protoocl (MI_example). This protocol only allow one cache level (L1 cache only)... Tao 2011/9/20 lyh

Re: [gem5-users] Is M5 support snooping cache coherence

S = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU,InOrderCPU' PROTOCOL = 'MI_example' And i find that MI_example are also based Ruby On Tue, Sep 20, 2011 at 11:24 PM, Tao Zhang wrote: Hi DF, You can use ALPHA_SE as the platform and then run your simulation. The clas

Re: [gem5-users] Is M5 support snooping cache coherence

un ruby in O3CPU mode,because it is said that "Ruby only works with TimingSimpleCPU!!" in the se.py scripts. Thanks for patiention and i am very grateful for your reply. On Wed, Sep 21, 2011 at 9:17 PM, DF liu wrote: I got it~ Thanks a lot On Wed, Sep 21, 2011 at 8:38 PM, Tao

Re: [gem5-users] Is M5 support snooping cache coherence

ay what i want to do clearly, I want run splash2 in SE+Ruby mode, not FS mode. Do you have run splash2 in such mode. If yes, can you tell me how to run splash2 in SE mode with Ruby~ If no, I will try to merge se.py and run.py. Thanks a lot for you advice~ On Wed, Sep 21, 2011 at 9:55

[gem5-users] running SPEComp on ALPHA_FS

started the simulator, I didn't see the new directory under "/benchmarks". I also tried to paste the SPEComp benchmark to the root directory. But I failed again. Anyone can help me to fix it? Thank you very much! Description: 19 ** Tao Zhang Depa

Re: [gem5-users] running SPEComp on ALPHA_FS

m5.org] On Behalf Of Gabriel Michael Black Sent: Tuesday, October 04, 2011 4:55 PM To: gem5-users@gem5.org Subject: Re: [gem5-users] running SPEComp on ALPHA_FS Are you sure the simulator is actually using the image file you modified? You might want to double check that. Gabe Quoting Tao Zhang :

Re: [gem5-users] running SPEComp on ALPHA_FS

uble check that. Gabe Quoting Tao Zhang : > Dear all, > > > > When I tried to run SPEComp2001 on ALPHA_FS mode, I was stuck at how > to add the benchmark to the image. Actually, I have created an empty > image (120M, named "linux-latest-specomp.img") by gem5img

[gem5-users] "--l2size" is confusing when using RUBY

Hi, When I tried to build a CMP architecture with multiple cache banks in RUBY, I found the option "-l2size" is very confusing. Actually, it only specifies one L2 bank size. Therefore, it's better to rename it like "-l2bank_size" or add another option in configs/common/Options.py (I think the r

Re: [gem5-users] Checkpointing & Exiting

Hi, You can use option "-max-checkpoints". Set it as "1" so that gem5 will stop immediately after one checkpoint is generated. -Tao From: gem5-users-boun...@gem5.org [mailto:gem5-users-boun...@gem5.org] On Behalf Of ef Sent: Friday, November 04, 2011 4:17 PM To: gem5-users@gem5.org Subj

Re: [gem5-users] Compiling stats at multi-intervals.

Hi Surya, You may need to modify the Simulation.py in configs/commons/. Or, you create your own Simulation.py instead. m5.stats.reset() and m5.stats.dump() may help you to get the statistics periodically. -Tao On 11/08/2011 09:42 AM, Surya Narayanan wrote: Hello, Is there any opt

Re: [gem5-users] gem5 running error

I think the error message is very clear. Can you rebuild the ALPHA_FS and try again? Tao From: gem5-users-boun...@gem5.org [mailto:gem5-users-boun...@gem5.org] On Behalf Of hedieh baban Sent: Wednesday, November 09, 2011 10:29 PM To: gem5 users mailing list Subject: [gem5-users] gem5 runnin

Re: [gem5-users] Segmentation fault

Hi Meeran, GCC4.1.2 is buggy to compile GEM5. please change the compiler ( i have used 4.4.2 and 4.5.0, both are fine) and try again. -Tao On 11/10/2011 07:07 AM, Meeran Mohideeen wrote: Thank you Sir, I tried your help. I downloaded the recent version of m5(gem5-2fc7787f47a9) from the de

Re: [gem5-users] Can anyone given me a simple example of the config for MP execution in SE mode?

Hi Nifan, you can dig the code in configs/examples/se.py. In particular, the following segmentation you should take care. Note that "multiprocesses" are the workload assigned to each core (in your case, two processes should be created and assigned to two cores). The "else" branch create a pro

Re: [gem5-users] Ruby on ARM SE

Hi Xiangyu, I think the latest few versions cannot run directly. In my case, I annotate the following codes. system.cpu[i].interrupts.pio = ruby_port.master system.cpu[i].interrupts.int_master = ruby_port.slave system.cpu[i].interrupts.int_slave = ruby_port.master If y

[gem5-users] How to warm up the cache under SE+Ruby?

quot;-W" assigns the number of cycles running on cpu for the cache warmup. Then, the second switching occurs and cpu come back to run the rest simulation with "-I" cycles. Am I missing anything to run it smoothly? Regards, Tao -- ** Tao Zhang

Re: [gem5-users] Dump simulation statistics for executing a particular function

Hi Zheng, You can insert "m5.stats.reset()" immediately before the __kernel() function to restart the statistics and then call "m5.stats.dump()" following the __kernel() function to see the effect. Tao On 04/02/2012 09:39 AM, Zheng Wang wrote: Hi, I wonder how I can dump simulation statist

Re: [gem5-users] A Patch for DRAMsim2 Integration

Hi Andrew, I just finished the integration of DRAMSim2 with Ruby. Since I think Xiangyu's patch only work with classic memory, as a workaround, I can share the code with you if you'd like to use Ruby. Tao Zhang Department of CSE Penn State University (from my iphone4) On Apr 7, 201

Re: [gem5-users] A Patch for DRAMsim2 Integration

I am using Alpha now. I have tested the wrapper code by SPEC2006. I am sure this patch can support any ISA as long as Ruby can be used smoothly. You can quickly check whether ARM and Ruby is feasible. Tao Zhang Department of CSE Penn State University (from my iphone4) On Apr 7, 2012, at 9:48

[gem5-users] option "--maxtime" doesn't work?

econds(simtime) print "simulating for: ", simtime maxtick = simtime else: maxtick = m5.MaxTick Regards, Tao -- ** Tao Zhang Department of Computer Science& Engineering, College of Engineering, Pennsylvania State University

Re: [gem5-users] option "--maxtime" doesn't work?

atch that fixes the problem and put it on the review board? reviews.gem5.org? Thanks, Ali On Apr 8, 2012, at 7:31 PM, Tao Zhang wrote: Dear all, I found that the option "--maxtime (# of second in float)" didn't work once i tried to use it to terminate the simulation. Wh

Re: [gem5-users] What happened to DRAM model?

They have been replaced with "abstract_mem.cc" and "simple_mem.cc". -Tao On 05/13/2012 01:13 PM, Mahmood Naderan wrote: Hi There were some physicalmemory.py , dram.cc and dram.hh files in previous releases. But seems that they are no longer available. Appreciate any comment. _

Re: [gem5-users] What happened to DRAM model?

aram.Latency("6ns", "row cycle delay") num_banks = Param.Int(4, "Number of Banks") num_cpus = Param.Int(4, "Number of CPUs connected to DRAM") But seems that it has been removed. So it is no longer possible to set some DRAM parameters. On 5/13/12,

Re: [gem5-users] Full System on Mac OS

Hi Wael, Can you try it on a virtual machine? The Oracle VirtualBox can easily run a linux (Fedora) and do what you want. It's fast enough to create a image. Well, my experience is based on a file system image rather than the whole disk image. Hopefully it can be considered though... Tao On

Re: [gem5-users] Problem with ruby

in "config.ini", you can make sure whether the L2 controller is there. The command is wrong. it should be "PROTOCOL = MOESI_CMP_token" rather than "TOPOLOGY=MOESI_CMP_token" Tao On 05/18/2012 01:04 PM, Hamid Reza Khaleghzadeh wrote: I have compile Gem5 as following: scons ~/build/ALPHA/gem5

[gem5-users] replacing simple memory with DRAMSim2 (patch released)

Tao -- ****** Tao Zhang Department of Computer Science& Engineering, College of Engineering, Pennsylvania State University 354B IST Building University Park, PA 16802 (Office) 814-863-1047 (Mobile) 814-321-4826 Homepage: www.cse.psu.ed

Re: [gem5-users] replacing simple memory with DRAMSim2 (patch released)

Hi Manmohan, The problem is that I put the assert() before the doAtomicAccess(), which didn't set the packet to "response" yet. I didn't test the code under gem5.opt while gem5.fast disabled the assertion. I have fixed it and updated the patch. You can re-download it. Please let me know if you

[gem5-users] problem in running multiple SAME sepc2006 benchmarks under SE mode

Dear all, I was trying to run multiple SAME spec2006 benchmarks under SE mode. For example, I employed 4 cores and each core run bzip2 independently. When I used fastforward "-F" and maximum instruction "-I", the whole simulation terminated exactly after the CPU switching. It seems like the swi

Re: [gem5-users] problem in running multiple SAME sepc2006 benchmarks under SE mode

me the physical address range to accommodate each benchmark is still different since gem5 generates 4 process stacks with different address mapping. Is it correct? Thanks a lot! Tao On 10/03/2012 11:24 AM, Nilay Vaish wrote: On Wed, 3 Oct 2012, Tao Zhang wrote: Dear all, I was trying to r

Re: [gem5-users] problem in running multiple SAME sepc2006 benchmarks under SE mode

Oct 2012, Tao Zhang wrote: Hi Nilay, Maybe I didn't make it clear. What I want is to run Multi-programmed simulation rather than multi-threaded simulation. In other words, I want 4 cores to run 4 benchmarks (though they are all same) and each core has only 1 thread. As a result, I set "n

Re: [gem5-users] problem in running multiple SAME sepc2006 benchmarks under SE mode

continue; } ... } } On 10/04/2012 12:43 PM, Nilay Vaish wrote: There are specific comments inline. Overall, I think you need to have a better understanding of the options that you are trying to work with. On Thu, 4 Oct 2012, Tao Zhang wrote: Hi Nilay, Maybe

Re: [gem5-users] Cache Hit & Miss latencies

In configs/ruby/, there are several configuration files for each coherence protocol (i.e., MESI_CMP_directory.py). The cache latency is set in those files. Actually, the base class RubyCache has several latency parameters you can use(i.e., dataAccessLatency, tagAccessLatency). See its definitio

Re: [gem5-users] Cache Hit & Miss latencies

Hi Anthony, I think these two files are limited to the classic memory system but not Ruby. Tao On 10/05/2012 09:29 AM, Anthony Gutierrez wrote: Try looking at the Caches.py and CacheConfig.py files. -Tony On Fri, Oct 5, 2012 at 9:27 AM, Pavlos Maniotis > wrote:

Re: [gem5-users] Cache Hit & Miss latencies

ncy". I am looking for a more complete and accurate way to configure cache behavior. Pavlos On Fri, 2012-10-05 at 09:40 -0400, Tao Zhang wrote: Hi Anthony, I think these two files are limited to the classic memory system but not Ruby. Tao On 10/05/2012 09:29 AM, Anthony Gutierrez wrote: Try

Re: [gem5-users] problem in running multiple SAME sepc2006 benchmarks under SE mode

un...@gem5.org] *On Behalf Of *Tao Zhang *Sent:* Thursday, October 04, 2012 7:13 PM *To:* gem5-users@gem5.org *Subject:* Re: [gem5-users] problem in running multiple SAME sepc2006 benchmarks under SE mode Finally, I fixed the problem. This is a gem5's bug when using both "-I"

Re: [gem5-users] problem in running multiple SAME sepc2006 benchmarks under SE mode

exitTimesWithinOneCycle++; std::cout << "This is the " << exitTimesWithinOneCycle << " exit events!" << std::endl; continue; } ... } } On 10/04/2012 12:43 PM, Nilay Vaish wrote: There are specif

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